powerplanning
DESCRIPTION
https://www.udemy.com/vlsi-academy Usually, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. But on a chip, it becomes necessary to have a grid structure of power, with more than one 'vdd' and 'vss'. The concept of power grid structure would be uploaded soon. It is actually the scaling trend that drives chip designers for power grid structure.TRANSCRIPT
Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.
Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• Partition and synthesize larger designs into smaller modules consisting of IP’s and std cells
Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• Define width and Height of ‘core’ and ‘Die’ using the physical area of synthesized netlist, utilization factor and aspect ratio
Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• Define locations of pre-placed cells
Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• Place de-coupling capacitors surrounding pre-placed cells
Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• Power Planning
Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• IO Pin/Pad placement
• We have defined the Width and Height of the core.
• Also defined the locations of pre-placed cells.
• We have encapsulated the Pre-placed Cells by Decoupling capacitor.
• We will do the Power Planning for the Chip
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• If observed, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom.
• But on a chip, it becomes necessary to have a grid structure for power source, with more than one 'vdd' and 'vss‘.
Power Planning
Power Planning is to connect each cell in the design to the power source i.e. VDD and VSS.
We will convert the power lines into the Power Mesh.
Block a Block b
Block c
Core
Die
Pre-placedCells DECAP2
DECAP1D4
DECAP3
Block a Block b
Block c
Core
Die
DECAP2
DECAP1D4
DECAP3
Block a Block b
Block c
Core
Die
DECAP2
DECAP1D4
DECAP3
Vss
Vdd
Block a Block b
Block c
Core
Die
DECAP2
DECAP1D4
DECAP3
Vss
Vdd
Block a Block b
Block c
Core
Die
DECAP2
DECAP1D4
DECAP3
Vss
Vdd
Block a Block b
Block c
Core
Die
DECAP2
DECAP1D4
DECAP3
Vss
Vdd
Block a Block b
Block c
Core
Die
DECAP2
DECAP1D4
DECAP3
Vss
Vdd
Contact
Block a Block b
Block c
Core
Die
DECAP2
DECAP1D4
DECAP3
Vss
Vdd
Contact
Block a Block b
Block c
Core
Die
DECAP2
DECAP1D4
DECAP3
Vss
Vdd
Contact
The Power mesh will look as below.
Vss
Vdd
Contact
Block a Block b
Block c
DECAP2
DECAP1D4
DECAP3
Vss
VddCore
Die
Contact