need for power aware methodology

8/8/2019 Need for Power Aware Methodology

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idesign

Published in issue of Chip Design Magazine

The Need for Package-Aware Methodology for ICDesign

A package-aware chip design methodology

gives designers a much-needed one-pass

package design flow, helping to deliver products

to market on time.

By Joel McGrath, Technical Marketing Manager, Rio Design Automation

IC design and package design are not performed concurrently today, but

they should be. Today's chips have more pins, more I/O, mixed analog anddigital technologies, more power domains, higher frequencies, more

demands on power plane integrity, and issues related to simultaneousswitching output (SSO). All of this contributes to a designer's inability to

successfully deploy the chip on its package.

As the industry moves to smaller process geometries, it's become clear that

chip designers must be able to design chips that are both system-aware andpackage-aware. Fundamentally, they need a way to visualize and explore

the chip in the package. This means performing early analysis, designoptimizations, and tradeoffs in different environments where a signalpropagates through the die, the package substrate, and the PCB.

For package-aware chip design to be most effective, it needs to take place

during the initial stages of the design. It is during these early stages whendesign tradeoffs can be made and the benefits of such tradeoffs fully

realized. Like the foundation of a building, good I/O planning and

intelligent decisions result in a more solid design that meets expectations.

In order to enable this intelligent decision-making process, insight into theenvironment beyond the silicon boundaries must be made available.

Without this visibility during I/O planning, designers must rely on rule of

thumb decisions that are geared "not to fail" rather than optimized for thatparticular design. This can lead to a more complex, cost-burdened finished


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product that may not meet market requirements.

This lack of visibility can also lead to bad assumptions whereby the finaldesign simply cannot meet performance requirements. This is especiallyproblematic with power delivery. Imbalanced or inadequate package power

distribution networks can cripple the performance of high-speed designs.

Quite often, these problems are not uncovered until the verification phase.

In many cases, the only option is to redesign the package leading to weeksof delay and a missed time-to-market window.

For flip chip devices, exploration of various I/O placement, redistribution

layer (RDL), and bump patterning is essential to design optimization. Incore-limited designs, where the die size limit is fixed, design convergence

can be a challenge (Figure 1). In this case, the ability to implement an I/O

synthesis step in the context of the package can result in greater utilizationof the I/O area. This frees up valuable real estate for core expansion without

increasing the overall die size. To be effective, this step must take package

escape routing into consideration, and this can only happen when the chipand package are present in the same design environment.


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Figure 1: Core limited example

In the case of a pad-limited design, the core size is small, but the I/O countis proportionally high; this results in under-utilized die area, which can

drive up cost (Figure 2). I/O synthesis in this scenario would enable

exploration of various bump pitches and I/O stacking combinations whileassuring escapability in the package. As a result, better utilization of die

area could lead to a reduction in die size and final cost.

Figure 2: Pad limited example

Another key advantage to package-aware chip design is the ability to

simulate actual design interconnects rather than estimating an arbitrary load

for the package. When the chip and package are simulated together asthey will exist in the real world a more accurate picture emerges.

Currently this chip/package co-simulation occurs only as part of the finalverification step and not as part of a concurrent flow. This can severely

limit the designer's ability to accurately determine what the signal behavior

will look like once the chip is assembled in the package.


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Of even greater concern with high-performance devices is the ability to

predict the power delivery network. Without actual package data to workwith, it is not possible to accurately understand the impact of plane

discontinuities on signal performance. And, with the voltage level oftoday's chips going down and the current density going up, the powerdistribution network needs to be optimized. That will ensure that enough

current is being delivered to the die at the proper impedance level.

Otherwise, voltage fluctuations can have an impact with regard to meeting

performance targets.

Lastly, package-aware concurrent design can have a direct impact in the

overall design cycle times. With the nearly serial design flow in use today,

package designs do not even commence until late in the cycle (Figure 3).This leads to compressed design timelines where potential cost savings and

tradeoffs are sacrificed due to the need to get first articles manufactured in

time for the chips coming out of the fabs. Additionally, it often requirescompanies to pay a premium in non-recurring engineering (NRE) tooling

charges to fast-track delivery of these first articles.

Figure 3: Traditional flow


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Implementing a concurrent design flow, package design can begin much

earlier and any issues, such as problematic bump to ball assignments can beaddressed before final design, thereby avoiding any schedule delays and

achieving a one pass flow for package design (Figure 4).

Figure 4: Co-design flow

In summary, implementing a package-aware chip design methodology is an

essential step with today's high speed devices. Benefits of such a

methodology are numerous and will influence the ability to achieve optimal

performance at the lowest possible cost. It will ensure predictable powerdelivery and greater use of the die area. A concurrent design flow will help

assure timely first article delivery. A package-aware chip design

methodology gives designers a much-needed one-pass package designflow, helping to deliver products to market on time.

Such a methodology is long overdue. Shouldn't you be looking at this

revolutionary approach to chip design?


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-----------------------

Joel McGrath is the Technical Marketing Manager for Rio Design

Automation (www.rio-da.com) in Santa Clara, Calif. Before joining Rio,

Joel was director of IC Packaging development at Mentor Graphics.Previously, Joel was a senior marketing manager at Cadence Design

Systems for seven years, responsible for its IC Packaging tools. Prior to

joining Cadence, he worked at Digital Equipment Corp for 10 years as aprinciple IC packaging engineer for Alpha microprocessors.
http://www.rio-da.com/http://www.rio-da.com/

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