multilevel logic minimization

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370 IEEE TRANSACTIONS ON EDUCATION, VOL. 38. NO. 4,NOVEMBER 1995

Multilevel Logic MinimizationUsing K-map XOR PatternsRichard F. Tinder

Abstruct4ntered variable XO R patterns are used in com-pressed Karnaugh maps to achieve gate-level minimum functionsnot possible wi th standard SOP and POS forms. Proceduresare given for minimum cover extraction and Verification. Thedesign of a simple ALU illustrates multilevel-multiple outputoptimization.I. INTRODUCTION

OMBINING entered variable (EV) subfunctions andC OR patterns in a Karnaugh map (K-map) extractionprocess [3] is a special and powerful form of K-map multilevelfunction minimization. Used with two-level logic forms (ANDand OR functions) this multilevel minimization approach leadsto XOIUSOP, EQVPOS and hybrid forms that often representa substantial reduction in the hardware not possible other-wise. XOWSOP and EQVROS forms are those connectingp-terms with XOR operators or s-terms with EQV operators,respectively. Hybrid forms are those containing a mixture ofthese.

Conventional (1s and 0s) K-map methods involving XORpattems have been used to obtain coefficient values for Reed-Muller XOR expansions [4]. Such methods have been shownto provide minimum fixed-polarity solutions to such expan-sions. Sasao [2 ] has shown that the use of conventionalK-maps together with Boolean manipulation can be used toyield a XOIUSOP minimum for some functions. Except forthe work cited in [3 ] no other published work is known toexist on the subject of logic minimization using EV K-mapXOR patterns.

In the past the XOR gate (or EQV gate) has been viewedas a two-level device, meaning two units of path delay.Thus, its use with other gates, including other XOR or EQVgates, resulted in multiple units of path delay, hence the termmultilevel. Also, XOR logic was known to be expensive,hardware-wise. But the emergence of CMOS IC technologyhas moved the XOR and EQV gates close to single levelgates with respect to compactness and speed [3]. Furthermore,the arrival of FPGAs and FPLDs has made XOWSOP andEQV/POS based logic synthesis practical [2].In this article it will be shown how simple pencil-and-paper methods can be used to extract gate-minimum mul-tilevel logic designs not yet possible by any other methodincluding the use of CAD techniques. The methods describedin this article make possible multilevel IC designs that occupymuch less real estate than would be possible for an equivalent

Manuscript received October 16, 1993; revised June 29, 1994.The author is with the School of Electrical Engineering and ComputerIEEE Log Number 9415004.Science, Washington State. University, Pullman, WA 99164-2752 USA.

two-level design, and often with little or no sacrifice inspeed-an advantage for VLSI design.

Inherent in the K-map extraction methods and the verifica-tion of results that follow are the well known SOP and POSdefining relations for the XOR and EQV functions [3]

a $ b = j L . b + a . $ S O P (1)a 0 =(a +b ) ( a+b ) ( 2 )a @ b = l i . b + a . b SO P (3)a @ b =(a+$ ) ( a+b ) (4 )

Here, (1) and (2 ) are logic duals, as are (3) and (4). Alsoimportant to verification of the K-map extraction results aretwo corollaries or lemmas of XOR algebra that express theinterchangablility of the operators [11431

Corollary I allows that if any two p-terms, a and P , of afunction never take logic 1simultaneously (hence are mutuallydisjoint), then

POSPOS.

a . P = O and a f % P = a + P . ( 5 )Corollary ZZ by duality, permits that if any two s-terms, a

and /?, f a function never take logic 0 simultaneously, thena + / 3 = 1 and a@ / ? = a . P . (6)

Also used in verification of multilevel XOR forms are thedistributivity laws in XOR algebra 131 given by

( a . ) $ ( a . c ) =a . b @ c )( a+6 )0 U+c ) =a +( b0 ) ( 7 )(8)

which are seen to be logically dual relations. Equation (7) canbe called the factoring law of XOR algebra.

Where appropriate to do so, reference will be made toexpressions (I) --@) n discussions that follow. Reference willalso be made to MINTERM code (logic 0 for a complementedvariable and logic 1 for an uncomplemented variable), and toMAXTERM code which is the dual of MINTERM code. Forexample, expression (1) and (3) are used with MINTERM codewhile expressions (2 ) and (4 ) are used with MAXTERM code.

11. XOR TYPEPAlTERNS AN DEXTRACTIONF GATE-MINIMUMOVER

There are four types of XOR patterns that can be easily1) Diagonal pattems2) Adjacent pattems3) Offset pattems4) Associative pattems.

identified in EV K-maps. They are

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TINDER: MULTILEVEL LOGIC MINIMIZATION USING K-MAP XOR PATTERNS 371

Of these, only the offset pattern requires third and higher orderK-maps for its appearance. K-maps used in the followingdiscussions are all MINTERM code based, but are used toextract gate-minimum functions in both MINTERM code andMAXTERM code.

Simple examples of the first three patterns are shown inFig. l(a) where a six variable function has been compressedinto a third-order EV K-map. Empty cells 0 and 2 in Fig. l(a)are to be disregarded so as to focus attention on the patterns:The diagonal pattern formed by cells 1 and 4 is read inMINTERM code as B X ( A @ C) or in MAXTERM code asB +X +A C . Notice that the diagonal pattern lies in theB domain ( B domain in MAXTERM code) "for all that isX , " and that defining relations (1) and (2 ) are used for cells 1and 4 to give A @ C and A @ C, respectively, for MINTERMcode and MAXTERM code. The adjacent pattern is formed bycells 3 and 7 and is read BC(A @2 ) n MINTERM code or asB+C+ A O2 in MAXTERM code. Here, the adjacent patternlies at the intersection of domains B and C in MINTERM code(B+C in MAXTERM code), and defining relations ( 3 ) and(2) are used to obtain the MINTERM and MAXTERM codeextraction, respectively. The offset pattern is formed by cells5 and 6 and is read in MINTERM code as A Y ( B@C )and inMAXTERM code as A +Y +B @ C. In this case, the offsetpattern lies in the A domain ( A n MAXTERM code) "for allthat is Y," nd the defining relations (1) and (2) are used forcells 5 and 6 to obtain B @ C and B 0 C, respectively.

Each of the three XOR type patterns extracted fromFig. l(a) has a gatelinput tally of 215 (excluding inverters). Thegatehput ta l ly is a measure of logic circuit cost (in hardwareand real estate). It is defined as the ratio of the total numberof gates to the total number of gate inputs including internalgate inputs and, unless stated otherwise, will exclude invertersand their inputs. Then, by comparison, the two-level logicgatelinput tally for each is 318. Throughout this discussion itis assumed that any entered variable, for example X ,Y or 2,may represent a multivariable term of any complexity.

Associative patterns may combine with any or all of theother three patterns thereby forming compound patterns. Forthis reason associative patterns require special considerationand will be dealt with in the next section.A . Extraction ofCover From EV

Gate-Minimum XO R PatternK - m a p s

Before illustrating the extraction process by example, itwill be instructive to outline the extraction procedure. Inthis procedure reference will be made to MINTERM andMAXTERM codes. Since all K-maps are MINTERM codebased, extraction of EQVPOS cover from them requires thatthe K-map domains be complemented, but not the enteredvariables [ 3 ] .Extraction of XOWSOP cover follows conven-tional procedure. The following six step extraction procedureapplies generally to all four types of XOR patterns.Extraction Procedure

Step I : Identify the type of EV XOR pattern that exists inthe K-map. A diagonal pattern requires identical K-map cell

Fig. 1.adjacent and offset pattems. (b), (c), and (d) Associative pattems.Examples of XOR pattems in compressed I


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372 IEFE TRANSACTIONS ON EDUCATION, VOL. 38, NO. 4, NOVEMBER 1995

and is seen to be a two-level function. Here, according to StepI11 of the extraction procedure, the associative XOR patternis extracted in MINTERM code in SOP form with X ocatedin the A domain, hence A .X. he EXOR/SOPorm can beconverted to the EEQVIPOSorm by single complementationas shown, or can be read in MAXTERM code directly fromthe K-map.

The function F in the second-order K-map of Fig. l(c) isread in MAXTERM code, according to Step I11 and is given by

FEQVIPOS[ ( B+ o I .Awhich is a three-level function. In this case the EQV con-nective associates the E in cells 0 and 2 (hence B +Y inMAXTERM code) with the X in all four cells. The remainingPOS cover in cell 0 is extracted with the dont care ($) in cell1 by ANDing the previous result with A as required by Step(IV) in the extraction procedure.

The function G in the third-order EV K-map, shown inFig l(d), is also read in MAXTERM code. Here, the EQVconnective associates the X s in cells 0, 1, 4 and 5 (thusB +X in MAXTERM code) with the Y s in cells 5 and 7(hence A +C +Y) iving the resultwhich is also a three-level function. The term ( A+C +X )removes the remaining POS cover in cells 4 and 6, as requiredby Step IV.

The two-level minimum results for ESOP,POSnd Gposare

Esop =X Y +A X Y +A YFpos =( X +Y ) ( B+X +Y ) ( B+X ) AGpos =( B+X +Y ) ( A+G + X +Y ) ( A+C + X ). ( A + B +X ) ( A+B +X +Y ) .The use of associative patterns often leads to significant

reduction in hardware compared to the two-level SOP andPOS forms. For example, function E x o R p ~ pas a minimumgatelinput tally of 214 compared to 4/10 for ESOP, the two-level SOPminimum cover. The gatelinput tally for FEQVIPOSis 316 compared to 4/11 for the Fpos cover, and functionGEQV/POS as a minimum gatehnput tally of 4/12 comparedto 6/22 for GPOS, the two-level POS minimum result, allexcluding inverters.

XOR patterns may be combined very effectively to yieldgate-minimum results. Shown in Fig. 2(a) is a second-ordercompression where diagonal, adjacent and offset patterns areassociated in MINTERM code by the XOR operator in cell1. Here, (1) is applied to the diagonal pattern (cells 1 and 4)in the B domain for all that is X to yield B X ( A@ C). Thispattern is then associated with the intersection (ANDing) ofthe adjacent pattern ( A0 ) nd the offset pattern ( B@ C) incells 1, 2, 5 and 6 to give the gate-minimum, three-level result

HXOR/SOP =[ B X ( A@ c)] [ ( A Y ) ( B@ c)]

101 o I o I o I \ Z I/J

(C)Fig. 2. Examples of complex XOR pattems. (a) Combined XOR typepattems. (b) and (c) Compound associative patterns.

while (1) is applied to the offset pattern (Y and Y in the BCdomain, and P and Y in the BC domain). This is comparedto the two-level result

Hsop =ABCXY +A B C X +ABCY +B C X Y+A B C Y +A B C Ywhich has a gatehnput tally of 7/31.

Compound (interconnected) associative patterns are alsopossible and may lead to gate-minimum functions, althoughoften of a higher level (hence slower) than those wherethere is no interconnection between associative patterns. Twoexamples are given in Fig. 2(b) and (c), both third-ordercompressions (hence three EVs). Function I is extracted inMAXTERM code yielding the four-level, gate-minimum result

which has a gatehnput tally of 7/14. Extraction involves theassociation of an adjacent pattern and a diagonal pattern withthe three EQV connectives. The adjacent pattern in domain B(cells 0 and 2) requires the use of (4)o give [B+ A@ X ) ] .This is associated with the diagonal pattern in cells 0 and 3 byusing (4) for all that is Y to give [Y+( A@ B ) ] , ut is alsoassociated with the cell 3 connective in domain A for all thatis 2.Notice that the terms in square brackets are commutative.For comparison purposes the two-level POS result for functionI is given by

Ipos =( A+B + X+Y ) ( A+B +X + Y ). ( A+B +x +Z ) ( A+B +X +2). ( A+B+Y +Z ) ( A+B +Y+2 )

and has a gatehnput tally of 7/30.giving the four-level, gate-minimum result

The function J in Fig. 2(c) is extracted in MINTERM codeJXOR/SOP =[D(BO ) ( AO C ) ]@ [ B ( A@ X ) ( CO D ) ]

@ [C(Do ) ( Ao ) ]with a gatelinput tally of 6/13. Equation (3) is used for theadjacent pattern (Y n the A domain and Y in the A domain) with a gatehnput tally of 11/25. This function is extracted asthree sets of two intersecting patterns all associated by the



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TINDER: MULTILEVEL LOGIC MINIMEATION USING K -MAP XOR PATTERNS 313

TABLE IGATE~INPIJTALLIESNCLUDING INVERTERS FOR FUNCTIONSE , F , G, H, I AN D J REPRESENTED AS MULTILEVELXO R LOGIC ORMS N D AS TWO-LEVEL LOGIC FORMS

three XOR connectives. The 2 set consists of adjacent anddiagonal patterns given by (3 ) as (B 2 ) and ( A @ C),respectively, which intersect (AND) in the D domain. TheX set consists of adjacent and offset patterns given by(1 ) and (3 ) as ( A@ X ) and (C 0 D), respectively, whichintersect in the B domain. Finally, the Y set also consistsof adjacent and offset patterns such that (3) yields ( D @ Y )and ( AO B ) , espectively, which intersect in the C domain.As in the previous example, the terms in square brackets arecommutative. In comparison the two-level SOP minimum forfunction J is given byJsop =ABCDXY +ABCDYZ +A B CD Z +ABCDY+ABCDY +ABCDX +ABCDX +ABCDZ+ACDXZ +BCDXZ +BCDXY +ACDYZand has a gatehput tally of 13/74.

Both four-level functions, I E Q V p O S and JXOR/SOp areeasily verified by introducing in turn the cell coordinates foreach into the expression. Generation of the subfunctions ineach cell validates the extraction process.

The gatehnput tallies for all five functions represented previ-ously were given exclusive of inverters. When account is takenof the inverters required for inputs assumed to arrive activehigh, the gatehnput tally differentials between the multilevelresults and the two-level results increases significantly. Thesegatehnput tallies are compared in Table I.

There are still other factors that may increase significantlythe gatehnput tally differential between multilevel and stan-dard two-level SOP and POS minimum forms. These includegate fan-in restrictions, static hazard cover and multiple outputoptimization considerations. For example, if active high inputsare assumed for function J , six p-terms must be added to thetwo-level SOP result to cover eleven possible static hazards,and given likely fan-in restrictions (there are now 18 p-terms for the two-level result), the differential in gatehnputtallies between the Jsop and JXOR,ISOP orms is expectedto widen considerably. Work is in progress on the analysisand elimination of static hazards in multilevel XOR formsand will be presented in a future paper. For logic familiessuch as CMOS, propagation delay is increased significantlywith increasing numbers of gate inputs, and it is here wherethe multilevel XOR forms often have a distinct advantageover their two-level counterparts. For example, the largestnumber of inputs to any gate in the implementation of functionJ XOR I SO ~s three whereas for the two-level function Jsopit is 12 without hazard cover. An example of how multipleoutput optimization considerations may further increase the

gatehput tally differential between the multilevel and two-level approaches to design is given in Section 11-D.

B. Algebraic Ver$cation of Optimal XORFunction Extraction From K-maps

Verification of the multilevel XOR forms begins by directK-map extraction of the function in SOPor POS form by usingMINTERM code for XOR connectives and MAXTERM codefor EQV connectives. It then proceeds by applying corollary I(5) or corollary II (6) together with distributivity, commutivityand a defining relation given by (1)-(3) or (4).

As an example, consider the function H in Fig. 2(a) whichis extracted in MINTERM code. Verification of this functionis accomplished in six steps

H =ABC(X @ Y) ABCX +ABCY+ABCY +ABCY Step 1 From K-map@ (ABCY)@ (ABCY) Step 2 By (5 )

Step 3 By (7 )( A B CY)@ ( A B CY)

@ [ B C { ( A Y ) ( A Y ) } ] Step 4 By (7 )Step 5 BY(3 , 7), (1) and (3 )

Step 6 By (7 ) and (1).

=[ABC(X@ Y ) ] ( A B C X )@ ( A B CY)

=( A B CX )@ ( A B C Y )@ ( A B CX )@ (ABCY)=[B X {( A C) ( A C) }] [BC{(AY) ( A Y ) } ]=[ B X ( A C)]@ [BC(Ao Y ) ] [ B C ( AO Y ) ]=[ B X ( A@ C ) ]@ [ ( A0 ) ( B@ C ) ]

Notice that in going from step 3 to step 4 the commutativelaw of XOR algebra [3 ] is used.As a second example, consider function I in Fig. 2(b) whichhas been extracted in MAXTERM code. Verification of thisfunction is also accomplished in six steps

I =( A+B + X o Y ) ( A+B +X o Z ).( A+B +Y O 2 )0 A+B +Y 0 )

Step 1 From K-map

Step 2 By (6)=( A +B + X O Y ) o ( A + B + X Z )=( A+B +X ) o ( A+B + Y )o ( A+B +X)0 A+B +2 )0 A+B +Y )O ( A+Bz +2 )

Step 3 By (8)Step 4 By (8)

Step 5 By (6)Step 6 By (4).

=[B+( A + X )O A+X ) ]0 Y+( A+B )0 A+ B ) ]=[B+( A+X ) ( A+X)] [Y+( A+B ) ( A+B ) ]=[ B+( A@ X ) ]O [Y+( A@ B )]0 A+Z]0 A+z+B0 ) ]0 A+Z ]

In going from step 3 to step 4 commutivity was applied beforeapplication of (8). Also, in step 4, B 0 =0.



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374 IEEE TRANSACTIONS ON EDUCATION, VOL. 38, NO. 4,NOVEMBER 1995

C . K-map Plotting and Entered Variable XO R PatternsAt the onset let it be understood that one does not usually

hunt for applications of the XOR pattern minimization meth-ods described here. It is possible to do this, as the example inthis section illustrates, but it is more likely that such methodswould be applied to EV XOR patterns that occur naturallyin the design of a variety of combinational logic devices.Examples of these include a 2 x 2 bit fast multiplier,comparator design, gray-to-binary code conversion XS3-to-NBCD code conversion, ALU design of the type illustratedherein, binary-to-2s complement conversion, and NBCD to84-2-1 code conversion, to name but a few [3]. EV XORpatterns may also occur quite naturally in the design of somestate machines as, for example, the design of a three-bitupldown Gray code counter [3].

EV K-map plotting for the purpose of extracting a gate-minimum cover by using XOR patterns is not an exactscience, and it is often difficult to find the optimum K-mapcompression involving specific EVs, hence specific K-mapaxis variables. However, for some functions it is possible toplot the map properly directly from the canonical form, asillustrated by the example that follows. It is also possible in acombinational logic design to optimally arrange the entries inan EV truth table to best suit the formation of XOR patterns,but this is more the exception than the rule. The design of anALU in the next section is such an example.

For some relatively simple functions, the K-map plottingprocess can be deduced directly from the canonical expression.Consider the simple function given in canonical code form

\n

f(W,X , Y , Z )=C m ( l , 2 , 3 , 6 , 7 , 8 , 1 2 , 1 3 ) .Shown in Fig. 3 are the conventional (1s and 0s) K-mapand the second-order compression (two EVs) K-map deriveddirectly from the conventional K-map. The two-level SO Pminimum and the multilevel XOWSOP gate-minimum formsare

fS0P =WXZ+W X Y +WYZ+W Yand

which have gatelinput tallies of 5/15 and 317, respectively.The second-order K-map in Fig. 3(b) is deduced directly fromthe K-map in Fig. 3(a) by observing that W @ X exists inthe Y Z = 01 column, with W and ii located in adjacentY Z columns. Thus, by taking Y and Z as the axis variablesand W and X as the EVs for the compressed K-map theXOR patterns appear allowing one to easily extract gate-minimum results. Only in one other compressed K-map arethe gate-minimum XOR patterns obvious, and that is shownin Fig. 3(c). In all four other compressed K-map possibilities,those having axes W / X , / Z ,W / Z and W / Y , he XORpatterns shown in Fig. 3(b) and (c) disappear making a gate-minimum extraction without extensive Boolean manipulationvery difficult if not impossible. Notice that the compressed

1

(b) (C)Fig. 3. Compressed K-maps, suitable for extraction of gate-minimum XORforms, deduced from a conventional (1s and 02) K-map. (a) ConventionalK-map for the function f . (b) Second-order compression K-map deducedfrom the K-map in (a) showing XOR patterns. (c) Alternative second-orderIC-map.

K-map in Fig. 3(c) is not easily obtained from the that ofFig. 3(a).For complex functions involving five or more variables,

the process of generating a gate-minimum result by usingXOR EV patterns becomes increasingly more a matter of trialand error as the number of variables increases. Again, theapplication of the EV XOR pattern approach to design is leftmore to the natural occurrence of such patterns than it is tothe hunt-and-choose method. However, if it is suspected thatXOR patterns occur naturally in a given function and if one isfamiliar with conventional (1s and 0s) K-map methods forfive or more variables, it is possible to deduce a compressedK-map that will yield XOWSOP or EQVPOS forms, butwhich may not represent gate-minimum functions.D. A Simple Design Example

As an example of multilevel optimization, a simple 1-bitslice arithmetic logic unit (ALU) is designed by using themultilevel XOR approach. The operation table for the ALU isshown in Fig. 4(a) where the eight operations are optimallyplaced. Here, A and B are the data inputs, Ci and COarethe carryin and carryout, F represents the resultant function(arithmetic or logic), and M , S1 and SOand are the operationcontrols, all applying to each stage of the ALU. Subtraction iscarried out in 2s complement and the LSB Ci is the carryinto the least significant bit stage of the ALU.The function F and carryout CO re compressed into thesecond-order EV K-maps shown in Fig. 4(b) and (c), eachrepresenting a fourth-order compression (hence, four EVs).Both are extracted in MINTERM code giving the optimumfour-level results

&OR/SOP =( A@ So) CB (MCi) E ( S I B )+MS iBCOXOR/SOP =C i ( A @ SO)@ (SIB)f (SlB)(A@ SO)

with a combined gatehnput tally of 10121. Here, terms A@ SO,SIB and ( A @ So)@ ( S I B ) re seen to be shared betweenfunctions F and CO, form of multioutput optimization. In



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TINDER: MULTILEVEL LOGIC MINIMIZATION USING K-MAP XOR PATTERNS 315

1 1 1 1 I x + B

(b) (C)Fig. 4.K-map and optimum multilevel cover for carryout Co.Design of a simple ALU. (a) Operation table. (b) Compressed EV K-map and optimum multilevel cover for function F. (c) Compressed EV

comparison, a two-level SOP optimization yields a combinedgate/input tally of 22/102 (with no shared prime implicants),excluding inverters and placing no limit on number of gateinputs. If active high inputs and NAND logic are assumed,the presence of inverters would increase the gatelinput talliesto 11/22 and 28/108, respectively, for the multilevel and two-level optimized results. Then, if five additional p-terms mustbe added to the Fsop result to cover seven static hazards,the gate/input tally for the two-level result becomes 33/137.(The functions F x o ~ p o p nd COXORISOPave but threestatic hazards each). Finally, if gate fan-in restrictions apply,the gatehnput tally differential is greatly increased betweenthe multilevel XOR/SOP and two-level SOP results. Note thatgate-minimum cover for F requires an additional term, MS 1B[or M ( A @ S o ) ] ,o cover what remains in cell 3 after extractingthe ( A @ So) @ B portion in cell 1 from the ( A @ So)+Bterm in cell 3.

Future work should include computer algorithms that willautomate the multilevel minimization process described in thiswork. Given the complexity of many of the patterns, it will notbe easy to accomplish this. Furthermore, such algorithms mustbe combined with suitable two-level minimization algorithmssince XO R multilevel results often involve a two-level SOPor POS component.

REFERENCES[ l ] D. L. Dietmeyer, Logic Design of Digital Systems. Boston: Allyn andBacon, 1978, p. 118.[2] T. Sasao, Logic synthesis with XOR gates, in Logic Synthesis andOprimizarion, T. Sasao,Ed. Norwell, MA: Kluwer, pp. 259-285, 1993.[3] R. F. Tinder, Digital Engineering Design: A Modem Approach. Engle-wood Cliffs, NJ: Prentice-Hall, 1991, pp. 57-58, 7&73, 116, 15 6161 ,181-183, 211, 219, 24&242, 269-275, 305, 307.[4] X. Wu, X. Chen, and S. L. Hurst, Mapping of Reed-Muller coefficientsand the minimization of exclusive-OR switching functions, Proc. Insf.Elec. Eng., pt. E, vol. 129, pp. 15-20, Jan. 1982.

111. CONCLUSION AND FUTURE WORKuse of entered variable XO R patterns in compressed K ~ -naugh maps is shown to yield gate-minimum results notpossible by conventional mapping methods. The XOR patternmethod is shown to be especially advantageous in the designOf ALUs*This form Of leadsto hardware savings in excess of 50 percent. Furthermore,

Richard F. Tinder received the B.S. degree in chemical engineering in 1955,and the M.S. and Ph.D. degrees in materials science in 1956 and 1962, allfrom the University of California (Berkeley).Since then he has been on the faculty of Washington State University,Pullman, WA, where he is presently Professor of Electrical Engineering andComputer Science. His interests are broadly based, and he has publishednumerous articles in the areas of matter tensor properties, surface physics,shock dynamics, crystalline microplasticity and digital logic design. His cur-

minimizationmultilevel XO R functions are easily tested than theirtwo-1eve1sopOr Os countepmsince a sing1e nput changein a multilevel XO R function forces a function change. Iffan-in restrictions are placed on the two-level result, speedmay even favor the XoR method, pmicularlY forimplementations of the functions.

rent interests include asynchronous programmable sequencers, asynchronousinternally clocked systems, arbiters and metastability, asynchronous sequentialMU S nd multilevel logic design using exclusive-OR forms. He is the authorof DIGITAL ENGINEERING DESIGN: A Modem Appmach (Frentice Hall,1991) and is holder of a 1991 patent, Microprog~ammableAsynchronousControllers for Digital Electronic Systems. In completely unrelated work,he has worked on safety enclosures and systems for high speed vehicles andholds a recent major patent in this area.

multilevel logic minimization

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