minimization techniques for reversible logic synthesis

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Minimization Techniques for Reversible Logic Synthesis

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Page 1: Minimization Techniques for Reversible Logic Synthesis

Minimization Techniques for

Reversible Logic Synthesis

Page 2: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 2

Outline• Why reversible logic?• The building blocks• The synthesis problem• Some solutions• Optimization• Finding identities• Remaining problems

Page 3: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 3

Reversible Logic

• from the output you can determine the input (bijection)

• Why would we want this?

• Landauer's principle: every bit of information lost consumes energy

• k is the Boltzman constant

• T is the temperature

• energy loss is small

kTln2

2.9×10−21 Joule

inputs outputscircuitnetwork

Page 4: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 4

Applications

• Quantum Computing– necessarily reversible

• Low power CMOS– In adiabatic circuits, current is restricted to flow

across devices with low voltage drop and the energy stored on their capacitors is recycled

• Optical Computing• Nano-technologies

– Billiard Ball Model (BBM)

Page 5: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 5

Standard Gates• which ones are reversible?

and

not

xor

or

Embedding anon-reversible function into a reversible one

How many ways?

Page 6: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 6

Reversible Gates• Feynman gate (controlled not)

• Toffoli gate

x

x yy

x

y

xy zz

y

x x

• Generalized Toffoli gate more control lines

Page 7: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 7

Reversible Gates• Fredkin gate (controlled swap)

y

zx’ + yxz

yx’ + zx

x x

• Generalized Fredkin gate more control lines

Page 8: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 8

Restrictions• No fan-out• No back-feeds

Page 9: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 9

Restrictions• No fan-out• No back-feeds

Cascade of Gates

inputs outputg1 g2 gi gi+1 gn-1 gn… …

Page 10: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 10

Function Representation• How do we represent a reversible function?

– truth table

– BDDs

• Is there an easy check to see that the function is reversible?

Page 11: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 11

Synthesis• Given a reversible function find a network of gates

that realize the function• Cost should be near minimal• Possible cost assumptions:

– Each gate has the same cost

– The cost of each gate reflects its actual implementation cost

Page 12: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 12

Approach 1

inputs outputsReversibletransformation

Page 13: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 13

Approach 1

inputs outputsReversibleTransformation

T1

inputs outputsReversibleTransformation

T2

GATE

Page 14: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 14

Conditions• T2 should be “simpler” than T1• How do you measure simplicity?

– Hamming distance

– Spectral techniques

• Questions:– Will it converge?

– How good is the result?

• Improvements – Look ahead

– Backtracking

Page 15: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 15

Approach 2

Input Output

000 000

001 001

010 100

011 011

100 111

101 101

110 010

111 110

Page 16: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 16

Approach 2

Input Output

000 000

001 001

010 100

011 011

100 111

101 101

110 010

111 110

These are correct

Page 17: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 17

Approach 2

Input Output

000 000

001 001

010 100

011 011

100 111

101 101

110 010

111 110

These are correct

Step 1: move up100 to 110

Page 18: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 18

Approach 2

Input Output

000 000

001 001

010 100

011 011

100 111

101 101

110 010

111 110

These are correct

Step 1: move up100 to 110

a

b

c

a

b

c

Page 19: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 19

Approach 2

Input Output

000 000

001 001

010 100

011 011

100 111

101 101

110 010

111 110

These are correct

Step 1: move up100 to 110

a

b

c

a

b

c

Page 20: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 20

Approach 2

Input Output

000 000

001 001

010 100

011 011

100 111

101 101

110 010

111 110

These are correct

Step 1: move up100 to 110

a

b

c

a

b

c

Input Output

000 000

001 001

010 110

011 011

100 101

101 111

110 010

111 100

Page 21: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 21

Approach 2

These are correct

Step 2: move down110 to 010

Input Output

000 000

001 001

010 110

011 011

100 101

101 111

110 010

111 100

Page 22: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 22

Approach 2

These are correct

Step 2: move down110 to 010

a

b

c

a

b

c

Input Output

000 000

001 001

010 110

011 011

100 101

101 111

110 010

111 100

Page 23: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 23

Approach 2

These are correct

Step 2: move down110 to 010

a

b

c

a

b

c

Input Output

000 000

001 001

010 110

110 011

100 101

101 111

110 010

111 100

Input Output

000 000

001 001

010 010

011 111

100 101

101 011

110 110

111 100

Page 24: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 24

Approach 2

Step 2: move down110 to 010

a

b

c

a

b

c

Input Output

000 000

001 001

010 110

011 011

100 101

101 111

110 010

111 100

Input Output

000 000

001 001

010 010

011 111

100 101

101 011

110 110

111 100

Page 25: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 25

Approach 2

Input Output

000 000

001 001

010 010

011 111

100 101

101 011

110 110

111 100

Page 26: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 26

Approach 2

c

b

a

c

b

a

Input Output

000 000

001 001

010 010

011 111

100 101

101 011

110 110

111 100

Page 27: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 27

Advantages/Disadvantages• Always converges• Fast • No look ahead• Several optimizations are possible• May not be optimal• Worst case?

Page 28: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 28

Approach 3• Local transformation• Replace a sequence of gates with another• For example replace 3 gates with 2

Page 29: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 29

Page 30: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 30

Approach 3• Use Identity circuits for local transformations

inputs identityg1 g2 gi gi+1 gn-1 gn… …

Page 31: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 31

Approach 3

inputs identityg1 g2 gi gi+1 gn-1 gn… …

F(X) F-1(X)

Page 32: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 32

Approach 3

inputs identityg1 g2 gi gi+1 gn-1 gn… …

F(X) F-1(X)

Replace this sequenceof gates

Page 33: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 33

Approach 3

inputs identityg1 g2 gi gi+1 gn-1 gn… …

F(X) F-1(X)

Replace this sequenceof gates

with this sequenceof gates

Page 34: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 34

Template Description• As a class - an identity that is not reducible by another

template

• A template may be rotated

• A template may be applied in reverse order

• Size 2 ==> Duplicate gates (may be deleted)

• Size 3 ==> There are none

• Size 4 ==> Passing rule

Page 35: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 35

Template Class — Size 5

A line may be removed

A line may be duplicated

Page 36: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 36

How many classes of identities are there?

Size Identities Classes

1 0

2 1

3 0

4 2

5 1

6 3

7 2

8 16

9 56

Page 37: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 37

The Templates: Application

Page 38: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 38

The quest for identities• Exhaustive searches are not feasible• A feasible approach (to find size n identities):

– Find all functions of size n/2 • With limited number of lines

• With some canonical order

– Pair each function with its inverse

– If no reduction is possible ==> we found a new template

Page 39: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 39

A new approach• Start with an identity that has target lines only• For any subset of gates that preserve the identity a

new control line may be added• Example:

Page 40: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 40

Recent Advances• Automatic template encoding• Application of iterative minimization heuristics• Progress in calculating “real quantum cost”

– Using gates NOT, CNOT, V, and V+

– Quantum templates

• Using SAT to find exact results

Page 41: Minimization Techniques for Reversible Logic Synthesis

Reversible Logic Synthesis Slide 41

Future Work• Handling don’t cares (can be done with SAT)• Billiard ball implementation of reversible circuits

(via cellular arrays)• Better representation for reversible functions

– Truth table is not adequate

– Some form of BDD (possibly Davio)

• Minimization with aid of group theory