616 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 4, APRIL 1994

Modeling Pentode-Like Characteristics of Recessed-Gate Static Induction Transistor

Antonio G. M. Strollo

Abstract-It is described a new analytical model for the pentode-like region of the characteristics of recessed-gate SIT structures. The model allows to investigate the transition from saturating characteristics of long channel JFET’s to nonsaturating behavior of SIT devices, taking into account realistic device geometry.

I. INTRODUCTION

The static induction transistor is a short-channel vertical power JFET device [I], [2], used in linear mode high-frequency amplifiers [3], and in high-power switching converters [4]. The SIT charac- teristics in the so called “triode” region, corresponding to a reverse gate bias larger than punch-through voltage Tb, has been widely investigated in literature [5], [6]. Much less effort has been devoted to the analysis of the second regime of operation of SIT( I T i: I < I>) , corresponding to “pentodelike” characteristics. This is due to the short-channel structure of the SIT which precludes the possibility of using the customary gradual-channel JFET theory. In [7] the lack of sharp saturation in SIT characteristics is qualitatively discussed in terms of reduction of series channel resistance while the theoretical analysis of [SI is developed for an idealized structure, with the gates extending down from source to drain, and assuming constant carriers mobility.

In this brief it is described a new analytical model for the “pentode” region of the SIT characteristics, which takes into account a realistic device geometry, the effect of the drift region and mobility degradation at high electric field.

II. ANALYTICAL MODEL Recessed-gate SIT devices are obtained by using silicon etching to

realize vertically walled gate regions. A simplified schematic of the device is shown in the inset of Fig. 2. The width of SIT elementary cell is indicated as 2C, the channel width as 2.4, the channel length as R, the thickness of the drift region as W .

The drain current is due to electron drift, and is given by ID = 2qBZu ~~1 where Z is the total source stripe length, 2B is the width of the conductive channel in which are confined mobile carriers, n the electron concentration in the conductive channel and t ld the electron drift velocity. Each of B , 1 1 , and I’d may vary with position x along the channel, as a function of both components E , and E, of electric field. In order to simplify the model, we will assume that the mobile carriers are confined in an infinitely thin region along the s axis [SI and that the finite value of I D is supported by a surface-charge density U. The value of U is obtained by performing a straightforward one-dimensional (1D) analysis in the y-direction. The potential contribution at y = 0 produced by U is so calculated as (10 = ~ - 4 / ( 2 c ) . In the same way, the potential at y = 0 produced by the “true” charge distribution (that is, the one produced by a charge

Manuscript received October 8, 1992; revised July 6, 1993. The review of this brief was arranged by Associate Editor T. P. Chow. This work was supported in part by grants from CNR and MURST.

The author is with Department of Electronics Engineering, University of Naples, via Claudio 21-80125, Naples, Italy.

IEEE Log Number 9215825.

density qn in a stripe of width 2 B ) is q’ l = qnB(A - B/2)/c . By equating l;lo and Q1 one has U = q n A [ l - ( 1 - B/d)2] .

The presence of a surface-charge density imposes a discontinuity for the y-component of the electric field and E,(O+) = - 0 / ( 2 c ) . Recalling the expressions of U and I D one obtains the following boundary condition;

where I> = q , V ~ . 4 ~ / ( 2 e ) is the pinch-off voltage and 11 has been assumed equal to the epi doping l Y ~ . The potential distribution in the device is governed by the 2D Poisson equation T29 = - - Q ~ ~ ~ D / E .

Let us start by solving this equation in the “channel region” of the device 0 < y < A, 0 < s < R, see inset of Fig. 2. The boundary conditions for 9 are given by ( I ) and by the following relations:

(2) O ( X . A ) = 1;; - li,, for 0 < s < R

for 0 < y < A. (3)

In (3) the 1D potential profile, including fixed charges contribution, has been assumed as boundary condition for I = 0. T b, is the built-in potential of the gate-epi junction.

In order to solve the Poisson equation, following the approach of [6], the potential distribution is expanded is series of power of y. Considering the first three terms of the series one has o(.r. y ) = CO ( x ) + e1 ( x )y + c2 ( .r)y2. The ( I ) yields the expression for function c1. Then, using (2 ) it is possible to obtain C Z ( S ) as a function of co(.r) and its derivative, cb(x), as follows

1;. - I;, - c o ( x )

A2 c*( . r ) =

where the dependence of I’d upon electric field has been taken into account. The Poisson equation is now evaluated along the x-axis, obtaining:

From (4)-(5) it comes out that co(.r) can be obtained by solv- ing an ordinary differential equation. The first initial condition is simply co(0) = 0; the second one can be written as cb(0) = U d ( O ) / ( p , J l - V ~ ( O ) ~ / V & , ~ ) . The drift velocity at .r = 0 can be obtained by using (3) to calculate c ~ ( 0 ) and substituting the result in (I) , obtaining: l ’ d ( 0 ) = ID/[Z~L\’D~A(~ - ,/(Ti,, - I ~ ; ) / I > ) ] . Equations (4)-(5) can so be solved, for a given value of I D , from x = 0 to x = R, obtaining potential and field distributions along the channel axis of the SIT. A first-order implicit backward difference formula has been used for the numerical integration.

Rearranging (4)-(5) it is possible to express the drain current as

I D = zqLvD2d

From (6) it comes out that the only difference in the present formulation with respect gradual channel theory is the term involving the second derivative of potential distribution. This term takes into

0018-9383/94$04.00 0 1994 IEEE

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 4, APRIL 1994 617

0 10 20 30 X axis [pm]

1

- .OB C E .06 1 U

c

9 04 E 0 02

0 0 5 10 15 20 25 30

Drain Voltage [VI

Fig. 1. Drain output characteristics of SIT in the pentodelike region. dotted bias. liner PISCES simulation. solid line: Analytical model. Inset: Simplified

Normalized .r-component of the electric field for y = 0 at zero gate Fig. 2.

schematic of recessed-gate SIT.

account, In a first-order approximation, the two dimensional effects due to the short-channel SIT structure.

The analysis follows the same approach outlined for the channel region also in the “drift region” of the device: R < s < R + L, 0 < y < C , where L is the depth of the space-charge region of the P+ - gate-epilayer junction. As boundary condition along the line y = C it is assumed the ID distribution: f (s) = T i : -I;, + IC(.r- R ) - l>( . r - R)*/d’, where IC = (Io - 12; + l i , , ) / L + l>L/A2.

The differential equation for the potential distribution along the channel axis is similar to ( S ) , and can be integrated from .r = R to s = R + L , by assuming as initial conditions the ro( R ) and C A ( R ) values obtained from the analysis of the channel region. Finally, lo can be computed as cg( R + L ) plus the resistive drop on the undepleted epilayer region R + L < I‘ < R + IT-. Note that, since f (s) depends upon drain voltage, and I’D is initially unknown, an iterative trial and error algorithm is needed to obtain a self-consistent solution for the potential distribution in the drift region.

111. RESULTS

In order to check the results of the analytical model a number of numerical simulations were performed by using PISCES-I1 [9]. The device used for the simulations has 2 6 = R = 15 pm; 2C = 20 pm; I T - = 15 pm; 2 = 1 cm and ;I’D = lo1‘ ~ m - ~ .

Fig. 1 shows the s-component of the electric field for y = 0. The results of the analytical model are in good agreement with PISCES simulations. For small drain voltage E , is below the limit corresponding to saturated drift velocity (E , = lo4 Vkm), and the electric field peaks at the abscissa s = R. By increasing I O the peak of E, shifts in the drift region; for \/o = 48 V all the drift region is in the saturated drift velocity regime.

Fig. 2 shows a set of 1-1.’ curves computed by PISCES and the corresponding analytical results. A resistive behavior is shown for low drain voltages. For larger I‘D values a pentodelike behavior is observed, although no clear “saturation” region is exhibited in the characteristics (note that in the gradual channel model the I b value corresponding to I D saturation at I;7 = 0 is about 3.4 V for the device considered in this simulation).

The lack of “saturation” region in SIT characteristics is due to both the large channel aspect ratio =I/R (needed for reducing ON resistance) and the low epi doping (required in high breakdown voltage devices). This is clearly shown in Fig. 3, where the drain current at zero gate bias, normalized to ID ( I > - I,$; ), is reported as a function of normalized drain voltage Ib/( I,> - Ii,i). The plots have been obtained for R = IT’ = 15 pm. For :VD = 5 * 10“’ the curves are very poorly saturated; a channel aspect ratio A / R smaller than 1/3 cannot be obtained, in this case, to avoid channel pinch-off at zero gate bias. By increasing the epi doping to LYD = 2 * the 11- curves becomes more “pentodelike” finally, for = 10’“ and d / R < l / d , a sharp saturation is achieved.

2.5

g 2

2

E 1.5

0 1 2 3 4 5 norm Drain Voltage

Normalized drain current l u / I ~ ( 1 >-I i,;) versus normalized drain Fig. 3. voltage 1 -D / (1 > - 1 i,i ) for different epi dopings and channel widths.

ACKNOWLEDGMENT

The author wishes to thank Professors Paolo Spirito and Gianfranco Vitale for stimulating discussions and valuable suggestions.

REFERENCES

111 J. Nishizawa, T. Terasaki, and J. Shibata, “Field-effect transistor versus analog transistor (Static Induction Transistor),” IEEE Trans. Electron Devices, vol. ED-22, pp. 185-197, Apr. 1975.

121 B. J. Baliga, Modern PowerDevices. New York: Wiley, 1987, chap. 5. [ 3 ] I. Bencuya, A. I. Cogan, S. J. Butler, and R. J. Regan, “Static in-

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[4] H. Akagi, T. Sawae, and A. Nabae, “130 kHz 7.5 kW current source inverter using Static Induction Transistors for induction heating appli- cations,’’ IEEE Trans. Power Electronics, vol. 3 , pp. 303-309, July 1988.

[5] C. Bulucea and A. Rusu, “A first-order theory of the static induction transistor,” Solid Stare Electron., vol. 30, pp. 1227-1242, 1987.

[6] A. G . M. Stroll0 and P. Spirito, “A self-consistent model for the SIT DC characteristics,” IEEE Trans. Electron Devices, vol. 38, pp. 1943-1951, Aug. 1991.

[7] Y. Mochida, J. Nishizawa, and T. Ohmi “Characteristics of static induction transistor: effects of series resistance,” IEEE Trans. Electron Devices, vol. ED-25, pp. 761-767, July 1978.

[8] J. A. Guerst, “Theory of insulated-gate field-effect transistors near and beyond pinch-off,’’ Solid State Electron., vol. 9, pp. 129-142, 1966.

[91 “TMA PISCES-IIB, user guide,” Technology Modeling Assoc., Inc., Palo Alto, CA, 1992.