microprocessor presentation

WELCOME RESPECTED TEACHERS

&DEAR FELLOWS

GROUP MEMBERS

SYED WASI SHAH

SYED MOHSIN SHAH

M.SAMI-UL-HAQ HASHMI

MUHAMMAD UMER FAROOQ

SYSTEM CLOCK & BUS CYCLE

1. Definition

2. Clock signal

3. Applications

4. Block Diagram (8284A)

5. Exp of Block Diagram

6. CLK voltage timing characteristics for a 5MHZ processor

7. Pin Diagram (8284A)

8. Explain Pin Configuration

9. Connecting the 8284 to the 8088

10. Relationship between CLK and PCLK

(b). BUS CYCLE AND

TIME STATES

1. Definition

2. Applications

3. Four Time States

4. Idle State

5. Wait State

6. How to read a timing diagram

7. Example of bus cycle

(a). SYSTEM CLOCK OR CLOCK GENERATOR

PRESENTATION LAYOUT

(1) DEFINITION:

A clock generator or system clock is a circuit that produces a timing signal (known as a clock signal and behaves as such) for use in synchronizing a circuit's operation.

1. A clock signal of some frequency generated by system clock, operates the microprocessor on that frequency.

2. The standard 8088 operates at 5 MHz and the 8088-2 operates at 8 MHz

3. The 8086 is manufactured in three speeds: 5-MHz 8086, 8-MHz 8086-2, and the 10-MHz 8086-1

4. The CLK is externally generated by the 8284 clock generator and driver IC.

(a) SYSTEM CLOCK OR CLOCK GENERATOR

1. Definition

2. Clock signal

3. Applications








1. Definition

(2) CLOCK SIGNAL:

1. A clock signal is a particular type of signal that oscillates between a high and a low state.

2. To find frequency(f) of clock signal. f=1/p(period)


1. Definition

2. Clock signal

3. Applications








2. Clock signal

(3) APPLICATIONS:1. The time base for synchronization of

the internal and external operations of the microprocessor in a microcomputer system is provided by the clock (CLK) input signal.

2. The clock signal in a microprocessor allows synchronization of several components of the microprocessor. The correctness of the computation of the microprocessor depends upon efficient and balanced distribution of the clock signal. The clock generator generates the clock signal.

3. also provides the READY signal for the insertion of wait states into the CPU bus cycle.

1. Definition

2. Clock signal

3. Application









3. Applications

(4) Block Diagram (8284A):


1. Definition

2. Clock signal

3. Application










1. Definition

2. Clock signal

3. Application









(5) Exp Block Diagram:

1. Crystal Oscillator2. +3 and +2 sync3. Buffer4. Latches and Flip Flop

(5) EXPLAINATION OF BLOCK DIAGRAM (8284A):

1. XTAL OSCILLATOR: 8284 is used with the 8088 is to connect either a 15MHZ or 24MHZ crystal between its X1 and X2 inputs.

2. A series capacitor CL is also required. Its typical value when used with the 15MHZ crystal is 12pF.

3. The CLK output of the 8284 can be directly connected to the CLK input of the 8088.The 8284 connects to the 8086 in exactly the same way.


3. The fundamental crystal frequency is divided by 3 within the 8284 to give either a 5 or 8MHZ clock signal. This signal is internally buffered and output at CLK. For PCLK +2 sync(CLK frequency divided into 2).

4. A buffer is a means of isolating a signal source circuit from the loading circuit. They are generally needed when the signal source does not have sufficient capacity to deliver the current demanded by the load circuit. If buffers are not used, a problem called input loading results and this may cause the circuit to malfunction or to become damaged.

5. In digital circuits, the buffers reproduce the sequence of 1's and 0's received from one circuit and make them available to another circuit at a higher power level. A buffer is like a non-inverting amplifier with a gain of unity.

(6) CLK voltage and timing characteristics for a 5MHZ processor:


1. Definition

2. Clock signal

3. Application









(6) CLK voltage and timing characteristics for a 5MHZ:

1. The signal is specified at metal oxide semiconductor (MOS)-compatible voltage levels and not TTL levels.

2. Its mini and max low logic levels are VLmin= -0.5V and VLmax= 0.6V, respectively .

3. Its mini and max high logic levels are VHmin= 3.9V and VHmax= Vcc +1V.

(6) CLK voltage and timing characteristics for a 5MHZ:

4. The period of the clock signal of a 5MHZ 8088 can range from a minimum of 200ns to a maximum of 500ns.

5. The maximum rise and fall times of its edges equal 10ns.

6. Duration of high and low logics are 68.66ns min and 118.33ns min resp.

(7) PIN DIAGRAM (8284A):


1. Definition

2. Clock signal

3. Application










1. Definition

2. Clock signal

3. Application








8. Exp Pin Diagram (8284A)

(8)Exp PIN DIAGRAM (8284A):

Pins are divided into three category: 1.Power Supply Pins

2.Input Pins 3.Output Pins

(8) EXPLAIN PIN CONFIGURATION (8284A):

1. Power supply pins:

a) Vcc…..(18# pin)

Used for supply power. e.g +12vcc or +5vcc.

b) GND…..(9# pin)

Used for connecting the ic to lower potential or ground.

(8) EXPLAIN PIN CONFIGURATION (8284A):

2. Input pins:

a).Reset in …..(11 # pin )

b).X1 and X2 (crystal in)…..(17# and 16# pins) resp.

c).F/C (frequency/clock select)…..(13 #pin).

d).EFI(external freq in)…..(14# pin).

e).CSYNC(clock synchronization)…..(1# pin)

f).RDY1 and AEN1(ready1 and address enable1)…..(4# and 3# pins) resp.

g).RDY2 and AEN2(ready2 and address enable2)…..(6# and 7# pins) resp.

h).ASYNC(synchronization select)…..(15# pin).

(8) EXPLAIN PIN CONFIGURATION (8284A) INPUT PINS:

RES(RESET IN):

1. This is an input active-low signal to generate RESET.

2. It is connected to the power-good signal from the power supply.

3. When the power switch is turned on, assuming that the power supply is good.

4. a low signal is provided to this pin,

5. and the 8284 in turn will activate the RESET pin.

6. forcing the 8088/86 to reset; then the microprocessor takes over. This is called a cold boot.


X1 and X2 (crystal in):

1. XI and X2 are the pins to which a crystal is attached.

2. The crystal frequency must be 3 times the desired frequency for the microprocessor.

3. The maximum crystal for the 8284A is 24 MHz and 30MHz for the 8284A-1.

4. The IBM PC is connected to a crystal of 14.31818 MHz.

5. For some turbo compatibles,

it is 24 MHz.


F/C (frequency/clock select):

1. This pin provides an option for the way the clock is generated.

2. If connected to low, the clock is generated by the 8284 with the help of a crystal oscillator.

3. If it is connected to high, it expects to receive clocks at

the EFI pin.

4. Since the IBM PC uses a

crystal, this pin is connected

to low.


EFI (external frequency in):

1. External frequency is connected to this pin if F/C

has been connected to high.

2. In the IBM PC this is not connected since a crystal is

used instead of an external

frequency generator.

3. In some cases (such as the

Turbo PC), this pin is used to provide clock frequency in place of XI and X2.

EFI (external frequency in): Example

1. EFI - changed from earth to the OSC input from other 8284A (EFI=external frequency input)

2. F/C' - changed from earth to Vcc (5v) because now the chip is using F(frequency) input instead of C(crystal) input

3. Both X1 & X2 - grounded


CSYNC(clock synchronization):

1. This active-high signal is used to allow several 8284 chips to be connected together and synchronized.

2. The IBM PC only uses one

8284; therefore, this pin is

connected to low.


RDY1 and AEN1:

1. RDY1 is active high and AEN1 (address enable) is active low.

2. They are used together to provide a ready signal to the microprocessor, which will insert a WAIT state to the CPU read/write cycle.

3. In the IBM PC, RDY1 is connected to DMAWAIT and

AEN1 is connected to RDY/WAIT.

4. They allow the wait state to be inserted either by the CPU or by DMA.


RDY2 and AEN2:1. These function exactly like RDY1 and AEN1.2. These extra RDY and AEN signals are

provided to allow for a multiprocessing system.

3. It allows other general-purpose CPUs such as the 8088/86 to gain control over the buses.

4. In the IBM PC, RDY2 is connected to low, AEN2 is connected to high, which permanently disables this

function since there is only one 8088/86 microprocessor in the system.5. In cases of multiprocessor systems, these signals are used to coordinate access over the buses by different CPUs


ASYNC(READY SYNCHRONIZATION SELECT):

1. This is called ready synchronization select.

2. An active low is used for devices that are not able to

adhere to the very strict RDY setup time requirement.

3. In the IBM PC this is

connected to low, making

the timing design of the

system easier with slower

logic gates.

(8) EXPLAIN PIN CONFIGURATION (8284A) OUTPUT SIGNALS:

3. OUTPUT SIGNALS:

a).Reset …..(10# pin).

b). OSC(Oscillator)…..(12# pin).

c).CLK(clock)…..(8# pin).

d).PCLK(peripheral clock)…..(2# pin).

e).Ready…..(5# pin).


Reset:

1. This is an active-high signal that provides a RESET signal to the 8088/86 microprocessor.

2. It is activated by the RES

input signal discussed

earlier.


Oscillator(OSC):

1. This provides a clock

frequency equal to the crystal oscillator and it is TTL compatible.

2. Since the IBM crystal

oscillator is 14.31818 MHz,


Clock(CLK):

1. This is an output clock frequency equal to one-third of the crystal oscillator, or EFI input frequency, with a duty cycle of 33%. This is connected to the clock input of

the 8088/86 and all other devices

that must be synchronized with

the CPU.

2. In the IBM PC it is connected to

pin 19 of the 8088 microprocessor.

3. This frequency, 4.772776 MHz

(14.31818 divided by 3), is the

processor frequency on which

all of the timing calculations of

the memory and I/O cycle are

based.


Peripheral Clock(PCLK):

1. This frequency is one-half of CLK (or one-sixth of the crystal) with a duty cycle of

50% and is TTL compatible.

2. In the IBM PC this 2.386383

MHz is provided to the 8253 or 8254 timer to be used to generate speaker tones, and other functions.Also provided to 8279 keyboard/display interfacing ic.


Ready:

1. This signal is connected to READY of the CPU.

2. In the IBM PC it is used to

signal the 8088 to indicate if the CPU needs to insert a wait state due to the slowness of the devices that

the CPU is trying to contact.

3. At low logic, cpu is at wait state.

(9) CONNECTING THE 8284 TO 8088/8086:


1. Definition

2. Clock signal

3. Application








9. Connecting the 8284 to 8088

1. 8284 CLK connected to 8086 CLK to give it synchronized clocks.

2. 8284 Reset connected to 8086 Reset to forcing the 8088/86 to reset; then the microprocessor takes over. This is called a cold boot.

3. Ready pin is used to signal the 8088 to indicate if the CPU

needs to insert a wait state due to the slowness of the devices that

the CPU is trying to contact.

(9) CONNECTING THE 8284 TO 8088/8086:

(10) RELATIONSHIP BETWEEN CLK AND PCLK:


1. Definition

2. Clock signal

3. Application









Two clocks outputs on the 8284.

1. PCLK(Peripheral clock)

2. OSC CLK( oscillator clock)

a). These signals are provided to driver peripheral IC’s .

b). The clock signal output at PCLK is half the frequency of CLK.

c). For instance, if an 8088 is operated at 5MHZ, PCLK is 2.5MHZ .

d). Also it is at TTL compatible levels rather than MOS levels.

e). Osc output is at the crystal frequency , which is three times that of CLK.

(10) RELATIONSHIP BETWEEN CLK AND PCLK:

CLK = 33% crystal/EFI = 0.33 (15Mhz) =5 MhzPCLK = 50% crystal/EFI = 0.5 (15Mhz) =7.5Mhz

PRESENTATION LAYOUT

1. Definition

2. Clock signal

3. Applications








1. Definition

2. Applications

3. Four Time States

4. Idle State

5. Wait State



(b) BUS CYCLE AND TIME STATES


(1) DEFINITION:

A single transaction between the main memory and the CPU.

1. A bus cycle corresponds to a sequence of events that start with an address being output on the system bus followed by a read or write data transfer.

2. During these operations, the MPU produces a series of control signals to control the direction and timing of the bus.


1. Definition

2. Applications

3. Four Time States

4. Idle State

5. Wait State



1. Definition

(2) APPLICATIONS:

1. A bus cycle defines the basic operation that a microprocessor performs to communicate with external devices.

2. Bus cycle helps to manage data on bus.


1. Definition

2. Application

3. Four Time States

4. Idle State

5. Wait State



2. Applications

(3) FOUR TIME STATES:

1. The bus cycle of the 8088 & 8086 microprocessor consists of at least four clock periods. These four time states are called…

a) T1 State

b) T2 State

c) T3 State

d) T4 State


1. Definition

2. Application

3. Four Time States

4. Idle State

5. Wait State



3. Four Time States

(3) FOUR TIME STATES:

READa). T1 State:(Address Out State)CPU Drives Valid Address on Address

Bus.

b) T2 State:(Transaction Type) IOR or MEMR go Active. c) T3 State:(Memory or I/ORespond) CPU “waits” for Memory (or I/O) to drive data bus.

d) T4 State:(Data Latch State) CPU Latches Data Bus Signals into register.

These four clock states gives a bus cycle duration of 125ns*4=500ns in an 8MHZ 8088 system.

WRITEa) T1 State:(Address Out State) CPU Drives Valid Address on Address

Bus.

b) T2 State:(Transaction Type) IOW or MEMW and Data Bus go

Active.

c) T3 State:(Memory or I/ORespond) CPU Continues to Drive Data Bus.

d) T4 State:(Data Latch State) CPU Drives Data Until End of T4

Allowing Memory (or I/O) to Latch Data Bus Signals in.

(4) IDLE STATE:

1. If no bus cycles are required, the microprocessor performs what are known as idle states.

2. During these states, no bus activity takes place. Each idle state is one clock period long, and any number of them can be inserted between bus cycles.

3. Idle states are performed if the instruction queue inside the microprocessor is full and it does not need to read or write operands from memory.


1. Definition

2. Application

3. Four Time States

4. Idle State

5. Wait State



4. Idle State

(5) WAIT STATE:1. Wait states can also be inserted into a bus

cycle.

2. This done in response to a request by an event in external hardware instead of an internal event such as a full queue.

3. Ready input in 8284 of the MPU is provided specifically for this purpose.

4. Logic zero at this input indicates that the current bus cycle should not be completed.

5. As long as, Ready is held at the 0 level, wait states are inserted between states T3 and T4 of the current bus cycle.


1. Definition

2. Application

3. Four Time States

4. Idle State

5. Wait State



5. Wait State

(6) HOW TO READ A TIMING DIAGRAM:

Definition:

A timing diagram is a representation of a set of signals in the time domain.

Here we discuss about, how to read timing diagram of bus cycle.


1. Definition

2. Application

3. Four Time States

4. Idle State

5. Wait State


7. Example of bus cycle6. How to read a timing diagram

(6) HOW TO READ A TIMING DIAGRAM:

(7) EXAMPLE OF BUS CYCLE:

1. Memory Read Bus Cycle2. Memory Write Bus Cycle


1. Definition

2. Application

3. Four Time States

4. Idle State

5. Wait State


7. Example of bus cycle7. Example of bus cycle

1. Memory Read Bus Cycle

During period T1

1. The 8086 outputs the 20-bit address of the memory location to be accessed on its multiplexed address/data bus. BHE is also output along with the address during T1.

2. At the same time a pulse is also produced at ALE. The trailing edge or the high level of this pulse is used to latch the address in external circuitry.

3. Signal M/IO is set to logic 1 and signal DT/R is set to the 0 logic level and both are maintained throughout all four periods of the bus cycle.


Beginning with period T2

1. Status bits S3 through S6 are output on the upper four address bus lines.

2. This status information is maintained through periods T3 and T4.

3. On the other hand, address/data bus lines AD0 through AD7 are put in the high-Z state during T2.

4. Late in period T2, RD is switched to logic 0. This indicates to the memory subsystem that a read cycle is in progress.

5. DEN is switched to logic 0 to enable external circuitry to allow the data to move from memory onto the microprocessor's data bus.


During period T31. The memory must provide

valid data during T3 and maintain it until after the processor terminates the read operation.

2. The data read by the 8086 microprocessor can be carried over all 16 data bus lines.

During T4

3. The 8086 switches RD to the inactive 1 logic level to terminate the read operation.

4. DEN returns to its inactive logic level late during T4 to disable the external circuitry.

2. Memory Write Bus Cycle

During period T1

1. The address along with BHE are output and latched with the ALE pulse.

2. M/IO is set to logic 1 to indicate a memory cycle.

3. However, this time DT/R is switched to logic 1. This signals external circuits that the 8086 is going to transmit data over the bus.

2. Memory Write Bus Cycle

Beginning with period T2

1. WR is switched to logic 0 telling the memory subsystem that a write operation is to follow.

2. The 8086 puts the data on the bus late in T2 and maintains the data valid through T4.

3. Data will be carried over all 16 data bus lines.

4. DEN enables the external circuitry to provide a path for data from the processor to the memory.

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