Microprocessor presentation

Download Microprocessor presentation

Post on 24-May-2015

1.614 views

Category:

Education

0 download

Embed Size (px)

DESCRIPTION

clock generator, bus cycle

TRANSCRIPT

<ul><li> 1. WELCOMERESPECTED TEACHERS &amp; DEAR FELLOWS</li></ul><p> 2. SYSTEM CLOCK &amp; BUS CYCLE GROUP MEMBERS SYED WASI SHAHSYED MOHSIN SHAH M.SAMI-UL-HAQ HASHMIMUHAMMAD UMER FAROOQ 3. PRESENTATION LAYOUT (a). SYSTEM CLOCK OR CLOCK (b). BUS CYCLE AND GENERATOR TIME STATES1.Definition 1. Definition2.Clock signal 2. Applications3.Applications4.Block Diagram (8284A)3. Four Time States5.Exp of Block Diagram 4. Idle State6.CLK voltage timing 5. Wait Statecharacteristics for a 5MHZ 6. How to read a timing diagramprocessor7. Pin Diagram (8284A) 7. Example of bus cycle8. Explain Pin Configuration9. Connecting the 8284 to the 808810. Relationship between CLK andPCLK 4. (a) SYSTEM CLOCK ORCLOCK GENERATOR1.Definition (1) DEFINITION: A clock generator or system clock is2.Clock signal a circuit that produces a timing3.Applications signal (known as a clock signal and behaves as such) for use in4.Block Diagram (8284A)synchronizing a circuits operation.5.Exp of Block Diagram 1. A clock signal of some frequency generated by system clock,6.CLK voltage timing operates the microprocessor oncharacteristics for a 5MHZ that frequency.processor2. The standard 8088 operates at 5MHz and the 8088-2 operates at 87. Pin Diagram (8284A)MHz8. Explain Pin Configuration 3. The 8086 is manufactured in threespeeds: 5-MHz 8086, 8-MHz 8086-9. Connecting the 8284 to the 80882, and the 10-MHz 8086-110. Relationship between CLK and 4. The CLK is externally generated byPCLKthe 8284 clock generator and driverIC. 5. (a) SYSTEM CLOCK ORCLOCK GENERATOR1.Definition (2) CLOCK SIGNAL:2.Clock signalClock signal 1. A clock signal is a particular3.Applicationstype of signal that oscillates4.Block Diagram (8284A) between a high and a low state.5.Exp of Block Diagram 2. To find frequency(f) of clocksignal. f=1/p(period)6.CLK voltage timingcharacteristics for a 5MHZprocessor7. Pin Diagram (8284A)8. Explain Pin Configuration9. Connecting the 8284 to the 808810. Relationship between CLK andPCLK 6. (a) SYSTEM CLOCK ORCLOCK GENERATOR1.Definition (3) APPLICATIONS: 1.The time base for synchronization2.Clock signal of the internal and external3.3.ApplicationApplications operations of the microprocessor in a microcomputer system is4.Block Diagram (8284A)provided by the clock (CLK) input5.Exp of Block Diagram signal. 2.The clock signal in a6.CLK voltage timing microprocessor allowscharacteristics for a 5MHZ synchronization of severalprocessorcomponents of the microprocessor. The correctness of the computation7. Pin Diagram (8284A) of the microprocessor depends8. Explain Pin Configuration upon efficient and balanced distribution of the clock signal.9. Connecting the 8284 to the 8088 The clock generator generates the clock signal.10. Relationship between CLK and 3. also provides the READY signalPCLKfor the insertion of wait states intothe CPU bus cycle. 7. (a) SYSTEM CLOCK OR CLOCK GENERATOR1. Definition(4) Block Diagram (8284A):2. Clock signal3. Application4. Block Diagram (8284A)4. Block Diagram (8284A)5. Exp of Block Diagram6. CLK voltage timingcharacteristics for a 5MHZprocessor7. Pin Diagram (8284A)8. Explain Pin Configuration9. Connecting the 8284 to the 808810. Relationship between CLK andPCLK 8. (a) SYSTEM CLOCK ORCLOCK GENERATOR1.Definition (5) Exp Block Diagram:2.Clock signal3.Application4.Block Diagram (8284A)5.Exp of Block DiagramExp of Block Diagram6.CLK voltage timingcharacteristics for a 5MHZprocessor1. Crystal Oscillator7. Pin Diagram (8284A)2. +3 and +2 sync8. Buffer Pin Configuration3. Explain4. Connecting the 82849. Latches and Flip Flop to the 808810. Relationship between CLK andPCLK 9. (5) EXPLAINATION OF BLOCK DIAGRAM (8284A):1. XTAL OSCILLATOR: 8284 is used with the 8088 is to connect either a 15MHZ or 24MHZ crystal between its X1 and X2 inputs.2. A series capacitor CL is also required. Its typical value when used with the 15MHZ crystal is 12pF.3. The CLK output of the 8284 can be directly connected to the CLK input of the 8088.The 8284 connects to the 8086 in exactly the same way. 10. (5) EXPLAINATION OF BLOCK DIAGRAM (8284A):3. The fundamental crystal frequency is divided by 3 within the 8284 to give either a 5 or 8MHZ clock signal. This signal is internally buffered and output at CLK. For PCLK +2 sync(CLK frequency divided into 2).4. A buffer is a means of isolating a signal source circuit from the loading circuit. They are generally needed when the signal source does not have sufficient capacity to deliver the current demanded by the load circuit. If buffers are not used, a problem called input loading results and this may cause the circuit to malfunction or to become damaged.5. In digital circuits, the buffers reproduce the sequence of 1s and 0s received from one circuit and make them available to another circuit at a higher power level. A buffer is like a non-inverting amplifier with a gain of unity. 11. (5) EXPLAINATION OF BLOCK DIAGRAM (8284A): 12. (a) SYSTEM CLOCK OR CLOCK GENERATOR1. Definition(6) CLK voltage and timing2. Clock signal characteristics for a 5MHZ3. Applicationprocessor:4. Block Diagram (8284A)5. Exp of Block Diagram6. CLK voltage timingcharacteristics for a 5MHZprocessor7. Pin Diagram (8284A)8. Explain Pin Configuration9. Connecting the 8284 to the 808810. Relationship between CLK andPCLK 13. (6) CLK voltage and timing characteristics for a 5MHZ:1. The signal is specified at metal oxide semiconductor (MOS)- compatible voltage levels and not TTL levels.2. Its mini and max low logic levels are VLmin= -0.5V and VLmax= 0.6V, respectively .3. Its mini and max high logic levels are VHmin= 3.9V and VHmax= Vcc +1V. 14. (6) CLK voltage and timing characteristics for a 5MHZ:4. The period of the clock signal of a 5MHZ 8088 can range from a minimum of 200ns to a maximum of 500ns.5. The maximum rise and fall times of its edges equal 10ns.6. Duration of high and low logics are 68.66ns min and 118.33ns min resp. 15. (a) SYSTEM CLOCK ORCLOCK GENERATOR1.Definition (7) PIN DIAGRAM (8284A):2.Clock signal3.Application4.Block Diagram (8284A)5.Exp of Block Diagram6.CLK voltage timingcharacteristics for a 5MHZprocessor7. Pin Diagram (8284A)Pin Diagram (8284A)8. Explain Pin Configuration9. Connecting the 8284 to the 808810. Relationship between CLK andPCLK 16. (a) SYSTEM CLOCK ORCLOCK GENERATOR1.Definition(8)Exp PIN DIAGRAM (8284A):2.Clock signal3.Application4.Block Diagram (8284A)5.Exp of Block Diagram6.CLK voltage timingcharacteristics for a 5MHZprocessor7. Pin Diagram (8284A)8. Explain Pin ConfigurationExp Pin Diagram (8284A)9. Connecting the 8284 to the 8088Pins are divided into three category:10. Relationship between CLK and1.Power Supply PinsPCLK 2.Input Pins3.Output Pins 17. (8) EXPLAIN PIN CONFIGURATION (8284A):1. Power supply pins:a) Vcc..(18# pin) Used for supply power. e.g+12vcc or +5vcc.b) GND..(9# pin)Used for connecting the ic to lowerpotential or ground. 18. (8) EXPLAIN PIN CONFIGURATION (8284A):2. Input pins:a).Reset in ..(11 # pin )b).X1 and X2 (crystal in)..(17# and 16# pins) resp.c).F/C (frequency/clock select)..(13 #pin).d).EFI(external freq in)..(14# pin).e).CSYNC(clock synchronization)..(1# pin)f).RDY1 and AEN1(ready1 and address enable1)..(4# and 3# pins) resp.g).RDY2 and AEN2(ready2 and address enable2)..(6# and 7# pins) resp.h).ASYNC(synchronization select)..(15# pin). 19. (8) EXPLAIN PIN CONFIGURATION (8284A) INPUT PINS:RES(RESET IN):1. This is an input active-low signal to generate RESET.2.It is connected to the power-good signal from the power supply.3. When the power switch is turned on, assuming that the power supply is good.4. a low signal is provided to this pin,5. and the 8284 in turn will activate the RESET pin.6. forcing the 8088/86 to reset; then the microprocessor takes over. This is called a cold boot. 20. (8) EXPLAIN PIN CONFIGURATION (8284A)INPUT PINS:X1 and X2 (crystal in):1. XI and X2 are the pins to which a crystal is attached.2. The crystal frequency must be 3 times the desired frequency for the microprocessor.3. The maximum crystal for the 8284A is 24 MHz and 30MHz for the 8284A-1.4. The IBM PC is connected to a crystal of 14.31818 MHz.5. For some turbo compatibles, it is 24 MHz. 21. (8) EXPLAIN PIN CONFIGURATION (8284A) INPUT PINS: F/C (frequency/clock select):1. This pin provides an option forthe way the clock is generated.2. If connected to low, the clock isgenerated by the 8284 with thehelp of a crystal oscillator.3. If it is connected to high, itexpects to receive clocks at the EFI pin.4. Since the IBM PC uses a crystal, this pin is connectedto low. 22. (8) EXPLAIN PIN CONFIGURATION (8284A) INPUT PINS:EFI (external frequency in):1. External frequency is connectedto this pin if F/C has been connected to high.2. In the IBM PC this is notconnected since a crystal is used instead of an externalfrequency generator.3. In some cases (such as the Turbo PC), this pin is used toprovide clock frequency in placeof XI and X2. 23. EFI (external frequency in):Example1. EFI - changed from earth to the OSC input from other 8284A (EFI=external frequency input)2. F/C - changed from earth to Vcc (5v) because now the chip is using F(frequency) input instead of C(crystal) input3. Both X1 &amp; X2 - grounded 24. (8) EXPLAIN PIN CONFIGURATION (8284A) INPUT PINS:CSYNC(clock synchronization):1. This active-high signal is used to allow several 8284 chips to be connected together and synchronized.2. The IBM PC only uses one 8284; therefore, this pin is connected to low. 25. (8) EXPLAIN PIN CONFIGURATION (8284A) INPUT PINS:RDY1 and AEN1:1. RDY1 is active high and AEN1 (address enable) is active low.2. They are used together to provide a ready signal to the microprocessor, which will insert a WAIT state to the CPU read/write cycle.3. In the IBM PC, RDY1 is connected to DMAWAIT and AEN1 is connected to RDY/WAIT.4. They allow the wait state to be inserted either by the CPU or by DMA. 26. (8) EXPLAIN PIN CONFIGURATION (8284A) INPUT PINS:RDY2 and AEN2:1. These function exactly like RDY1 andAEN1.2. These extra RDY and AEN signals areprovided to allow for amultiprocessing system.3. It allows other general-purpose CPUssuch as the 8088/86 to gain controlover the buses.4. In the IBM PC, RDY2 is connected tolow, AEN2 is connected to high, whichpermanently disables thisfunction since there is only one 8088/86 microprocessor in thesystem.5. In cases of multiprocessor systems, these signals are usedto coordinate access over thebuses by different CPUs 27. (8) EXPLAIN PIN CONFIGURATION (8284A) INPUT PINS:ASYNC(READY SYNCHRONIZATION SELECT):1. This is called readysynchronization select.2. An active low is used for devicesthat are not able to adhere to the very strict RDYsetup time requirement.3. In the IBM PC this is connected to low, making the timing design of the system easier with slower logic gates. 28. (8) EXPLAIN PIN CONFIGURATION (8284A)OUTPUT SIGNALS:3. OUTPUT SIGNALS:a).Reset ..(10# pin).b). OSC(Oscillator)..(12# pin).c).CLK(clock)..(8# pin).d).PCLK(peripheral clock)..(2#pin).e).Ready..(5# pin). 29. (8) EXPLAIN PIN CONFIGURATION (8284A) OUTPUT SIGNALS:Reset:1. This is an active-high signal thatprovides a RESET signal to the8088/86 microprocessor.2. It is activated by the RESinput signal discussedearlier. 30. (8) EXPLAIN PIN CONFIGURATION (8284A)OUTPUT SIGNALS:Oscillator(OSC):1. This provides a clock frequency equal to the crystaloscillator and it is TTLcompatible.2. Since the IBM crystal oscillator is 14.31818 MHz, 31. (8) EXPLAIN PIN CONFIGURATION (8284A) OUTPUT SIGNALS:Clock(CLK):1. This is an output clock frequencyequal to one-third of the crystaloscillator, or EFI input frequency, witha duty cycle of 33%. This is connectedto the clock input ofthe 8088/86 and all other devices that must be synchronized withthe CPU.2.In the IBM PC it is connected to pin 19 of the 8088 microprocessor.3.This frequency, 4.772776 MHz(14.31818 divided by 3), is theprocessor frequency on whichall of the timing calculations ofthe memory and I/O cycle arebased. 32. (8) EXPLAIN PIN CONFIGURATION (8284A)OUTPUT SIGNALS:Peripheral Clock(PCLK):1. This frequency is one-half ofCLK (or one-sixth of the crystal)with a duty cycle of 50% and is TTL compatible.2. In the IBM PC this 2.386383MHz is provided to the 8253 or8254 timer to be used to generatespeaker tones, and otherfunctions.Also provided to 8279keyboard/display interfacing ic. 33. (8) EXPLAIN PIN CONFIGURATION (8284A) OUTPUT SIGNALS:Ready:1. This signal is connected to READY of the CPU.2. In the IBM PC it is used to signal the 8088 to indicate if the CPU needs to insert a wait state due to the slowness of the devices thatthe CPU is trying to contact.3. At low logic, cpu is at wait state. 34. (a) SYSTEM CLOCK ORCLOCK GENERATOR1.Definition (9) CONNECTING THE 8284 TO2.Clock signal 8088/8086:3.Application4.Block Diagram (8284A)5.Exp of Block Diagram6.CLK voltage timingcharacteristics for a 5MHZprocessor7. Pin Diagram (8284A)8. Explain Pin Configuration9. Connecting the 8284 to the 8088Connecting the 8284 to 808810. Relationship between CLK andPCLK 35. (9) CONNECTING THE 8284 TO 8088/8086:1. 8284 CLK connected to 8086 CLK to give it synchronized clocks.2. 8284 Reset connected to 8086 Reset to forcing the 8088/86 to reset; then the microprocessor takes over. This is called a cold boot.3. Ready pin is used tosignal the 8088 to indicate if the CPU needs to insert a wait state due to the slowness of the devices that the CPU is trying to contact. 36. (a) SYSTEM CLOCK ORCLOCK GENERATOR1.Definition (10) RELATIONSHIP BETWEEN2.Clock signal CLK AND PCLK:3.Application4.Block Diagram (8284A)5.Exp of Block Diagram6.CLK voltage timingcharacteristics for a 5MHZprocessor7. Pin Diagram (8284A)8. Explain Pin Configuration9. Connecting the 8284 to the 808810. Relationship between CLK andRelationship between CLK andPCLK 37. (10) RELATIONSHIP BETWEEN CLK AND PCLK:Two clocks outputs on the 8284.1. PCLK(Peripheral clock)2. OSC CLK( oscillator clock)a). These signals are provided to driver peripheral ICs .b). The clock signal output at PCLK is half the frequency of CLK.c). For instance, if an 8088 is operated at 5MHZ, PCLK is 2.5MHZ .d). Also it is at TTL compatible levels rather than MOS levels. CLK = 33% crystal/EFI = 0.33 (15Mhz) =5 Mhze). Osc output is at the crystal frequency , which PCLK = 50% crystal/EFI = 0.5 (15Mhz) =7.5Mhz is three times that of CLK. 38. PRESENTATION LAYOUT (a) SYSTEM CLOCK OR CLOCK (b) BUS CYCLE ANDGENERATORTIME STATES1.Definition 1. Definition2.Clock signal 2. Applications3.Applications4.Block Diagram (8284A)3. Four Time States5.Exp of Block Diagram 4. Idle State6.CLK voltage timing 5. Wait Statecharacteristics for a 5MHZ 6. How to read a timing diagramprocessor7. Pin Diagram (8284A) 7. Example of bus cycle8. Explain Pin Configuration9. Connecting the 8284 to the 808810. Relationship between CLK andPCLK 39. (b) BUS CYCLE ANDTIME STATES1. Definition Definition (1) DEFINITION:2. Applications A single transaction between the3. F...</p>