microprocessor Lec 01 mic

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<ol><li> 1. Microprocessor Basics </li><li> 2. 05/09/15 Presentation By Sania Gul 2 Microprocessor &amp; Microcomputer The complete processor built on a single chip is called microprocessor (P) or micro processing unit (MPU). The computer built from microprocessor is called microcomputer </li><li> 3. 05/09/15 Presentation By Sania Gul 3 Architecture of Microcomputer Bus Architecture </li><li> 4. 05/09/15 Presentation By Sania Gul 4 MEMORY (Primary &amp; Secondary) Primary storage memory is made of RAM &amp; ROM. Secondary storage memory is Hard disk, Floppy disk, USB, CDs, DVDs etc. These devices store data so they are memory devices but for the microprocessor all secondary memory devices are I/O devices. For P, memory is only the primary memory. </li><li> 5. 05/09/15 Presentation By Sania Gul 5 Peripherals All I/O devices are called peripherals. The P, primary memory &amp; the peripherals are connected to system bus and all the data exchange among them takes place over the system bus. </li><li> 6. 05/09/15 Presentation By Sania Gul 6 Primary Memory The primary memory is a collection of lot of registers. One register of memory can hold any number of bits, but usually it is designed to hold 1 byte (8 bits). The complete chip consists of lot of such register, each having different address by which P calls it (or identifies it). Remember, the number of registers in a memory chip are always in the power of 2. For example u have heard about kilo byte (KB), Mega Byte (MB), Giga Byte (GB) etc. </li><li> 7. 05/09/15 Presentation By Sania Gul 7 Primary Memory always in power of 2 1 KB 210 Bytes =1024 Bytes 1 MB 220 Bytes =1024 K Bytes 1GB 230 Bytes =1024 Mbytes 1 TB 240 Bytes =1024 GBytes </li><li> 8. 05/09/15 Presentation By Sania Gul 8 I/O peripherals Well known I/O devices are printer, scanner, key board, mouse, joy stick etc. The I/O devices are connected to system bus through peripheral interface IC called I/O controllers. (u can see these ICs on the mother board). This IC or I/O controller consists of many registers &amp; like memory each register inside the IC has a unique address &amp; P calls them by their address to exchange data with them. </li><li> 9. 05/09/15 Presentation By Sania Gul 9 Peripheral controller Hard disk, floppy disk, CD-R, DVD Modem, LAN Card Monitor, LCD, Multimedia </li><li> 10. 05/09/15 Presentation By Sania Gul 10 System bus Bus is a group of wires that transmit a binary word. The system bus is composed of 3 buses. 1. Address bus 2. Data Bus 3. Control Bus </li><li> 11. 05/09/15 Presentation By Sania Gul 11 System bus 1. Address bus: The address bus is used to carry the address from micro-processor to peripheral or memory. The address generated by the P is in the form of bits &amp; each bus line carries one bit of address. It is a unidirectional bus. Each line is represented by A 2. Data Bus: The data from memory or peripheral to P &amp; vice versa is exchanged on data bus. It is a bidirectional bus. Each line is represented by D </li><li> 12. 05/09/15 Presentation By Sania Gul 12 System Bus 3. Control bus: This bus is used to carry control signals from P to memory or peripherals &amp; vice versa. It is not a bus in the true sense as it is not a common transmission medium to carry control signal. Every device is connected to microprocessor control pins individually. Multiplexed Bus: In order to reduce external pins, one pin can be shared to carry both address &amp; data. But both are not carried at the same time. This kind of bus is called multiplexed bus, Each line is represented by AD. (address data) </li><li> 13. 05/09/15 Presentation By Sania Gul 13 Address decoding of 4 bit address This register is selected with address of 0 H and its contents are CD H </li><li> 14. 05/09/15 Presentation By Sania Gul 14 Memory with on chip address decoding </li><li> 15. 05/09/15 Presentation By Sania Gul 15 Memory Interfacing </li><li> 16. 05/09/15 Presentation By Sania Gul 16 Address space The complete set of addresses which can be created from fix number of bits. e.g. with 4 bits only 24 (16) address can be created. The address range will be 0000 = 0H (first address) note: addresses are always given in Hex format 0001 =1H (Second address) 1111 = FH (last address) </li><li> 17. 05/09/15 Presentation By Sania Gul 17 Address mapping On maps of houses, we give particular location of a room, washrooms &amp; kitchen. Like wise allocating a unique address to any register or device on the address space is called address mapping. Memory address space </li><li> 18. 05/09/15 Presentation By Sania Gul 18 Memory Matrix </li><li> 19. 05/09/15 Presentation By Sania Gul 19 Inside Microprocessor There are also registers inside the P. Some special purpose registers &amp; few data registers. The purpose of data registers is to store data &amp; results. These results can afterwards be displayed on output devices or stored in memory for later use. As there are very few registers inside processor so instead of address, they got names like register A, B, C etc. The size of processor register defines how much maximum data, the processor can process at one time. For example the size of 8085 Ps registers is 8 bit, so it is 8 bit processor &amp; that of 8088/8086 is 16 bits, so it is 16 bit processor. </li><li> 20. 05/09/15 Presentation By Sania Gul 20 Inside Microprocessor </li><li> 21. 05/09/15 Presentation By Sania Gul 21 Performance Comparison of Ps Performance of microprocessor is measured in units of MIPS how many million of instructions they can execute per second. </li><li> 22. 05/09/15 Presentation By Sania Gul 22 Primary memory Segmentation Imagine u visit a library &amp; there are no sections. All books are randomly placed. Can u find your required book easily? NO Similarly the program (code) &amp; data must be organized in different sections of memory to help the processor to find them easily, because it will reduce the processing time. </li><li> 23. 05/09/15 Presentation By Sania Gul 23 Types of Segments 4 types of segments exists in memory 1. Code Segment for storing program 2. Data Segment for storing Data 3. Stack Segment for storing Temporary Data 4. Extra Segment for storing extra Data in addition to data in DS </li><li> 24. 05/09/15 Presentation By Sania Gul 24 Code Segment (CS) It is that portion of memory which contains the program (Code). The program is set of instructions. The P fetches (picks) one instruction from the memory, decodes it to find what to do, &amp; process the data according to the instruction. So for each instruction 3 steps are performed Fetch Decode Execute </li><li> 25. 05/09/15 Presentation By Sania Gul 25 Program Counter (PC) or Instruction pointer (IP) Pointer means address. IP is a register inside microprocessor which holds the address of next instruction to be executed. When the processor fetches one instruction from the memory, it automatically points to the next instruction in the memory which is to be executed after the current instruction. It is like an office secretary who always points to his officer what to do next in his schedule. Its job is to send to the memory the address of the next instruction to be fetched &amp; executed. </li><li> 26. 05/09/15 Presentation By Sania Gul 26 Stored program The instructions are already stored by programmer in the memory. When the processor is turned on, it automatically takes first instruction from the memory because initially its IP or PC is 0H. The instructions are stored in binary format in memory &amp; one instruction may take one byte or many bytes of memory. </li><li> 27. 05/09/15 Presentation By Sania Gul 27 Sequential execution Computer is a sequential machine i.e. it fetches instructions from memory and executes them in proper order. unless there is any instruction or external event (interrupt) which breaks the sequence. Main Program 1st instruction 2nd instruction 3rd instruction 4th instruction last instruction CPU memory Data bus Main Program 1st instruction 2nd instruction 3rd instruction 4th instruction last instruction </li><li> 28. 05/09/15 Presentation By Sania Gul 28 Instruction Cycle Instruction decoder &amp; control unit Adder Inverter AND logic PC A B C 0H Add res s Contents 0H 80 H 1H 12 H 2H 40 H 3H 05 H 4H 75 H AH 06 H BH 01H MOV A,3H ADD A, 5H HLT 80 H12H 2H 3H ADD A,5H 4H Sum=8H Memory =16 Bytes Data Segment Code Segment 4 bit Address Bus 8 bit data bus RD control signal Note: if the instruction is of 2 bytes, it takes 2 Bus cycles to Fetch the instruction if the data Bus is 8 bit wide. </li><li> 29. 05/09/15 Presentation By Sania Gul 29 Instruction Cycle Cycle means duration. The P takes certain amount of time to execute the instruction. The time required varies from one processor to other &amp; also depends on System Clock frequency f. For example, the instruction ADD A, 5H takes 4 T states. If the system clock frequency f=2 Hz, the T=1/f = =0.5 s So ADD A, 5H 4 T = 4* 0.5= 2 s </li><li> 30. 05/09/15 Presentation By Sania Gul 30 Sub routines/ procedure or functions These are small programs written separately from the main program. These program are written separately because of many reasons like. 1. It makes programming modular, easy to debug, &amp; allowing many programmers to work on small units of their interests. 2. The subroutine developed by one programmer can be used by other programmers in their own programs. 3. The subroutine can be called by main program many times without writing the sub routine code again &amp; again so less memory is required. The program control is passed to subroutine when the main program calls it, &amp; returned back to main program once the subroutine is finished. </li><li> 31. 05/09/15 Presentation By Sania Gul 31 Stack Segment (SS) It is the portion of the RAM used for temporary storage of Data. It is the data structure which works on LIFO (last in first out principle) like a stack of books. The last data pushed on the stack is the one which is popped first. In Intel Ps, the stack storage starts from the highest address &amp; continue towards the lower addresses. In normal data structures the data is stored starting from the lowest address (the bottom) and continue towards the higher addresses even in Intel micro controllers stack. Higher address Lower address Stack grows </li><li> 32. 05/09/15 Presentation By Sania Gul 32 Need of Stack Segment When the main program calls sub routine, the program control shifts to sub routine &amp; the Program counter PC is loaded with the address of the first instruction of sub routine. However at the end of subroutine, the control has to shifted back to the main program. So before shifting the control to sub routine, the contents of PC are stored automatically on stack with the CALL instruction. And when the sub routine is over, the old contents of PC are automatically retrieved from the stack when the last instruction of sub-routine RET is executed &amp; execution starts from the next instruction of the main program. which has called the sub-routine. </li><li> 33. 05/09/15 Presentation By Sania Gul 33 </li><li> 34. 05/09/15 Presentation By Sania Gul 34 Need of Stack Segment As there are very few registers inside P, so it may be possible that the main program &amp; sub-routine both require them. This is not possible if there was no stack. So the programmer ensures that before the sub-routine uses the P registers, the data inside these registers related to main program are stored on stack with the help of PUSH instructions &amp; then POPPED from the stack at the end of sub-routine with the help of POP instruction. The number of POPs instruction must be equal to number of PUSHES. POPPING must be in reverse order of PUSHiNG to restore original contents due to LIFO principle. </li><li> 35. 05/09/15 Presentation By Sania Gul 35 Pushing means adding Popping means removing </li><li> 36. 05/09/15 Presentation By Sania Gul 36 Stack pointer This register stores the address of the Top Of Stack (TOS), the top most valid filled location of SS. As in Intel Ps, the stack grows from the higher address towards the lower one, so when the data is pushed on stack SP decrements &amp; when it is popped from stack, SP increments. </li><li> 37. 05/09/15 Presentation By Sania Gul 37 </li><li> 38. 05/09/15 Presentation By Sania Gul 38 </li><li> 39. 05/09/15 Presentation By Sania Gul 39 </li><li> 40. 05/09/15 Presentation By Sania Gul 40 Instruction pipelining In old processors, one instruction is fetched, decoded &amp; executed. After that the same process occurs for the second instruction &amp; so on. Fetching of the next instruction, while the current instruction executes is called pipelining. This saves the time &amp; increase processing speed. </li><li> 41. 05/09/15 Presentation By Sania Gul 41 BCD &amp; Signed Numbers Unpacked BCD Packed BCD </li></ol>