Microprocessor Generations The First MicroprocessorIntel created the first microprocessor 4004 in 1971.Ran at a clock speed of 108KHzContained !"00 transistors and #as $%ilt on a 10&micron process.'hen came the (&80 $) (ilo* in 197+ %sed in 'R,&80+-0 $) ./, 'echnolo*ies %sed in 0pple&I and II. The First PCIn 1981 I1. introd%ced the I1. 2C! #hich #as $ased on a 4.77.Hz Intel 8088 processor r%nnin* the .icrosoft 3isk /peratin* ,)stem 4.,&3/,5 1.06"0!000 transistor at 4.77.Hz 61+ $it internal re*isters 4I0&1+5 78 $it e8ternal data $%s60 $it address $%s co%ld address %pto 999999991)tes:0ll 2rocessors are $ack#ard compati$le! like 24! 0.3 0thlon! etc. Generation of Microprocessors;irst 0@ memor) %p to 1 .e*.2rotected .ode & r%ns m%ltiple tasks! address %p to 1+ .e* ph)sical memor)! pl%s it can address =irt%al memor).6Airt%al memor) is reall) hard disk space $ein* %sed as R0.. Second Generation (P2) 808+Bas a=aila$le in different clock speeds.Companion Coprocessor & 8087 Third Generation (P3)80"8+3C6"&$it 4internall) D e8ternall)5 s%ccessor to 808+! 1"&pins6Had to do 1+&$it and 8&$it I7/ data transfers to keep it compati$le #ith older soft#are and peripherals.6Co%ld s#itch $et#een real and protected memor) #itho%t a re$oot. Third Generation (P3) 'his ad=anced memor) mana*ement allo# for R/. shado#in*! mo=in* code o%t of R/. into faster R0..6Ee# addressin* mode #as de=eloped called =irt%al mode..ade the 80"8+ appear like m%ltiple C' processors so m%ltiple pro*rams co%ld r%n at once.80"8+,C6100 pin chip.6Internall) the same as a 80"8+3C! e8ternall) had 4&$it address and1+&$it data $%s. Third Generation (P3) /ther ;la=o%rs of 80"8+680"8+,@? %sed in laptops! had lo#er 4@5 po#er cons%mption.Had e8ternal "&$it address $%s like 3C! $%t e8ternal 1+&$it data $%s like ,C.60.80"8+,C and 3C? 0.3 man%fact%red clone. ,C #as like the ,@. Fourth Generation (P4)8048+3C?61+8 pin 6Incl%ded math coprocessor6s)nchrono%s #ith main processor and e8ec%tes in fe#er c)cles than pre=io%s math coprocessors8K1 @e=el 1 memor) cache690&9-F zero #ait statesRed%ced instr%ction&e8ec%tion time6a=era*e of t#o clock c)cles per instr%ction compared to pre=io%s of more than fo%r clock c)cles needed1%rst&mode memor) c)cles Fourth Generation (P4) /ther ;la=o%rs of 8048+?68048+,C? same as 3C e8cept there is no coprocessor. Companion coprocessor & 8048768048+3C? the processorGs internal speed is do%$led.68048+3C4? the processorGs internal speed is tripled.6CC48+,@C?C)ri8 processor that is $asicall) a "8+,C.6CC48+3@C?C)ri8 processor that is 48+3C.6CC48+3RH?C)ri8 processor that is 48+3C. Fourth Generation (P4) 0.3 48+ 4-88+548+ that r%ns at 1"".Hz,ome 48+ mother$oards s%pport this chip,imilar to 2enti%m 7-60.3 08048+3C&80,A81 440.Hz 8 560.3 08048+3C4&100,A81 4"".Hz 8 "560.3 08048+3C4&10,A81 440.H8 8 "5 Fifth Generation (P5)+4&$it data $%s6 separate 8K1 internal caches! 1 for instr%ctions! 1 for data6s%perscalar microprocessor! r%ns m%ltipleinstr%ctions sim%ltaneo%sl)achie=ed $) pipelinin* 62ipelinin* $reaks instr%ction c)cle into small sta*es.>ach sta*e is capa$le of handlin* man) instr%ctions.6'#o pipelines in penti%m! %&pipe and =&pipe6>ach pipeline has its o#n 0@H Pipelining ;etchin* and e8ec%tion of each instr%ction is split into man) sta*es! all #orkin* in parallel.'his allo#s the processin* of %p to fi=e instr%ctions to $e o=erlapped. Pipelining In 808- there #as no pipelinin*.808+ had enIo)ed the first pipelinin*.In the 48+ the pipeline sta*e is $roken do#n e=en f%rther! to - sta*es as follo#s? 61. fetch 4prefetch5 6. decode 1 4t#o sta*e decode56". decode64. e8ec%te 6-. re*ister #rite&$ack 4res%lt *oes to >0C5 pipelined s! nonpipelined e"ecution Pipelining Pipelining InstructionFetchInstructionDecodeOperandFetchInstructionExecutionWriteBackStage 1 Stage 2 Stage 3 Stage 4 Stage 5Stage 1Stage 2Stage 3Stage 4Stage 5111112222233333444445555566666

!!!!!"""""12 3 45 6! "#i$e heail# pipelining 1) hea=il) pipelinin* the fetchin* and e8ec%tion of instr%ctions! man) 48+ instr%ctions are e8ec%ted in onl) 1 clock c)cle instead of in " clocks as in the "8+. Fifth Generation (P5) 2enti%m ;irst 8ternal le=elcache t)picall) -+K1 or -1K160ddition of -7 instr%ctions related to m%ltimedia and comm%nication processin*.60=aila$le in 1++7007++ .Hz clock speeds.6ReJ%ires different =olta*e le=el"."A for I7/.8A for core $ther Fifth%Generation Processors0.36K-Competes #ith Classic 2enti%m/ffers an assortment of clock speeds and $%s speedsCompati$le #ith most mother$oards that s%pported 2enti%ms61I/, mi*ht need to $e %p*raded6=olta*e le=el sli*htl) different & ".-A0=aila$le as?62R7-! 2R90! 2R100! 2R10! 2R1""! 2R&1++ $ther Fifth%Generation Processors ;eat%res?1+K1 instr%ction cache3)namic e8ec%tion;i=e&sta*e RI,C&like pipeline;2H2in&selecta$le clock m%ltiples of 1.-8 D 8I3' Centa%r C+ Binchip6,ocket&7 compati$le6,peeds of 180! 00! -! 40 .Hz6Eot s%perscalar6,lo#er #ith m%ltimedia applications and *ames6,maller! less po#er cons%mption Si"th%Generation (P&)3)namic >8ec%tion3%al Independent 1%s 0rchitect%re1etter ,%perscalar 3esi*n2enti%m 2ro?6"87 pin packa*e6has on&$oard 4incl%ded #ith the C2H $%t not internal5 @ cache! either -+! -1K1 or 1.1 r%nnin* at f%ll core speed Si"th%Generation (P&) 2enti%m 2ro mother$oards J%ite often ha=e sockets for t#o C2Hs 6Recommended for applications that rel) hea=il) on fast access to cache memor)60pplications that foc%s on comple8 calc%lations! rather than on ser=ers! need this hi*h&speed performance63oes not perform #ell #ith older 1+&$it le*ac) applications #ritten for 3/, or Bindo#s ".8 Si"th%Generation (P&) 2enti%m II61asicall) the same as 2enti%m 2ro e8ceptHas ..C,ame @e=el 1 cache size as 2enti%m ..C 4"K52acka*e chan*ed from 2d*e Contact 4,>C5 cartrid*e@ cache of -1K1 at half core speedSP''( CP) C*$C+ M$T,'-.$/-( SP''("" .Hz ".-8 ++ .Hz++ .Hz 48 ++ .Hz"00 .Hz 4.-8 ++ .Hz""" .Hz -8 ++ .Hz"-0 .Hz ".-8 100 .Hz400 .Hz 48 100 .Hz4-0 .Hz 4.-8 100 .Hz Si"th%Generation (P&) 2enti%m II Ceon62+-1K1! 1.1! or .1 of @ Cache r%nnin* at f%ll core speed Si"th%Generation (P&) Celeron62+ #ith no @ cache62acka*ed in ,in*le >d*e 2rocessor 2acka*e 4,>22 or ,>25almost the same as ,>C! missin* plastic cartrid*e co=er6Celerons a$o=e "00 .Hz also fo%nd in 2lastic 2in 2"00 .Hz Eo ,>2"00&0 .Hz Kes ,>2! 222! 222! 222! 22CC5 Si"th%Generation (P&) Processor Me1or#%/ddressing Capa2ilities 2enti%m III 7 II Ceon6lar*er ,>C packa*e 6connects to mother$oard =ia ,lot $ther Si"th%Generation Processors6Ee8*en E8-8+Eot pin compati$le #ith 2enti%ms6normall) soldered on mother$oardsHad all fifth&*eneration feat%resHad si8th&*eneration feat%re of $ranch predictionHad RI,C coreBas discontin%ed after mer*er #ith 0.360.3&K+Competes #ith 2enti%m IIHses ..C technolo*)In earl) tests! performed faster than 2enti%m II in normal $%siness applications Processor Me1or#%/ddressing Capa2ilities 0.3&K+,ocket 7 interface,i8th&*eneration internal desi*n! fifth&*eneration interface60.3&K+&Hi*her clock speedsHi*her $%s speeds of %p to 100.Hz"3Eo#L 1 ne# *raphics and so%nd processin* instr%ctions60.3&K+&"-+K1 of on&die f%ll core speed @ cache Processor Me1or#%/ddressing Capa2ilities .other$oards m%st $e a$le to s%pport 0.3 =olta*es..%st ha=e 0.3&K+ processor read) 1I/,60.3&K7 40thlon5Cartrid*e t)pe packa*in*! ,lot 0! not compati$le #ith 2enti%m II 7 III mother$oards,peeds of --0 .Hz and %p18K1 @1 cache-1K1 @ cache! r%nnin* at 17! 7-! or 17" processor speed dependin* model0thlon & 'h%nder$ird has -+K on&processor cachedoes not s%pport ,,> instr%ctions60.3 3%ron'he same as the 0thlon #ith a smaller @ cache,ocketed processor #hich fits in ,ocket 0. Processor Me1or#%/ddressing Capa2ilities C)ri8 .edia