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MICROELECTRONICS ELCT 703 (W17)
LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN
Dr. Eman Azab
Assistant Professor
Office: C3.315
E-mail:
[email protected]. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
1
TWO STAGE CMOS OP-AMP
It consists of two stages:
First stage amplifier is a differentialamplifier: Q1-Q2 with active loadsQ3-Q4 and biasing current sourceQ5- Q8
Second stage amplifier is a CommonSource amplifier Q6 with active loadQ7
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
2Figure from Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.
TWO STAGE CMOS OP-AMP
The two stage CMOS op-amp can be modeled as follows:
Gm1 & Gm2 is the trans-conductance gains of the 1st and 2nd stage respectively
R1 & R2 is the output resistances of the 1st and 2nd stage respectively
C1 & C2 is the parasitic capacitances of the 1st and 2nd stage respectively
Cc is used as a compensation capacitance to control the bandwidth
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
3Figure from Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.
TWO STAGE CMOS OP-AMP
The model parameters are derived at the mid-band (All capacitors areopen circuit)
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
4
𝑉𝑜1 = −𝑔𝑚1,2𝑅1 𝑉1 − 𝑉2
𝑅1 = 𝑟𝑑𝑠2 ∕∕ 𝑟𝑑𝑠4
𝑉𝑜𝑢𝑡 = −𝑔𝑚6𝑅2𝑉𝑜1
𝑅2 = 𝑟𝑑𝑠6 ∕∕ 𝑟𝑑𝑠7
𝐺𝑚1 = 𝑔𝑚1,2
𝐺𝑚2 = 𝑔𝑚6
𝐴𝑉𝑑 = 𝑔𝑚1,2𝑔𝑚6𝑅1𝑅2
TWO STAGE CMOS OP-AMP
Op-amp High frequency gain is given by:
The transfer function is characterized by two poles and one zero
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
5
𝐴𝑉𝑑 𝑠 =𝐺𝑚1𝐺𝑚2𝑅1𝑅2 1 −
𝐶𝑐𝐺𝑚2
𝑠
1 + 𝑠 𝐶𝐶 + 𝐶2 𝑅2 + 𝐶𝐶 + 𝐶1 𝑅1 + 𝐺𝑚𝑅1𝑅2𝐶𝐶 + 𝑠2𝑅1𝑅2 𝐶𝐶𝐶1 + 𝐶𝐶𝐶2 + 𝐶1𝐶2
TWO STAGE CMOS OP-AMP
Op-amp High frequency gain is given by:
CC controls the bandwidth of the op-amp!
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
6
𝐴𝑉𝑑 𝑠 =𝐴𝑉𝑜 1 −
𝑠𝜔𝑧
1 +𝑠
𝜔𝑝11 +
𝑠𝜔𝑝2
𝐴𝑉𝑜 = 𝐺𝑚1𝐺𝑚2𝑅1𝑅2
𝜔𝑧 =𝐺𝑚2
𝐶𝑐𝜔𝑝1 ≅
1
𝐺𝑚2𝑅1𝑅2𝐶𝑐𝜔𝑝2 ≅
𝐺𝑚2𝐶𝑐𝐶1𝐶2 + 𝐶𝐶 𝐶1 + 𝐶2
≈𝐺𝑚2
𝐶1 + 𝐶2
COMPENSATION THEORY Stability of Closed-loop
Systems
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
7
CLOSED-LOOP SYSTEMS USING OP-AMPS
Voltage op-amps are used to realize different analog signal processingapplications
Negative feedback concept is used to implement these applications
Example: Inverting amp.
This transfer function is derived under the assumption that the amplifier is ideal (infinitegain and zero input current)
This is a closed loop system formed with op-amp in feed-forward path and resistornetwork (R1 and R2) in the feedback path
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
8
𝑣𝑂𝑣𝐼
= −𝑅2𝑅1
Figure from Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.
CLOSED-LOOP SYSTEMS USING OP-AMPS
Comparing the inverting amplifier with the closed-loop system
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
9
𝑣𝑂𝑣𝐼
= −𝑅2𝑅1
𝐴 =𝑣𝑂𝑣𝐼
=𝑎(𝑠)
1 + 𝑎 𝑠 𝑓
𝑣𝑂𝑣𝐼
≅1
𝑓𝑓𝑜𝑟 𝑎𝑓 ≫ 1
𝑓 = −𝑅1𝑅2 𝐴(𝜔 = 0) =
𝑎(𝜔 = 0)
1 + 𝑎(𝜔 = 0) 𝑓
Figure from Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.
CLOSED-LOOP SYSTEMS USING OP-AMPS
Closed-loop system employingnegative feedback must be stablefor proper operation
Thus, the system eqn. roots mustsatisfy the stability condition , Polesare in the left half plane
A critically stable system isrealized when the poles are on thej𝜔 axis
Since the feedback network ispurely passive, the stabilitydepends on the amplifier’sfrequency response “a(s)”
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
10
𝑎𝑓 @𝑢𝑛𝑖𝑡𝑦 𝑔𝑎𝑖𝑛 𝑓𝑟𝑒𝑞.= 1 = 0𝑑𝐵
Phase 𝑎𝑓 @𝑢𝑛𝑖𝑡𝑦 𝑔𝑎𝑖𝑛 𝑓𝑟𝑒𝑞.> 180°
CLOSED-LOOP SYSTEMS USING OP-AMPS
An important frequency is theunity gain freq. 𝝎𝑻The frequency at which the loop gain𝑎 𝑠 = 𝜔𝑇 × 𝑓 = 1 magnitude equalsto one (Zero dB)
Critically stable system condition
Phase margin is an indication forstability
It is calculated as the phase of the loopgain at the unity gain frequency (Criticalstable condition)
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
11
𝑎𝑓 @𝑢𝑛𝑖𝑡𝑦 𝑔𝑎𝑖𝑛 𝑓𝑟𝑒𝑞.= 1 = 0𝑑𝐵
Phase 𝑎𝑓 @𝑢𝑛𝑖𝑡𝑦 𝑔𝑎𝑖𝑛 𝑓𝑟𝑒𝑞.> 180°
𝐴 =𝑣𝑂𝑣𝐼
=𝑎(𝑠)
1 + 𝑎 𝑠 𝑓
𝐶𝑟𝑖𝑡𝑐𝑎𝑙𝑙𝑦 𝑠𝑡𝑎𝑏𝑙𝑒 𝑠𝑦𝑠𝑡𝑒𝑚 @ 1 + 𝑎 𝑠 = 𝜔𝑇 𝑓 = 0
𝑃ℎ𝑎𝑠𝑒 𝑚𝑎𝑟𝑔𝑖𝑛 = 180° + Phase 𝑎 𝑠 = 𝜔𝑇 𝑓
CLOSED-LOOP SYSTEMS USING OP-AMPS
A standard 60 deg. Phase marginis sufficient to stabilize the loop andreduce the overshoot in the systemtransient response
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
12
𝑎𝑓 @𝑢𝑛𝑖𝑡𝑦 𝑔𝑎𝑖𝑛 𝑓𝑟𝑒𝑞.= 1 = 0𝑑𝐵
Phase 𝑎𝑓 @𝑢𝑛𝑖𝑡𝑦 𝑔𝑎𝑖𝑛 𝑓𝑟𝑒𝑞.> 180°
𝐴 𝑠 = 𝜔𝑇 =𝑎 𝑠 = 𝜔𝑇
1 + 𝑒−𝑗120°
𝐶𝑟𝑖𝑡𝑐𝑎𝑙𝑙𝑦 𝑠𝑡𝑎𝑏𝑙𝑒 𝑠𝑦𝑠𝑡𝑒𝑚 @ 1 + 𝑎 𝑠 = 𝜔𝑇 𝑓 = 0
𝑃ℎ𝑎𝑠𝑒 𝑚𝑎𝑟𝑔𝑖𝑛 = 180° − 120° = 60°
Phase 𝑎 𝑠 = 𝜔𝑇 𝑓 = −120°
𝑎 𝑠 = 𝜔𝑇 × 𝑓 = 1 𝑎 𝑠 = 𝜔𝑇 =1
𝑓
𝐴 𝑠 = 𝜔𝑇 =1
𝑓
COMPENSATION OF CLOSED LOOP AMP.
Assume that a(s) is a three pole amplifier, and f=1
The phase margin is negative for the closed loop
We have to stabilize the loop by adding a dominant pole to the system
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
13
EX.: COMPENSATION OF OP-AMPS By adding a compensating capacitoracross the second stage, we can controlthe phase margin of the op-amp
Increasing the phase margin stabilizeany closed-loop system realized using theop-amp
We have to select the value of Cc toachieve the desired phase margin
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
14
𝐴𝑉𝑑 𝑠 =𝐴𝑉𝑜 1 −
𝑠𝜔𝑧
1 +𝑠
𝜔𝑝11 +
𝑠𝜔𝑝2 𝜔𝑧 =
𝐺𝑚2
𝐶𝑐
𝜔𝑝1 ≅1
𝐺𝑚2𝑅1𝑅2𝐶𝑐𝜔𝑝2 ≈
𝐺𝑚2
𝐶1 + 𝐶2
COMPENSATION OF OP-AMPS
The first pole P1 is the dominant pole (verysmall compared to the zero and the secondpole)
P1 introduces 90° phase shift before theunity gain frequency
The phase margin is affected by the secondpole and zero
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
15
𝐴𝑉𝑑 𝑠 =𝐴𝑉𝑜 1 −
𝑠𝜔𝑧
1 +𝑠
𝜔𝑝11 +
𝑠𝜔𝑝2
≅𝐴𝑉𝑜
1 +𝑠
𝜔𝑝1
≈𝐴𝑉𝑜𝜔𝑝1
𝑠
𝜔𝑧 =𝐺𝑚2
𝐶𝑐𝜔𝑝1 ≅
1
𝐺𝑚2𝑅1𝑅2𝐶𝑐𝜔𝑝2 ≈
𝐺𝑚2
𝐶1 + 𝐶2
𝑢𝑛𝑖𝑡𝑦 𝑔𝑎𝑖𝑛 𝑓𝑟𝑒𝑞.≡ 𝜔𝑇 ≈ 𝐴𝑉𝑜𝜔𝑝1
EXAMPLE
For a two stage voltage Op-amp given in figure, calculate the unity gainfrequency and phase margin?
For stable system the phase margin should be greater than zero
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
16
𝐴𝑉𝑑 𝑠 =𝐴𝑉𝑜 1 −
𝑠𝜔𝑧
1 +𝑠
𝜔𝑝11 +
𝑠𝜔𝑝2
𝑃ℎ𝑎𝑠𝑒 𝑚𝑎𝑟𝑔𝑖𝑛 = 180° − tan−1𝜔𝑇
𝜔𝑧− tan−1
𝜔𝑇
𝜔𝑝1− tan−1
𝜔𝑇
𝜔𝑝2𝐴𝑉𝑑 𝑗𝜔𝑇 =
𝐴𝑉𝑜 1 +𝜔𝑇𝜔𝑧
2
1 +𝜔𝑇𝜔𝑝1
2
1 +𝜔𝑇𝜔𝑝2
2
= 1
COMPENSATION OF OP-AMPS
Note: To check the speed of op-amp, the Slew rate iscalculated/measured
Slew rate is the rate of change of the output voltage, when the op-amp is used as a buffer at unit step input
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
17
𝑆𝑅 =𝑑𝑉𝑂𝑑𝑡
𝑉𝑖(𝑡) = 2 𝑉𝑖(𝑠) =2
𝑠
𝐴𝐹𝐵 𝑠 ≈1
1 +𝑠
𝜔𝑝1
𝑉𝑂(𝑠) =2
𝑠×
1
1 +𝑠
𝜔𝑝1
𝑉𝑂(𝑡) = 2 × 1 − 𝑒−𝜔𝑝1𝑡
Figure from Gray/Meyer Copyright © by John Wiley & Sons, Inc.
COMPENSATION OF OP-AMPS
The higher the 3-dB frequency is the fasterthe output response
However, the high input voltage causes theinput stage to saturate (Q1 off and Q2 on)
Thus all the current of Q5 will flow in CC
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
18
𝑆𝑅 =𝑑𝑉𝑂𝑑𝑡
=𝐼𝐷5𝐶𝑐
𝑉𝑂(𝑡) = 2 × 1 − 𝑒−𝜔𝑝1𝑡
Predicted Response Actual Response
Figure from Gray/Meyer Copyright © by John Wiley & Sons, Inc.
NOTES
We can control the op-amp specs asfollows:
Choosing the transistors’ trans-conductance gaingm controls the gain (Change biasing current ID orAspect ratio W/L)
gm can be used to control poles (consequently itcontrols phase margin, stability and slew rate)
There are different techniquesto change the poles of the op-amp (Check the reference!)
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
19
DESIGN EXAMPLE CMOS Op-amp design
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
20
CMOS DESIGN OF VOLTAGE OP-AMPS
For the two stage op-amp shown inFigure, find the following:
All DC currents as a function of IREF
Expression of the mid-band gain
The maximum and minimum input voltagerange
The maximum and minimum output Voltagerange
Expressions of the poles and zeros
If the zero is 5 times the unity gainfrequency, what is the value of the secondpole to achieve 45° phase margin?
DR. EMAN AZAB
ELECTRONICS DEPT., FACULTY OF IET
THE GERMAN UNIVERSITY IN CAIRO
21