mb88f33x ‘indigo2(-x)’ · the mb88f33x ‘indigo2(-x)’ device belongs to the indigo family...

June 18, 2014 hm-mb88F33x-indigo2(-x)-rev1-20

Hardware Manual

Fujitsu Semiconductor Europe GmbH

Rev1-20June 18, 2014

Attached files

MB88F33x ‘Indigo2(-x)’

ii hm-mb88F33x-indigo2(-x)-rev1-20 June 18, 2014

Fujitsu Semiconductor Europe GmbH MB88F33x ‘Indigo2(-x)’

Preface

PrefaceIntention and Target Audience of this DocumentThis document describes and gives you detailed insight to the stated Fujitsu semiconductor product.

The MB88F33x ‘Indigo2(-x)’ device belongs to the Indigo Family used for graphics applications.

The target audience of this document is engineers developing products which will use the MB88F33x‘Indigo2(-x)’ devices. It describes the function and operation of the devices. Please read this documentcarefully.

TrademarksAPIX is a registered trademark of Inova Semiconductors GmbH, Grafinger Str. 26, 81671 Munich,Germany

ARM is a registered trademark of ARM Limited in UK, USA and Taiwan.

ARM is a trademark of ARM Limited in Japan and Korea.

System names and product names which appear in this document are the trademarks of the respectivecompany or organization.

LicensesUnder the conditions of Philips corporation I2C patent, the license is valid where the device is used inan I2C system which conforms to the I2C standard specification by Philips Corporation.

The purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to usethese components in an I2C system, provided that the system conforms to the I2C StandardSpecification as defined by Philips.

Supplementary Documentation For additional technical documentation, please visit out Website. (http://www.fujitsu.com/emea/services/microelectronics/gdc/gdcdevices/mb88f334-indigo2.html)

APIX FIR Setup APIX PCB-Design Guideline Device Setup and Fujitsu Developer Suite Host Interface and Level Shifter Handling Using Bootmode 2&3 External Flash DFE Setup

For additional application notes that handle the use of the APIX® interface, please visit InovaSemiconductors GmbH Website (Inova Semiconductors GmbH).

Attached Files pinning.xlsx SetupTools_Iris-MVL.xls Erase_Sector_3.txt Write_16Bit_Sector.txt Write_32Bit_Sector.txt

http://www.fujitsu.com/emea/services/microelectronics/gdc/gdcdevices/mb88f334-indigo2.htmlhttp://www.fujitsu.com/emea/services/microelectronics/gdc/gdcdevices/mb88f334-indigo2.htmlhttp://www.fujitsu.com/emea/services/microelectronics/gdc/gdcdevices/mb88f334-indigo2.htmlhttp://www.fujitsu.com/emea/services/microelectronics/gdc/gdcdevices/mb88f334-indigo2.htmlhttp://www.inova-semiconductors.de/en/design_application_notes.htmlhttp://www.inova-semiconductors.de/en/design_application_notes.htmlhttp://www.inova-semiconductors.de/en/design_application_notes.htmlhttp://www.fujitsu.com/emea/services/microelectronics/gdc/gdcdevices/mb88f334-indigo2.htmlhttp://www.fujitsu.com/emea/services/microelectronics/gdc/gdcdevices/mb88f334-indigo2.html

MB88F33x ‘Indigo2(-x)’ Fujitsu Semiconductor Europe GmbH

History

Revision Date Author Description

0-01 03.08.2012 AvT/RvR Preliminary first version

0-02 12.10.2012 Avt/RvR Revised and extended version

0-03 25.10.2012 AvT/RvR Revised and updated:- Section 1.7. Unused pins added- Section 2.3. Global Control Register added- Section 7.5.11. Low voltage Detection added- Figure 7-10 updated- Table 7-10 updated

0-04 13.12.2012 AvT/RvR Revised and updated:- Section 1.9. Figures updated- Section Interrupt Table added- Section 3.2.3. Related Pins added- Section 7.6.3. Configuration pins added

0-05 18.01.2013 AvT/RvR The following chapters has been revised and updated:- APIX- USART/LIN - Programmable CRC- External Interrupt Controller

0-06 26.02.2013 RvR Revised and updated:- Figures 1-9, 1-10. 1-11 updated.- Section System Watchdog - Functional Description updated.- Section command sequencer watchdog updated.- Sections Watchdog reset and watchdog set-up updated- Section Power-up updated

0-07 26.03.2013 RvR Revised and updated:- Section AShell Messages Overview - notations revised- Section Event Messages - Example added, Register names updated. - AShell Remote Handler Register Overview table - Register description updated. Note added- AShell Remote Handler Operation - AShell Downstream lock/Unlock Write, Note added.- Iris-MVL - Display buffer: Restrictions added to sections Buffer format, Scan Directions and Simple Scaling- Section IO Circuits added- Figure 7-10: Supply Power on Sequence updated.

0-08 17.05.2013 RvR Revised and updated:- AXI-Flash Interface chapter extended- Section 7.6.11 SMC Outputs added

0-09 02.07.2013 RvR Revised and updated:- Figure 2-2: Clock structure- Table 2-7: Boostrap setting - CFG-4 Function- Interrupt table added.- ConfigFIFO - Max. size for one channel added.- APIX2 MII - Half duplex operation not supported.- APIX2 MII - Section MII Multiplexer added.- Section E2IP Dynamic Re-Configuration revised.- Section “Daisy-chain Operation” revised.- Clock Setup of Iris-MVL - Figures updated- Power Consumption - Section updated.- IO Circuits - Revised and updated. New type (IN50) added.- AC Limits - Section ADC added.- Iris MVL - Dual channel operation setting added.- Figures 3-33, and 3-36 updated.- Section 2.4.5 Clock Synthesis - Note added.

June 18, 2014 hm-mb88F33x-indigo2(-x)-rev1-20 iii


1-00 12.11.2013 RvR Completely revised and updated.- Section “2.4.5 Clock Synthesis” - “Example:”updated.- Section “2.4.7 Internal Display PLL” added.- Section “2.9 Software Interface” updated.- Section “3.3 Bus Matrix - Address Map” and Figure 3-16 rectified.- Table 5-4 in section Configuring Display Output Pins (Multiplexing) updated.- Section “Writing 8bit/16bit Register” added- Section “6.8.3 Operation of Programmable Pulse Generator” updated.- Table 6-32 in section “6.9.4.3 Trigger Input/Output” updated.- “Chapter 7: Electrical Characteristics” completely revised. Figures and tables updated.

1-10 14.03.2014 RvR Revised and updated:- Table 2-8, “Interrupts” rectified.- Figure 3-7, “Host Interface (clock timing and phase)” rectified.- Table 4-7, “Event messages” rectified.- Register names in sections “6.5.3.1 PWM Generation” and “6.5.3.5 Sound Generator Output Generation Logic” rectified.- Table 6-36, “Clock sources for CSL0/1/2 bit settings” in section “Reload Timer Additional Register Information” corrected.- For the IO circuit type “DISP_D” in Table 7-6, “IO circuit types” , two additional tables for “Differential mode” added.

1-11 20.03.2014 RvR Revised and updated:- Figure 3-7, “Host Interface (clock timing and phase)” rectified.- Max. pic_clk for RSDS single channel (Table 5-1 ) rectified.- Added Differential Mode table in IO circuit type “DISP_D” - Table 7-6, “IO cir-cuit types”” rectified.

1-20 18.06.2014 RvR Revised and updated. Major changes:- Note added to section “4.7.5.4 Power-Up Initialization” - Figure 7-10, “Clock Input” updated- Table 7-15, “Clock Input” updated- Table 7-6, “IO circuit types” updated- Section “7.11 FLASH Memory Program/Erase Characteristics” added

Revision Date Author Description

iv hm-mb88F33x-indigo2(-x)-rev1-20 June 18, 2014


Table of ContentsSection Page

Chapter 1: Overview ........................................................................................................................... 1-11.1 General ...................................................................................................................................... 1-11.2 Features ..................................................................................................................................... 1-11.3 Block Diagrams .......................................................................................................................... 1-3

1.3.1 MB88F334 ‘Indigo2’ ......................................................................................................... 1-31.3.2 MB88F335 ‘Indigo2-S’ ...................................................................................................... 1-41.3.3 MB88F336 ‘Indigo2-N’ ..................................................................................................... 1-5

1.4 Package ..................................................................................................................................... 1-61.5 Pinning ....................................................................................................................................... 1-7

1.5.1 MB88F33x ‘Indigo2(-x)’ ...................................................................................................... 1-71.5.1.1 Pinning Overview............................................................................................................. 1-7

1.6 Pin Descriptions ......................................................................................................................... 1-81.7 Unused Pins ............................................................................................................................... 1-81.8 Pin Multiplexing .......................................................................................................................... 1-9

1.8.1 Pinmux Registers ............................................................................................................... 1-91.9 Display Output ........................................................................................................................... 1-9

1.9.1 TTL/RSDS/LVDS Channel Assignment ............................................................................. 1-9

Chapter 2: Global Control .................................................................................................................. 2-12.1 General ...................................................................................................................................... 2-12.2 Block Diagram ............................................................................................................................ 2-12.3 Global Control Register .............................................................................................................. 2-2

2.3.1 Unlocking Global Control Register ..................................................................................... 2-22.3.2 Global Control Register Overview ..................................................................................... 2-3

2.4 Clock Structure .......................................................................................................................... 2-82.4.1 Overview ............................................................................................................................ 2-82.4.2 Spread Spectrum Clock Generation ................................................................................ 2-102.4.3 Crystal Oscillator (XTAL) ................................................................................................. 2-102.4.4 Functional Description ..................................................................................................... 2-112.4.5 Clock Synthesis ............................................................................................................... 2-132.4.6 Clock Modulation / Spread Spectrum .............................................................................. 2-132.4.7 Internal Display PLL ......................................................................................................... 2-15

2.5 Reset ........................................................................................................................................ 2-162.5.1 Power On Reset .............................................................................................................. 2-16

2.6 Bootstrap Configuration ........................................................................................................... 2-172.7 Failure Unit ............................................................................................................................... 2-18

2.7.1 Panic Switch .................................................................................................................... 2-182.7.2 Alive Sender .................................................................................................................... 2-182.7.3 Low Voltage Detection (LVD) .......................................................................................... 2-182.7.4 System Watchdog ............................................................................................................ 2-192.7.4.1 Functional Description ................................................................................................... 2-19

2.8 Interrupt Controller ................................................................................................................... 2-202.8.1 Interrupt Handling ............................................................................................................ 2-202.8.2 HOST_INT Output ........................................................................................................... 2-202.8.3 Command Sequencer Interrupts ...................................................................................... 2-202.8.4 Remote Handler Events ................................................................................................... 2-202.8.5 DMA Controller Requests ................................................................................................ 2-202.8.6 Interrupt Table ................................................................................................................. 2-21

2.9 Software Interface .................................................................................................................... 2-262.10 System Power-up ................................................................................................................... 2-27

Chapter 3: System ............................................................................................................................... 3-13.1 General ...................................................................................................................................... 3-13.2 Host Interface ............................................................................................................................. 3-2

3.2.1 Features ............................................................................................................................. 3-23.2.2 Block Diagram ................................................................................................................... 3-2

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3.2.3 Related Pins ...................................................................................................................... 3-33.2.4 Functional Description ....................................................................................................... 3-43.2.4.1 SPI Interface .................................................................................................................... 3-4

3.2.4.1.1 Write Access........................................................................................................... 3-43.2.4.1.2 Read Access .......................................................................................................... 3-6

3.2.4.2 Interrupt ........................................................................................................................... 3-83.2.4.2.1 AHB Slave Module Access Error Response........................................................... 3-8

3.2.5 Data Formats ..................................................................................................................... 3-83.2.5.1 Host Interface (Clock Timing and Phase) ........................................................................ 3-83.2.5.2 Reset Frame.................................................................................................................... 3-83.2.5.3 Signal Input Format from the Host CPU .......................................................................... 3-9

3.2.5.3.1 Non-continuous Data Bytes with Non-continuous HOST XCS............................... 3-93.2.5.3.2 Non-continuous Data Bytes with Continuous HOST XCS.................................... 3-103.2.5.3.3 Continuous Data Bytes with Continuous HOST XCS........................................... 3-10

3.2.6 Processing Flow .............................................................................................................. 3-113.2.6.1 Begin Timing of Protocol Sequence .............................................................................. 3-113.2.6.2 Receive Operation and the STATUS Byte..................................................................... 3-113.2.6.3 Setting the Address ....................................................................................................... 3-113.2.6.4 Handling of Irregular Operating Conditions ................................................................... 3-12

3.2.6.4.1 The First CMD is a Dummy Command................................................................. 3-123.2.6.4.2 The First CMD is a Reset Request....................................................................... 3-12

3.3 Bus Matrix - Address Map ........................................................................................................ 3-133.3.1 Overview .......................................................................................................................... 3-133.3.2 The third layer is a peripheral layer for all peripherals which operate at max. 40 MHz. Address Map .............................................................................................................................................. 3-13

3.4 SRAM Memory ......................................................................................................................... 3-173.4.1 Overview .......................................................................................................................... 3-17

3.5 Flash Memory .......................................................................................................................... 3-183.6 Flash AXI Interface (TCFLASH) ............................................................................................... 3-19

3.6.1 Features ........................................................................................................................... 3-193.6.2 Limitations ........................................................................................................................ 3-193.6.3 Block Diagram ................................................................................................................. 3-203.6.4 Detailed Functional Description ....................................................................................... 3-213.6.4.1 Flash Memory ............................................................................................................... 3-213.6.4.2 Flash Memory Operation Mode ..................................................................................... 3-213.6.4.3 Flash Memory Address/Sector Mapping........................................................................ 3-213.6.4.4 TCFLASH Programming................................................................................................ 3-213.6.4.5 ECC Logic...................................................................................................................... 3-233.6.4.6 Interrupts........................................................................................................................ 3-233.6.4.7 Bus Error Response ...................................................................................................... 3-233.6.5 Starting the Flash Memory Automatic Algorithm ............................................................. 3-243.6.5.1 Command Sequence Table ........................................................................................... 3-243.6.6 Confirming the Automatic Algorithm Execution State ...................................................... 3-253.6.6.1 Hardware Ready Flag.................................................................................................... 3-253.6.7 Detailed Explanation of Writing to and Erasing Flash Memory ........................................ 3-263.6.7.1 Detailed Explanation of Flash Memory Write/erase....................................................... 3-263.6.8 Setting Read/Reset State ................................................................................................ 3-263.6.8.1 Read/Reset Command Sequence ................................................................................. 3-263.6.8.2 Setting the Flash Memory to the Read/reset State........................................................ 3-263.6.9 Writing Data by Submitting the Write Command Sequence ............................................ 3-273.6.9.1 Write Command Sequence............................................................................................ 3-273.6.9.2 Starting the Write Automatic Algorithm.......................................................................... 3-27

3.6.9.2.1 Example for Writing to the Flash Memory ............................................................ 3-283.6.10 Erasing User Data (Sector Erase) ................................................................................. 3-293.6.10.1 Sector Erase Command Sequence ............................................................................. 3-293.6.10.2 Starting the Sector Erase Automatic Algorithm ........................................................... 3-29

vi hm-mb88F33x-indigo2(-x)-rev1-20 June 18, 2014



3.6.10.3 Example for Erasing Sectors in the Flash Memory ..................................................... 3-293.6.11 Notes on Using Flash Memory ...................................................................................... 3-313.6.12 Internal Flash Control Register Overview ...................................................................... 3-32

3.7 HS-SPI Interface for External Flash Memory ........................................................................... 3-333.7.1 Software Interface ............................................................................................................ 3-333.7.1.1 Address Map of the External Flash Memory.................................................................. 3-33

3.8 Command Sequencer .............................................................................................................. 3-353.8.1 Overview .......................................................................................................................... 3-353.8.2 Block Diagram ................................................................................................................. 3-353.8.3 Functional Description ..................................................................................................... 3-363.8.3.1 Boot Sequence .............................................................................................................. 3-363.8.4 Processing Algorithm ....................................................................................................... 3-373.8.4.1 Boot Procedure.............................................................................................................. 3-373.8.4.2 Event Handling .............................................................................................................. 3-383.8.4.3 Command Sequencer Watchdog................................................................................... 3-393.8.4.4 Command Buffer............................................................................................................ 3-393.8.4.5 Undefined Instructions ................................................................................................... 3-393.8.5 Control Flow ..................................................................................................................... 3-403.8.6 Command Buffer .............................................................................................................. 3-403.8.7 Setup Command Sequencer Watchdog .......................................................................... 3-403.8.8 Force Termination of Command List ............................................................................... 3-413.8.8.1 Receiving an Error Response........................................................................................ 3-413.8.8.2 Restart when in HALT or ERROR State ........................................................................ 3-413.8.9 User Instruction Set ......................................................................................................... 3-413.8.9.1 Abbreviations ................................................................................................................. 3-413.8.9.2 WAIT – Wait for a Number of Microseconds ................................................................. 3-413.8.9.3 SWINT – Generate Interrupt.......................................................................................... 3-423.8.9.4 WRITE – Write Data to Buffer........................................................................................ 3-423.8.9.5 OSETREG – Write Data to Buffer with Offset................................................................ 3-433.8.9.6 DRGET – Get DREG Data ............................................................................................ 3-433.8.9.7 DRPUT – Store DREG Data.......................................................................................... 3-443.8.9.8 GETINDIRECT – Get DREG Data from AREG Address ............................................... 3-443.8.9.9 PUTINDIRECT – Store DREG Data to AREG Address................................................. 3-453.8.9.10 CHECK – Check Value of DREG ................................................................................ 3-453.8.9.11 ARGET – Get AREG Data........................................................................................... 3-453.8.9.12 LABEL – Store current address ................................................................................... 3-463.8.9.13 LOOP – Jump to label ................................................................................................. 3-463.8.9.14 WDR – Command Sequencer Watchdog Reset.......................................................... 3-463.8.9.15 WDS – Command Sequencer Watchdog Setup.......................................................... 3-473.8.9.16 JUMP – Jump to Address ............................................................................................ 3-483.8.9.17 END – End of Command List....................................................................................... 3-483.8.9.18 OR – Logical or............................................................................................................ 3-483.8.9.19 AND – Logical and....................................................................................................... 3-493.8.9.20 ADD – Add Value to DREG ......................................................................................... 3-493.8.9.21 XOR – Logical Exclusive OR....................................................................................... 3-493.8.9.22 SHR – Logical Shift Right ............................................................................................ 3-503.8.9.23 SHL – Logical Shift Left ............................................................................................... 3-503.8.9.24 JMPR – Jump Relative ................................................................................................ 3-503.8.9.25 FILL – Constant Fill...................................................................................................... 3-513.8.9.26 NOT – Bitwise not........................................................................................................ 3-513.8.9.27 DRLOAD – Load DREG Data...................................................................................... 3-523.8.9.28 DRSAVE – Save DREG Data to Buffer ....................................................................... 3-523.8.9.29 DRRESTORE – Restore DREG Data from Buffer....................................................... 3-523.8.10 Command Sequencer Register Overview ..................................................................... 3-53

3.9 Configuration FIFO .................................................................................................................. 3-543.9.1 Features of the Configuration FIFO ................................................................................. 3-54

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3.9.2 Block Diagram ................................................................................................................. 3-543.9.3 Function Description ........................................................................................................ 3-563.9.3.1 AHB Slave Interface ...................................................................................................... 3-563.9.3.2 AHB Master Interface .................................................................................................... 3-563.9.3.3 FIFO Memory................................................................................................................. 3-573.9.3.4 Trigger Request ............................................................................................................. 3-613.9.3.5 Interrupt ......................................................................................................................... 3-613.9.4 Configuration FIFO Register Overview ............................................................................ 3-63

3.10 DMA Controller ...................................................................................................................... 3-733.10.1 Features of the DMA Controller ..................................................................................... 3-733.10.2 Block Diagram of DMA Controller .................................................................................. 3-733.10.3 Operation of DMA Controller ......................................................................................... 3-743.10.3.1 Features of DMA Controller ......................................................................................... 3-743.10.3.2 Global Functions of the DMA Controller ...................................................................... 3-743.10.4 DMA Channels ............................................................................................................... 3-753.10.4.1 Modes of Operation ..................................................................................................... 3-753.10.4.2 Block Transfer Mode.................................................................................................... 3-75

3.10.4.2.1 DMA Transfer Requests ..................................................................................... 3-753.10.4.2.2 Block of Data ...................................................................................................... 3-763.10.4.2.3 DMA Transfer Size ............................................................................................. 3-813.10.4.2.4 DMA Transfer Completion and Error Handling................................................... 3-813.10.4.2.5 Channel Disabling and Halting ........................................................................... 3-81

3.10.4.3 Burst Transfer Mode .................................................................................................... 3-823.10.4.4 Demand Transfer Mode............................................................................................... 3-82

3.10.4.4.1 DMA Transfer Requests ..................................................................................... 3-823.10.4.4.2 Block of Data ...................................................................................................... 3-823.10.4.4.3 DMA Transfer Size ............................................................................................. 3-833.10.4.4.4 DMA Transfer Completion and Error Handling in Demand Transfer Mode ........ 3-833.10.4.4.5 Source and Destination Protection in Demand Transfer Mode .......................... 3-833.10.4.4.6 Channel Disabling and Halting in Demand Transfer Mode ................................ 3-83

3.10.5 DMA Client Matrix .......................................................................................................... 3-843.10.5.1 Overview...................................................................................................................... 3-843.10.5.2 MB88F33x ‘Indigo2(-x)’ Client Table ........................................................................... 3-843.10.5.3 Programming Information ............................................................................................ 3-843.10.5.4 Modes of Operation ..................................................................................................... 3-853.10.5.5 Functional Description ................................................................................................. 3-85

3.10.5.5.1 Structure of the DMA Client Matrix ..................................................................... 3-853.10.5.5.2 DMA Client Matrix Configuration ........................................................................ 3-85

3.10.5.6 Initialization and Application Information ..................................................................... 3-863.10.5.6.1 Reset .................................................................................................................. 3-86

3.10.6 DMA Arbiter ................................................................................................................... 3-863.10.6.1 Overview...................................................................................................................... 3-863.10.6.2 Fixed Priority................................................................................................................ 3-863.10.6.3 Dynamic Priority........................................................................................................... 3-873.10.6.4 Round-Robin................................................................................................................ 3-883.10.6.5 Application Information ................................................................................................ 3-88

3.10.6.5.1 Fixed Priority Arbitration ..................................................................................... 3-883.10.6.5.2 Dynamic Priority Arbitration ................................................................................ 3-883.10.6.5.3 Round-Robin Arbitration ..................................................................................... 3-88

3.10.7 DMA AHB Slave Interface ............................................................................................. 3-893.10.7.1 Supported Data Transfers ........................................................................................... 3-893.10.7.2 Data Transfer Response.............................................................................................. 3-89

3.10.7.2.1 Register Access Error......................................................................................... 3-893.10.8 DMAC Register Overview .............................................................................................. 3-90

3.11 Programmable CRC ............................................................................................................... 3-923.11.1 Features of the Programmable CRC ............................................................................. 3-92

viii hm-mb88F33x-indigo2(-x)-rev1-20 June 18, 2014



3.11.2 Areas of Application ....................................................................................................... 3-923.11.3 Block Diagram of the Programmable CRC .................................................................... 3-923.11.4 Operation of Programmable CRC .................................................................................. 3-943.11.4.1 CRC Operation Flow Charts ........................................................................................ 3-943.11.5 CRC Input Data and Checksum Calculation Flow ......................................................... 3-973.11.6 CRC Calculation Example ........................................................................................... 3-1003.11.7 Programmable CRC Register Overview ...................................................................... 3-101

Chapter 4: APIX2 Interface ................................................................................................................. 4-14.1 General ...................................................................................................................................... 4-14.2 Features ..................................................................................................................................... 4-14.3 Block Diagram ............................................................................................................................ 4-24.4 APIX2 PHY ................................................................................................................................ 4-3

4.4.1 Overview ............................................................................................................................ 4-34.4.2 Block Diagram ................................................................................................................... 4-34.4.3 Daisy-chain Operation ....................................................................................................... 4-44.4.4 Automatic Gain Control (AGC) .......................................................................................... 4-54.4.5 Application Note ................................................................................................................. 4-54.4.6 APIX2 PHY Register Overview .......................................................................................... 4-6

4.5 APIX2 RX Link Layer ................................................................................................................. 4-84.5.1 APIX1 ................................................................................................................................. 4-94.5.1.1 APIX1 Video .................................................................................................................... 4-9

4.5.1.1.1 APIX1 Data Communication................................................................................... 4-94.5.1.1.2 Overview................................................................................................................. 4-94.5.1.1.3 AShell Services ...................................................................................................... 4-94.5.1.1.4 AShell Functions..................................................................................................... 4-94.5.1.1.5 AShell Data Interface............................................................................................ 4-104.5.1.1.6 AShell Back-pressure........................................................................................... 4-104.5.1.1.7 AShell Error Control.............................................................................................. 4-104.5.1.1.8 ARQ ON, Automatic Retransmission.................................................................... 4-104.5.1.1.9 AShell Status Signals ........................................................................................... 4-114.5.1.1.10 AShell Operational.............................................................................................. 4-114.5.1.1.11 APIX1 GPIO ....................................................................................................... 4-114.5.1.1.12 GPIO Downstream ............................................................................................. 4-114.5.1.1.13 GPIO Upstream.................................................................................................. 4-11

4.5.2 APIX2 ............................................................................................................................... 4-124.5.2.1 APIX2 Video .................................................................................................................. 4-124.5.2.2 Horizontal Timing Parameter ......................................................................................... 4-124.5.2.3 Vertical Timing Parameter ............................................................................................. 4-124.5.2.4 Absolute Maximum Timings........................................................................................... 4-124.5.2.5 APIX2 Audio .................................................................................................................. 4-13

4.5.2.5.1 Audio Clock Synthesizer....................................................................................... 4-134.5.2.5.2 Audio Formats ...................................................................................................... 4-134.5.2.5.3 Supported I2S Timings......................................................................................... 4-13

4.5.2.6 APIX2 Data Communication .......................................................................................... 4-144.5.2.6.1 Overview............................................................................................................... 4-144.5.2.6.2 AShell2 Services .................................................................................................. 4-144.5.2.6.3 AShell2 Functions................................................................................................. 4-144.5.2.6.4 AShell2 Data Interface.......................................................................................... 4-154.5.2.6.5 AShell2 Freeze..................................................................................................... 4-154.5.2.6.6 AShell2 Error Control............................................................................................ 4-164.5.2.6.7 ARQ ON, Automatic Retransmission.................................................................... 4-164.5.2.6.8 ARQ OFF, With Acknowledgement ...................................................................... 4-174.5.2.6.9 AShell2 Ticket Counter......................................................................................... 4-174.5.2.6.10 AShell2 Unidirectional Mode .............................................................................. 4-18

4.5.2.7 APIX2 MII....................................................................................................................... 4-18

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4.5.2.7.1 AShell2 Bandwidth ............................................................................................... 4-194.5.2.7.2 MII Multiplexer ...................................................................................................... 4-20

4.5.2.8 AShell2 Generic Data .................................................................................................... 4-204.5.2.8.1 AShell2 Target ID ................................................................................................. 4-204.5.2.8.2 Flow Control ......................................................................................................... 4-21

4.5.2.9 APIX2 GPIO................................................................................................................... 4-214.5.2.9.1 GPIO Downstream ............................................................................................... 4-214.5.2.9.2 GPIO Upstream.................................................................................................... 4-22

4.5.3 APIX2RX Link Register Overview .................................................................................... 4-234.5.4 APIX2 HDCP Register Overview ..................................................................................... 4-25

4.6 AShell Remote Handler ........................................................................................................... 4-264.6.1 Features of the AShell Remote Handler .......................................................................... 4-264.6.2 Block Diagram ................................................................................................................. 4-274.6.3 AShell Remote Handler Operation .................................................................................. 4-284.6.3.1 AShell Messages ........................................................................................................... 4-28

4.6.3.1.1 Write Transaction ................................................................................................. 4-334.6.3.1.2 Unlock/Lock Write................................................................................................. 4-334.6.3.1.3 Read Transaction/Response................................................................................ 4-334.6.3.1.4 Event Message..................................................................................................... 4-334.6.3.1.5 Push Message...................................................................................................... 4-35

4.6.3.2 Error Handling................................................................................................................ 4-364.6.4 AShell Remote Control Handler Control Flow ................................................................. 4-374.6.4.1 Request Messages ........................................................................................................ 4-374.6.4.2 Event Message .............................................................................................................. 4-374.6.4.3 Push Message ............................................................................................................... 4-384.6.5 Application ....................................................................................................................... 4-394.6.6 Event Messages .............................................................................................................. 4-414.6.7 AShell Remote Handler Register Overview ..................................................................... 4-46

4.7 Embedded Ethernet ................................................................................................................. 4-474.7.1 Features ........................................................................................................................... 4-474.7.2 Block Diagram ................................................................................................................. 4-484.7.3 Functional Description ..................................................................................................... 4-494.7.4 Operation ......................................................................................................................... 4-514.7.4.1 RPC (AUTOSAR) .......................................................................................................... 4-514.7.4.2 ICMP Frame Format ...................................................................................................... 4-524.7.4.3 ARP Frame Format........................................................................................................ 4-534.7.5 Control Flow ..................................................................................................................... 4-544.7.5.1 Extract and Collect RPC (AUTOSAR) Payload ............................................................. 4-54

4.7.5.1.1 Remote Handler Read- and Write Messages....................................................... 4-544.7.5.1.2 Remote Handler Event Messages........................................................................ 4-544.7.5.1.3 Remote Handler Push Messages......................................................................... 4-554.7.5.1.4 Occurrence of Messages...................................................................................... 4-55

4.7.5.2 Transmit Trigger Scheme .............................................................................................. 4-564.7.5.3 Host MAC Address Exchange ....................................................................................... 4-564.7.5.4 Power-Up Initialization ................................................................................................... 4-584.7.5.5 Software Reset Procedure or Reconfiguration Procedure............................................. 4-594.7.6 Embedded Ethernet Register Overview .......................................................................... 4-60

Chapter 5: IRIS-MVL ............................................................................................................................ 5-15.1 General ...................................................................................................................................... 5-15.2 Features ..................................................................................................................................... 5-2

5.2.1 Display Controller .............................................................................................................. 5-25.3 System Setup MB88F33x ‘Indigo2(-x)’ ...................................................................................... 5-4

5.3.1 Clock Setup of Iris-MVL ..................................................................................................... 5-45.3.1.1 Pixel Clock...................................................................................................................... 5-55.3.1.2 Video Clock...................................................................................................................... 5-5

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5.3.1.3 Bit Clock........................................................................................................................... 5-55.3.1.4 Display Clock ................................................................................................................. 5-75.3.1.5 Iris Clock Control ............................................................................................................. 5-75.3.2 Configuring Display Output Pins (Multiplexing) ................................................................. 5-85.3.3 Shifting Output Data for Display ........................................................................................ 5-9

5.4 IRIS-MVL Functions ................................................................................................................. 5-105.4.1 Use Cases ....................................................................................................................... 5-105.4.2 Limitations ........................................................................................................................ 5-125.4.2.1 Display Controller .......................................................................................................... 5-125.4.3 Basic Functions ............................................................................................................... 5-125.4.3.1 Register Access............................................................................................................. 5-125.4.3.2 Shadow Registers.......................................................................................................... 5-125.4.3.3 Register Locking ............................................................................................................ 5-145.4.3.4 Interrupt Controller......................................................................................................... 5-145.4.3.5 Power Optimization........................................................................................................ 5-145.4.4 Display Controller ............................................................................................................ 5-145.4.4.1 Display Stream .............................................................................................................. 5-145.4.4.2 Memory Stream ............................................................................................................. 5-155.4.4.3 Capture Stream ............................................................................................................. 5-155.4.4.4 Safety Features ............................................................................................................. 5-165.4.5 Processing Units .............................................................................................................. 5-165.4.5.1 Fetch Unit ...................................................................................................................... 5-16

5.4.5.1.1 AXI Settings.......................................................................................................... 5-165.4.5.1.2 Source Buffer Formats ......................................................................................... 5-165.4.5.1.3 Pixel Formats........................................................................................................ 5-175.4.5.1.4 Clip and Skip Window........................................................................................... 5-185.4.5.1.5 Global Alpha......................................................................................................... 5-185.4.5.1.6 Transparent Color................................................................................................. 5-195.4.5.1.7 Multiply Modes...................................................................................................... 5-19

5.4.5.2 Frame Generator ........................................................................................................... 5-195.4.5.2.1 Scan Directions .................................................................................................... 5-195.4.5.2.2 Run-Length Decoder ............................................................................................ 5-205.4.5.2.3 Sprites .................................................................................................................. 5-20

5.4.5.3 Frame Capture Unit ....................................................................................................... 5-205.4.5.4 External Source Interface .............................................................................................. 5-20

5.4.5.4.1 Pixel Formats........................................................................................................ 5-205.4.5.4.2 Clip Window.......................................................................................................... 5-205.4.5.4.3 Transparent Color................................................................................................. 5-21

5.4.5.5 Layer Blend Unit ............................................................................................................ 5-215.4.5.5.1 Overlay ................................................................................................................. 5-215.4.5.5.2 Blending................................................................................................................ 5-215.4.5.5.3 Packing................................................................................................................. 5-225.4.5.5.4 Alpha Mask Generation........................................................................................ 5-22

5.4.5.6 External Destination Interface........................................................................................ 5-235.4.5.6.1 Performance Counter ........................................................................................... 5-23

5.4.5.7 Frame Generator ........................................................................................................... 5-235.4.5.7.1 Timing Generator.................................................................................................. 5-235.4.5.7.2 Stream Overlay..................................................................................................... 5-235.4.5.7.3 Timing Synchronization ........................................................................................ 5-245.4.5.7.4 Programmable Interrupts...................................................................................... 5-245.4.5.7.5 Panic Mode........................................................................................................... 5-25

5.4.5.8 Color Matrix ................................................................................................................... 5-255.4.5.8.1 Linear Color Transformation................................................................................. 5-255.4.5.8.2 Alpha Pre-Multiply ................................................................................................ 5-255.4.5.8.3 Alpha Masking...................................................................................................... 5-255.4.5.8.4 Display Specifics .................................................................................................. 5-25

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5.4.5.9 Color Lookup Table ....................................................................................................... 5-265.4.5.9.1 Color Lookup ........................................................................................................ 5-265.4.5.9.2 Index Lookup........................................................................................................ 5-265.4.5.9.3 Dithering ............................................................................................................... 5-265.4.5.9.4 Alpha Masking...................................................................................................... 5-265.4.5.9.5 Display Specifics .................................................................................................. 5-26

5.4.5.10 Dither Unit.................................................................................................................... 5-265.4.5.10.1 Dithering ............................................................................................................. 5-265.4.5.10.2 Alpha Masking.................................................................................................... 5-26

5.4.5.11 Timing Controller ......................................................................................................... 5-275.4.5.11.1 Control Signals ................................................................................................... 5-275.4.5.11.2 Data Modes ........................................................................................................ 5-275.4.5.11.3 Data Multiplexing ................................................................................................ 5-275.4.5.11.4 Inversion Control ................................................................................................ 5-28

5.4.5.12 Signature Unit .............................................................................................................. 5-285.4.5.12.1 Signature Computation....................................................................................... 5-285.4.5.12.2 Evaluation Window............................................................................................. 5-295.4.5.12.3 Alpha Masking.................................................................................................... 5-295.4.5.12.4 Panic Mode......................................................................................................... 5-29

5.5 IRIS-MVL Map Tables .............................................................................................................. 5-305.5.1 Interrupt Map ................................................................................................................... 5-305.5.2 Address Map .................................................................................................................... 5-315.5.3 Key Map ........................................................................................................................... 5-32

5.6 Basic Setup .............................................................................................................................. 5-335.6.1 IP Identifier ....................................................................................................................... 5-335.6.2 Interrupts .......................................................................................................................... 5-335.6.3 Clock Settings .................................................................................................................. 5-335.6.4 Reset Settings ................................................................................................................. 5-335.6.5 Power Optimization .......................................................................................................... 5-34

5.7 Display Controller ..................................................................................................................... 5-345.7.1 Getting Started ................................................................................................................. 5-345.7.1.1 Minimal Setup ................................................................................................................ 5-345.7.1.2 Display Path................................................................................................................... 5-345.7.2 Control Flow ..................................................................................................................... 5-355.7.2.1 Static.............................................................................................................................. 5-355.7.2.2 Dynamic......................................................................................................................... 5-365.7.3 Display Stream ................................................................................................................ 5-395.7.3.1 Timing Setup.................................................................................................................. 5-395.7.3.2 Display Modes ............................................................................................................... 5-405.7.3.3 Color Transformations ................................................................................................... 5-415.7.3.4 Dithering ........................................................................................................................ 5-415.7.3.5 By-pass Mode................................................................................................................ 5-425.7.3.6 TCon Mode .................................................................................................................... 5-435.7.3.7 Programmable Interrupts ............................................................................................... 5-475.7.4 Memory Stream ............................................................................................................... 5-475.7.4.1 Timing Setup.................................................................................................................. 5-475.7.4.2 Background Layer.......................................................................................................... 5-495.7.4.3 Sprite Layer ................................................................................................................... 5-495.7.5 Capture Stream ............................................................................................................... 5-495.7.5.1 Timing Setup.................................................................................................................. 5-495.7.5.2 Skew Setup.................................................................................................................... 5-515.7.5.3 Video Layer.................................................................................................................... 5-545.7.5.4 Foreground Layer .......................................................................................................... 5-555.7.5.5 Sprite Layer ................................................................................................................... 5-555.7.6 Display Buffer .................................................................................................................. 5-555.7.6.1 AXI Setup....................................................................................................................... 5-55

xii hm-mb88F33x-indigo2(-x)-rev1-20 June 18, 2014



5.7.6.2 Buffer Format................................................................................................................. 5-565.7.6.3 Pixel Format................................................................................................................... 5-565.7.6.4 Clip and Skip Window.................................................................................................... 5-565.7.6.5 Global Alpha .................................................................................................................. 5-565.7.6.6 Constant Color............................................................................................................... 5-565.7.6.7 Multiply Modes............................................................................................................... 5-575.7.6.8 Transparent Color.......................................................................................................... 5-575.7.6.9 Run-Length Decoding.................................................................................................... 5-575.7.6.10 Scan Directions............................................................................................................ 5-575.7.6.11 Simple Scaling ............................................................................................................. 5-585.7.6.12 Sprites.......................................................................................................................... 5-595.7.7 Image Processing ............................................................................................................ 5-595.7.7.1 Color Palette .................................................................................................................. 5-595.7.7.2 Linear Transformation.................................................................................................... 5-605.7.7.3 Non-linear Transformation ............................................................................................. 5-615.7.7.4 Blend Operation............................................................................................................. 5-615.7.7.5 Alpha Masking ............................................................................................................... 5-615.7.8 Safety Features ............................................................................................................... 5-635.7.8.1 Signature ....................................................................................................................... 5-635.7.8.2 Panic Mode.................................................................................................................... 5-645.7.9 Tweaking ......................................................................................................................... 5-655.7.9.1 Single Buffer Foreground Layer..................................................................................... 5-655.7.10 Iris-MVL Register Overview ........................................................................................... 5-675.7.10.1 Iris-MVL - Global Control ............................................................................................. 5-675.7.10.2 Iris-MVL - Pixelbus....................................................................................................... 5-675.7.10.3 Iris-MVL - Display Configuration .................................................................................. 5-685.7.10.4 Iris-MVL - FetchRLD.................................................................................................... 5-685.7.10.5 Iris-MVL - FetchSprite.................................................................................................. 5-695.7.10.6 Iris-MVL - ExtSrc.......................................................................................................... 5-715.7.10.7 Iris-MVL - CLuT ........................................................................................................... 5-715.7.10.8 Iris-MVL - Matrix .......................................................................................................... 5-725.7.10.9 Iris-MVL - LayerBlend .................................................................................................. 5-725.7.10.10 Iris-MVL - ExtDst........................................................................................................ 5-725.7.10.11 FrameCap.................................................................................................................. 5-735.7.10.12 Iris-MVL - FrameGen_PS .......................................................................................... 5-735.7.10.13 Iris-MVL - Dither ........................................................................................................ 5-755.7.10.14 Iris-MVL - TCon ......................................................................................................... 5-755.7.10.15 Iris-MVL - Sig ............................................................................................................. 5-78

Chapter 6: Peripherals ........................................................................................................................ 6-16.1 General ...................................................................................................................................... 6-16.2 Stepper Motor Controller ............................................................................................................ 6-2

6.2.1 Features ............................................................................................................................. 6-26.2.2 Block Diagram of the Stepping Motor Controller ............................................................... 6-26.2.3 Operation of Stepping Motor Controller ............................................................................. 6-36.2.4 Operation of PWM-pulse Generator .................................................................................. 6-46.2.5 Operation of PWM-Trigger Generator ............................................................................... 6-66.2.6 Shadow Register Setup ..................................................................................................... 6-86.2.7 Notes on Using Stepping Motor Controller ........................................................................ 6-86.2.8 Zero Point Detection .......................................................................................................... 6-86.2.9 Stepper Motor Controller Additional Register Information ................................................. 6-96.2.9.1 PWM Control Register (SMCn_PWC) ............................................................................. 6-96.2.10 Stepper Motor Controller Core Register Overview ........................................................ 6-106.2.11 Stepper Motor Controller Trigger Register Overview ..................................................... 6-11

6.3 Analog Digital Converter (ADC) ............................................................................................... 6-126.3.1 Features of the A/D Converter ......................................................................................... 6-12

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6.3.2 Block Diagram ................................................................................................................. 6-136.3.3 Operation of the A/D Converter ....................................................................................... 6-146.3.3.1 Single Mode................................................................................................................... 6-146.3.3.2 Continuous Mode........................................................................................................... 6-156.3.3.3 Stop Mode ..................................................................................................................... 6-156.3.3.4 Single-shot Conversion.................................................................................................. 6-166.3.3.5 Scan Conversion ........................................................................................................... 6-176.3.3.6 Protection of the ADC Channel Data Registers............................................................. 6-186.3.3.7 Protection of ADCn_CD27~0......................................................................................... 6-196.3.3.8 Protection of ADCn_CR................................................................................................. 6-196.3.3.9 DMA Transfer ................................................................................................................ 6-19

6.3.3.9.1 Data Protection During DMA Transfer.................................................................. 6-196.3.3.10 ADC Pulse Detection Function .................................................................................... 6-20

6.3.3.10.1 Positive Events/negative Events ........................................................................ 6-206.3.3.10.2 Working Principle of ADC Pulse Detection Function .......................................... 6-20

6.3.4 ADC Software Interface ................................................................................................... 6-236.3.5 Analog-Digital Converter Register Overview ................................................................... 6-246.3.6 Additional Information for Registers ................................................................................. 6-296.3.6.1 A/D End Channel Setting Register (ADCn_SCH).......................................................... 6-29

6.4 I2C Interface ............................................................................................................................. 6-306.4.1 Features of the I2C Interface ........................................................................................... 6-306.4.2 Operation of the I2C Interface ......................................................................................... 6-316.4.2.1 Start Conditions ............................................................................................................. 6-316.4.2.2 Stop Conditions ............................................................................................................. 6-316.4.2.3 Addressing Slaves ......................................................................................................... 6-316.4.2.4 Arbitration ...................................................................................................................... 6-326.4.2.5 Acknowledgement ......................................................................................................... 6-326.4.3 Programming Flow Charts ............................................................................................... 6-326.4.3.1 Programming Flow Charts ............................................................................................. 6-336.4.4 I2C Register Overview ..................................................................................................... 6-356.4.5 I2C Interface Additional Register Information .................................................................. 6-366.4.5.1 Bus Control and Status Register (I2Cn_IBCSR) ........................................................... 6-36

6.4.5.1.1 SCC, MSS and INT Bit Competition ..................................................................... 6-366.4.5.2 Clock Control Register (I2Cn_ICCR) ............................................................................. 6-39

6.4.5.2.1 Clock Prescaler Settings ...................................................................................... 6-396.4.5.2.2 Common Peripheral Clock Frequencies............................................................... 6-40

6.4.5.3 DMA Configuration Register (I2Cn_DDMACFG)........................................................... 6-406.5 Sound Generator ..................................................................................................................... 6-41

6.5.1 Features of the Sound Generator .................................................................................... 6-416.5.2 Block Diagram ................................................................................................................. 6-416.5.3 Operation of the Sound Generator .................................................................................. 6-426.5.3.1 PWM Generation ........................................................................................................... 6-426.5.3.2 Frequency Generation ................................................................................................... 6-436.5.3.3 Interrupt, DMA Request, and Reload Generation.......................................................... 6-436.5.3.4 Register Reload Operation ............................................................................................ 6-446.5.3.5 Sound Generator Output Generation Logic ................................................................... 6-466.5.3.6 Sound Generator Mode Control Logic ........................................................................... 6-466.5.3.7 DMA-based Sound Generator Register Update Operation ........................................... 6-466.5.3.8 DMA Transfer Flowchart................................................................................................ 6-476.5.3.9 Programming the Sound Generator Module.................................................................. 6-496.5.3.10 Using the CPU to Control Sound Generator Operation ............................................... 6-506.5.3.11 Using DMA to Control Sound Generator Operation..................................................... 6-526.5.3.12 Sound Generator Operation (Timing) .......................................................................... 6-546.5.4 Sound Generator Register Overview ............................................................................... 6-56

6.6 LIN / U(S)ART Interface ........................................................................................................... 6-576.6.1 Features of the LIN/U(S)ART Interface ........................................................................... 6-57

xiv hm-mb88F33x-indigo2(-x)-rev1-20 June 18, 2014



6.6.2 Block Diagram ................................................................................................................. 6-586.6.3 Functional Description ..................................................................................................... 6-596.6.4 Operation of LIN-USART ................................................................................................. 6-646.6.4.1 LIN-USART Operation Modes ....................................................................................... 6-646.6.4.2 Inter-CPU Connection Method....................................................................................... 6-646.6.4.3 Synchronization Methods .............................................................................................. 6-656.6.4.4 Signal Mode................................................................................................................... 6-656.6.4.5 Operation Enable Bit...................................................................................................... 6-656.6.4.6 Operation in Asynchronous Mode (Operation Modes 0 and 1) ..................................... 6-65

6.6.4.6.1 Operation in Asynchronous Mode ........................................................................ 6-656.6.4.7 Operation in Synchronous Mode (Operation Mode 2) ................................................... 6-686.6.4.8 Features of LIN-USART in LIN Mode ............................................................................ 6-716.6.4.9 Operation with LIN Function (Operation Mode 3) .......................................................... 6-73

6.6.4.9.1 Operation in Asynchronous LIN Mode (Operation Mode 3) ................................. 6-736.6.4.9.2 LIN-USART as LIN master ................................................................................... 6-736.6.4.9.3 LIN-USART - Automatic Header Detection .......................................................... 6-736.6.4.9.4 LIN Sync Break Detection Interrupt and Flags ..................................................... 6-746.6.4.9.5 LIN Bus Timing..................................................................................................... 6-75

6.6.4.10 Direct Access to Serial Pins......................................................................................... 6-756.6.4.10.1 LIN-USART Direct Pin Access ........................................................................... 6-76

6.6.4.11 Bidirectional Communication Function (Normal Mode) ............................................... 6-766.6.4.11.1 Bidirectional Communication Function ............................................................... 6-766.6.4.11.2 Inter-CPU Connection ........................................................................................ 6-79

6.6.4.12 Master-Slave Communication Function (Multiprocessor Mode) .................................. 6-796.6.4.12.1 Master-Slave Communication Function.............................................................. 6-806.6.4.12.2 Inter-CPU Connection ........................................................................................ 6-826.6.4.12.3 Function Selection .............................................................................................. 6-82

6.6.4.13 LIN Communication Function ...................................................................................... 6-846.6.4.13.1 LIN Master-slave Communication Function........................................................ 6-84

6.6.4.14 Flowcharts for LIN-USART in LIN Communication (Operation Mode 3)...................... 6-866.6.4.14.1 LIN-USART as Master Device............................................................................ 6-876.6.4.14.2 LIN-USART as Master Device with Additional Features .................................... 6-88

6.6.5 Important Notes on Using LIN-USART ............................................................................ 6-926.6.5.1 Enabling Operation ........................................................................................................ 6-926.6.5.2 Auto Header Detection in LIN Mode .............................................................................. 6-926.6.5.3 Communication Mode Setting........................................................................................ 6-926.6.5.4 Transmission Interrupt Enabling Timing ........................................................................ 6-926.6.5.5 Using LIN Operation Mode 3 ......................................................................................... 6-926.6.5.6 Chan

mb88f33x ‘indigo2(-x)’ · the mb88f33x ‘indigo2(-x)’ device belongs to the indigo family...

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