mb88f33x ‘indigo2(-x)’ - fujitsu...0-06 27.02.2013 rvr minor changes, more formatting issues....

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20

Register Descriptions

Fujitsu Semiconductor Europe GmbH

MB88F33x ‘Indigo2(-x)’

Rev1-20

June 17, 2014

ii rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014

Fujitsu Semiconductor Europe GmbH MB88F33x ‘Indigo2(-x)’

Preface

Preface

Intention and Target Audience of this Document

This document describes and gives you detailed insight to the stated Fujitsu semiconductor product.

The MB88F33x ‘Indigo2(-x)’ devices belong to the Indigo Family used for graphics applications.

The target audience of this document is engineers developing products which will use the MB88F33x ‘Indigo2(-x)’ devices. It describes the function and operation of the devices. Please read this document care-fully.

Trademarks

APIX is a registered trademark of Inova Semiconductors GmbH, Grafinger Str. 26, 81671 Munich, Germany

ARM is a registered trademark of ARM Limited in UK, USA and Taiwan.

ARM is a trademark of ARM Limited in Japan and Korea.

ARM Powered logo is a registered trademark of ARM Limited in Japan, UK, USA, and Taiwan.

ARM Powered logo is a trademark of ARM Limited in Korea.

PrimeCell: is owned by ARM Limited.

System names and product names which appear in this document are the trademarks of the respective company or organization.

Licenses

Under the conditions of Philips corporation I2C patent, the license is valid where the device is used in an I2C system which conforms to the I2C standard specification by Philips Corporation.

The purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as de-fined by Philips.

Please acquire license of MediaLB from SMSC and request the following document: OS62400 MediaLB De-vice Interface Macro Advanced Product Data Sheet.

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 iii

MB88F33x ‘Indigo2(-x)’ Fujitsu Semiconductor Europe GmbH

History

Revision Date Author Description

0-01 03.08.2012 v. Treuberg First version - Only Register overviews

0-02 12.10.2012 v. Treuberg Updated and completed Version.

0-03 26.10.2012 v. Treuberg Revised and updated

0-04 05.12.2012 v. Treuberg Rename ‘E2IP’ to ‘Embedded Ethernet’ for formalistic reasons.

0-05 18.01.2013 AvT/RvR Update register content (minor changes)

0-06 27.02.2013 RvR Minor changes, more formatting issues.

0-07 26.03.2013 RvR Updated Registers:- Flash AXI Interface Registers- HS-SPI Registers- Sound Generator Registers- LIN-USART Registers- APIX2 Registers- RLT Registers- ADC Registers- Stepper Mottor Registers- Embedded Ethernet- I2C Registers

0-08 17.05.2013 RvR Updated Registers- APIX2RX Link Registers- Embedded Internet Registers- Remote Handler Registers- ConfigFIFO Registers- APIX2 PHY Registers- CCNT Registers

0-09 02.07.2013 RvR Updated Registers- APIX2RX Link Registers- Global Control Registers- Embedded Ethernet Registers- ConfigFIFO Registers- APIX PHY Registers- CmdSeq Register

1-00 14.11.2013 RvR All Registers revised and updated.

1-10 14.03.2014 RvR All Registers revised:- Global Control Registers updated- APIX PHY Registers updated

1-11 19.03.2014 RvR Following registers have been updated:- Formula in Register APIX_CFG_3:mii_clk_freq corrected. - Wrong bit positions in all SPG-Registers (Iris MVL -TCON)- Wrong bit positions in CmdSeq Register Control corrected- Bit description in Bit field PRBS test 8B10B corrected

1-20 17.06.2014 RvR All Registers revised. Major changes:- APIX Link Registers: APIX_STAT_CTRL_1, APIX_STAT_2,


Table of ContentsSection Page

Chapter 1: Memory Map ..................................................................................................................... 1-1

Chapter 2: General Information ......................................................................................................... 2-12.1 Format ........................................................................................................................................ 2-12.2 Meaning of Items and Sign ........................................................................................................ 2-1

Chapter 3: Registers Descriptions .................................................................................................... 3-13.1 Global Control Registers ............................................................................................................ 3-2

3.1.1 Global Control Register Overview ..................................................................................... 3-3 CHIP_ID ......................................................................................................................... 3-8 CHIP_INFO .................................................................................................................... 3-9 GC_TEST ..................................................................................................................... 3-10 GC_PROGID ................................................................................................................ 3-11 LockUnlock ................................................................................................................... 3-12 LockStatus.................................................................................................................... 3-13 IFC_CTRL ................................................................................................................ 3-14 LVD .......................................................................................................................... 3-15 SYSWD_RES ........................................................................................................... 3-16 SYSWD_CTL ........................................................................................................... 3-17 SYSWD_CNT ........................................................................................................... 3-18 SYSWD_WNDW ...................................................................................................... 3-19 SYSWD_STS ........................................................................................................... 3-20 ALVSND_CTL .......................................................................................................... 3-21 ALVSND_MEN ......................................................................................................... 3-22 ALVSND_STS .......................................................................................................... 3-23 CLOCK_SELECTION ............................................................................................... 3-24 CLOCK_DIV ............................................................................................................. 3-26 PLL_CTRL ................................................................................................................ 3-27 PLL_PIXCLOCK ....................................................................................................... 3-28 PLL_CLOCK_DIV ..................................................................................................... 3-29 PWR_CTRL .............................................................................................................. 3-30 DISP_CTL ................................................................................................................ 3-32 DISP0_PN0_CTL ..................................................................................................... 3-34 DISP0_PN1_CTL ..................................................................................................... 3-35 DISP0_PN2_CTL ..................................................................................................... 3-36 DISP0_PN3_CTL ..................................................................................................... 3-37 DISP0_PN4_CTL ..................................................................................................... 3-38 DISP0_PN5_CTL ..................................................................................................... 3-39 DISP0_PN6_CTL ..................................................................................................... 3-40 DISP0_PN7_CTL ..................................................................................................... 3-41 DISP0_PN8_CTL ..................................................................................................... 3-42 DISP0_PN9_CTL ..................................................................................................... 3-43 DISP0_PN10_CTL ................................................................................................... 3-44 DISP0_PN11_CTL ................................................................................................... 3-45 DISP0_PN12_CTL ................................................................................................... 3-46 DISP1_PN0_CTL ..................................................................................................... 3-47 DISP1_PN1_CTL ..................................................................................................... 3-48 DISP1_PN2_CTL ..................................................................................................... 3-49 DISP1_PN3_CTL ..................................................................................................... 3-50 DISP1_PN4_CTL ..................................................................................................... 3-51 DISP1_PN5_CTL ..................................................................................................... 3-52 DISP1_PN6_CTL ..................................................................................................... 3-53 DISP1_PN7_CTL ..................................................................................................... 3-54 DISP1_PN8_CTL ..................................................................................................... 3-55

iv rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



DISP1_PN9_CTL ..................................................................................................... 3-56 DISP1_PN10_CTL ................................................................................................... 3-57 DISP1_PN11_CTL ................................................................................................... 3-58 DISP1_PN12_CTL ................................................................................................... 3-59 TSIG0_3_CTL .......................................................................................................... 3-60 TSIG4_7_CTL .......................................................................................................... 3-62 TSIG8_11_CTL ........................................................................................................ 3-64 DSPINV_CTL ........................................................................................................... 3-66 ADC3_CTL ............................................................................................................... 3-67 ADC2_CTL ............................................................................................................... 3-68 ADC1_CTL ............................................................................................................... 3-69 ADC0_CTL ............................................................................................................... 3-70 SMC_1M_0_CTL ...................................................................................................... 3-71 SMC_1P_0_CTL ...................................................................................................... 3-72 SMC_2M_0_CTL ...................................................................................................... 3-73 SMC_2P_0_CTL ...................................................................................................... 3-74 SMC_1M_1_CTL ...................................................................................................... 3-75 SMC_1P_1_CTL ...................................................................................................... 3-76 SMC_2M_1_CTL ...................................................................................................... 3-77 SMC_2P_1_CTL ...................................................................................................... 3-78 SMC_1M_2_CTL ...................................................................................................... 3-79 SMC_1P_2_CTL ...................................................................................................... 3-80 SMC_2M_2_CTL ...................................................................................................... 3-81 SMC_2P_2_CTL ...................................................................................................... 3-82 SMC_1M_3_CTL ...................................................................................................... 3-83 SMC_1P_3_CTL ...................................................................................................... 3-84 SMC_2M_3_CTL ...................................................................................................... 3-85 SMC_2P_3_CTL ...................................................................................................... 3-86 SMC_1M_4_CTL ...................................................................................................... 3-87 SMC_1P_4_CTL ...................................................................................................... 3-88 SMC_2M_4_CTL ...................................................................................................... 3-89 SMC_2P_4_CTL ...................................................................................................... 3-90 SMC_1M_5_CTL ...................................................................................................... 3-91 SMC_1P_5_CTL ...................................................................................................... 3-92 SMC_2M_5_CTL ...................................................................................................... 3-93 SMC_2P_5_CTL ...................................................................................................... 3-94 CFG5_CTL ............................................................................................................... 3-95 CFG4_CTL ............................................................................................................... 3-96 CFG3_CTL ............................................................................................................... 3-97 CFG2_CTL ............................................................................................................... 3-98 CFG1_CTL ............................................................................................................... 3-99 CFG0_CTL ............................................................................................................. 3-100 DISP1_0_CTL ........................................................................................................ 3-101 DISP1_1_CTL ........................................................................................................ 3-103 DISP1_2_CTL ........................................................................................................ 3-105 DISP1_3_CTL ........................................................................................................ 3-107 DISP1_4_CTL ........................................................................................................ 3-109 DISP1_5_CTL ........................................................................................................ 3-111 DISP1_6_CTL ........................................................................................................ 3-113 DISP1_7_CTL ........................................................................................................ 3-115 DISP1_8_CTL ........................................................................................................ 3-117 DISP1_9_CTL ........................................................................................................ 3-119 DISP1_10_CTL ...................................................................................................... 3-121 DISP1_11_CTL ...................................................................................................... 3-123

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 v



DISP1_12_CTL ...................................................................................................... 3-125 TSIG11_CTL .......................................................................................................... 3-127 TSIG10_CTL .......................................................................................................... 3-128 TSIG9_CTL ............................................................................................................ 3-129 TSIG8_CTL ............................................................................................................ 3-130 TSIG7_CTL ............................................................................................................ 3-131 TSIG6_CTL ............................................................................................................ 3-132 TSIG5_CTL ............................................................................................................ 3-133 TSIG4_CTL ............................................................................................................ 3-134 TSIG3_CTL ............................................................................................................ 3-135 TSIG2_CTL ............................................................................................................ 3-136 TSIG1_CTL ............................................................................................................ 3-137 TSIG0_CTL ............................................................................................................ 3-138 DISP0_0_CTL ........................................................................................................ 3-139 DISP0_1_CTL ........................................................................................................ 3-141 DISP0_2_CTL ........................................................................................................ 3-143 DISP0_3_CTL ........................................................................................................ 3-145 DISP0_4_CTL ........................................................................................................ 3-147 DISP0_5_CTL ........................................................................................................ 3-149 DISP0_6_CTL ........................................................................................................ 3-151 DISP0_7_CTL ........................................................................................................ 3-153 DISP0_8_CTL ........................................................................................................ 3-155 DISP0_9_CTL ........................................................................................................ 3-157 DISP0_10_CTL ...................................................................................................... 3-159 DISP0_11_CTL ...................................................................................................... 3-161 DISP0_12_CTL ...................................................................................................... 3-163 SG_SGO_CTL ....................................................................................................... 3-165 SG_SGA_CTL ........................................................................................................ 3-166 I2C0_SDA_CTL ...................................................................................................... 3-167 I2C0_SCL_CTL ...................................................................................................... 3-168 I2C1_SDA_CTL ...................................................................................................... 3-169 I2C1_SCL_CTL ...................................................................................................... 3-170 ADC9_CTL ............................................................................................................. 3-171 ADC8_CTL ............................................................................................................. 3-172 ADC7_CTL ............................................................................................................. 3-173 ADC6_CTL ............................................................................................................. 3-174 ADC5_CTL ............................................................................................................. 3-175 ADC4_CTL ............................................................................................................. 3-176 MODULE_IRQ_STS ............................................................................................... 3-177 APIX_CLR .............................................................................................................. 3-178 APIX_SET .............................................................................................................. 3-179 APIX_STS .............................................................................................................. 3-180 ASHELL_RH_CLR ................................................................................................. 3-181 ASHELL_RH_SET ................................................................................................. 3-182 ASHELL_RH_STS ................................................................................................. 3-184 E2IP_CLR .............................................................................................................. 3-185 E2IP_SET ............................................................................................................... 3-187 E2IP_STS ............................................................................................................... 3-189 CFF_CTRL_CLR .................................................................................................... 3-191 CFF_CTRL_SET .................................................................................................... 3-192 CFF_CTRL_STS .................................................................................................... 3-193 CFF_FIFO_CLR ..................................................................................................... 3-194 CFF_FIFO_SET ..................................................................................................... 3-197 CFF_FIFO_STS ..................................................................................................... 3-200

vi rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



RLT_STS ................................................................................................................ 3-203 LIN_STS ................................................................................................................. 3-204 PPG_STS ............................................................................................................... 3-205 I2C0_STS ............................................................................................................... 3-206 I2C1_STS ............................................................................................................... 3-207 SGE_CLR ............................................................................................................... 3-208 SGE_SET ............................................................................................................... 3-209 SGE_STS ............................................................................................................... 3-210 ADC_STS ............................................................................................................... 3-211 EIRQ_STS .............................................................................................................. 3-212 ESPI_STS .............................................................................................................. 3-213 IRIS_CLR ............................................................................................................... 3-214 IRIS_SET ............................................................................................................... 3-217 IRIS_STS ............................................................................................................... 3-220 CMDSEQ_CLR ...................................................................................................... 3-223 CMDSEQ_SET ....................................................................................................... 3-224 CMDSEQ_STS ....................................................................................................... 3-225 GC_CLR ................................................................................................................. 3-226 GC_SET ................................................................................................................. 3-227 GC_STS ................................................................................................................. 3-228 DMAC_STS ............................................................................................................ 3-229 FSPI_STS .............................................................................................................. 3-230 PRGCRC_STS ....................................................................................................... 3-231 INTERCONNECT_CLR .......................................................................................... 3-232 INTERCONNECT_SET .......................................................................................... 3-233 INTERCONNECT_STS .......................................................................................... 3-234 IRQ_CMDSEQ_SEL0 ............................................................................................ 3-235 IRQ_CMDSEQ_SEL1 ............................................................................................ 3-258 CFF_TRG_SEL0 .................................................................................................... 3-275 CFF_TRG_SEL1 .................................................................................................... 3-299 HIRQ_CTL .............................................................................................................. 3-323 APIX_HIEN ............................................................................................................. 3-324 ASHELL_RH_HIEN ................................................................................................ 3-326 E2IP_HIEN ............................................................................................................. 3-328 CFF_CTRL_HIEN .................................................................................................. 3-330 CFF_FIFO_HIEN .................................................................................................... 3-331 RLT_HIEN .............................................................................................................. 3-334 LIN_HIEN ............................................................................................................... 3-335 PPG_HIEN ............................................................................................................. 3-336 I2C0_HIEN ............................................................................................................. 3-337 I2C1_HIEN ............................................................................................................. 3-338 SGE_HIEN ............................................................................................................. 3-339 ADC_HIEN ............................................................................................................. 3-340 EIRQ_HIEN ............................................................................................................ 3-341 ESPI_HIEN ............................................................................................................. 3-342 IRIS_HIEN .............................................................................................................. 3-343 CMDSEQ_HIEN ..................................................................................................... 3-346 GC_HIEN ............................................................................................................... 3-347 DMAC_HIEN .......................................................................................................... 3-348 FSPI_HIEN ............................................................................................................. 3-349 PRGCRC_HIEN ..................................................................................................... 3-350 INTERCONNECT_HIEN ........................................................................................ 3-351 PNCSW_CTL ......................................................................................................... 3-352 APIX_PSEN ........................................................................................................... 3-353

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 vii



ASHELL_RH_PSEN ............................................................................................... 3-355 E2IP_PSEN ............................................................................................................ 3-357 CFF_CTRL_PSEN ................................................................................................. 3-359 CFF_FIFO_PSEN .................................................................................................. 3-360 RLT_PSEN ............................................................................................................. 3-363 LIN_PSEN .............................................................................................................. 3-364 PPG_PSEN ............................................................................................................ 3-365 I2C0_PSEN ............................................................................................................ 3-366 I2C1_PSEN ............................................................................................................ 3-367 SGE_PSEN ............................................................................................................ 3-368 ADC_PSEN ............................................................................................................ 3-369 EIRQ_PSEN ........................................................................................................... 3-370 ESPI_PSEN ........................................................................................................... 3-371 IRIS_PSEN ............................................................................................................. 3-372 CMDSEQ_PSEN .................................................................................................... 3-375 GC_PSEN .............................................................................................................. 3-376 DMAC_PSEN ......................................................................................................... 3-377 FSPI_PSEN ............................................................................................................ 3-378 PRGCRC_PSEN .................................................................................................... 3-379 INTERCONNECT_PSEN ....................................................................................... 3-380 DMA_CNTRL ......................................................................................................... 3-381

3.2 APIX2 Registers ..................................................................................................................... 3-3933.2.1 APIX2 PHY Register Overview ...................................................................................... 3-394

PHY_RST_CTRL........................................................................................................ 3-396 PHY_RST_STAT........................................................................................................ 3-397 PHY_PWR_CTRL....................................................................................................... 3-398 PHY_LT_CFG_CTRL ................................................................................................. 3-400 PHY_LT_CFG_CTRL_1 ............................................................................................. 3-401 PHY_LT_CFG_CTRL_2 ............................................................................................. 3-402 PHY_LT_CTRL_1....................................................................................................... 3-403 PHY_LT_CTRL_2....................................................................................................... 3-404 PHY_LT_I_STAT........................................................................................................ 3-405 PHY_LT_P_STAT ...................................................................................................... 3-406 PHY_CDR_CFG......................................................................................................... 3-407 PHY_RX_TST ............................................................................................................ 3-408 PHY_RX_UP .............................................................................................................. 3-409 OBS_RX_2 ................................................................................................................. 3-410 BIST_PATTGEN_LINK............................................................................................... 3-411 BistTestDuration ......................................................................................................... 3-412 BistPrbsCfg................................................................................................................. 3-413 BistChkPrbsCfg .......................................................................................................... 3-414 BistCtrl ........................................................................................................................ 3-415 BistDownStatus .......................................................................................................... 3-416 CLKMEAS_CFG......................................................................................................... 3-417 CLKMEAS_CNT ......................................................................................................... 3-418 MII_CLK_CTRL .......................................................................................................... 3-419 SYS_CLK_CTRL ........................................................................................................ 3-420 PERI_CLK_CTRL....................................................................................................... 3-421 VID_CLK_CTRL ......................................................................................................... 3-422 VIDS_CLK_CTRL....................................................................................................... 3-423

3.2.2 APIX2RX Link Register Overview .................................................................................. 3-424 APIX_CFG_0.............................................................................................................. 3-426 APIX_CFG_1.............................................................................................................. 3-429 APIX_CFG_2.............................................................................................................. 3-431

viii rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



APIX_CFG_3.............................................................................................................. 3-434 APIX_CFG_4.............................................................................................................. 3-438 APIX_CFG_5.............................................................................................................. 3-443 APIX_CFG_6.............................................................................................................. 3-447 APIX_CFG_8.............................................................................................................. 3-449 APIX_PARAM_3......................................................................................................... 3-451 APIX_CFG_VALID ..................................................................................................... 3-452 APIX_CFG_MODE ..................................................................................................... 3-453 APIX_STAT_CTRL_0................................................................................................. 3-454 APIX_STAT_CTRL_1................................................................................................. 3-455 APIX_STAT_TIMEOUT .............................................................................................. 3-456 APIX_STAT_0 ............................................................................................................ 3-457 APIX_STAT_1 ............................................................................................................ 3-458 APIX_STAT_2 ............................................................................................................ 3-461 APIX_STAT_4 ............................................................................................................ 3-463 TST_CFG_0 ............................................................................................................... 3-464 TST_STAT.................................................................................................................. 3-465 DBG_STAT_4............................................................................................................. 3-466 DBG_STAT_5............................................................................................................. 3-467 APIX_REM_CMD_EN ................................................................................................ 3-468 APIX_REM_CMD_REQ.............................................................................................. 3-469 APIX_REM_CMD_STAT ............................................................................................ 3-470 INT_STAT_LINK......................................................................................................... 3-471 INT_STAT_ASHELL................................................................................................... 3-472 INT_STAT_PIX........................................................................................................... 3-474 INT_EN_LINK............................................................................................................. 3-475 INT_EN_ASHELL ....................................................................................................... 3-476 INT_EN_PIX ............................................................................................................... 3-478 INT_SET_LINK........................................................................................................... 3-479 INT_SET_ASHELL ..................................................................................................... 3-480 INT_SET_PIX ............................................................................................................. 3-482

3.2.3 AShell Remote Handler Register Overview ................................................................... 3-483 RH_CTRL ................................................................................................................... 3-484 RH_STAT ................................................................................................................... 3-486 RESET_CTRL ............................................................................................................ 3-487 AHBM_LOCK ............................................................................................................. 3-488 BASE_ADDR_WRITE ................................................................................................ 3-489 BASE_ADDR_READ.................................................................................................. 3-490 BASE_ADDR_EVENT................................................................................................ 3-491 FIFO_THRESH_VAL.................................................................................................. 3-492 FIFO_STAT ................................................................................................................ 3-493 RH_IRQ_EN ............................................................................................................... 3-494 MAILBOX.................................................................................................................... 3-495 PUSH_MODE............................................................................................................. 3-496 PUSH_MSG ............................................................................................................... 3-497 PUSH_INDEX............................................................................................................. 3-498 PUSH_TYPE .............................................................................................................. 3-499 PUSH_TID.................................................................................................................. 3-500 ASHELL_FLUSH ........................................................................................................ 3-501 EVENT_STAT0 .......................................................................................................... 3-502 EVENT_STAT1 .......................................................................................................... 3-503 EVENT_STAT2 .......................................................................................................... 3-504 EVENT_STAT3 .......................................................................................................... 3-505 EVENT_STAT4 .......................................................................................................... 3-506

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 ix



EVENT_STAT5 .......................................................................................................... 3-507 EVENT_STAT6 .......................................................................................................... 3-508 EVENT_STAT7 .......................................................................................................... 3-509 EVENT_EN0............................................................................................................... 3-510 EVENT_EN1............................................................................................................... 3-511 EVENT_EN2............................................................................................................... 3-512 EVENT_EN3............................................................................................................... 3-513 EVENT_EN4............................................................................................................... 3-514 EVENT_EN5............................................................................................................... 3-515 EVENT_EN6............................................................................................................... 3-516 EVENT_EN7............................................................................................................... 3-517 AHB_WRERR_ADDR................................................................................................. 3-518 AHB_RDERR_ADDR ................................................................................................. 3-519 EVENT_MSG_TABLE ................................................................................................ 3-520

3.2.4 APIX2 HDCP Register Overview ................................................................................... 3-521 CFG_HDCP................................................................................................................ 3-522 CTRL_HDCP_0 .......................................................................................................... 3-523 STATUS_HDCP_0 ..................................................................................................... 3-524 STATUS_HDCP_1 ..................................................................................................... 3-525 STATUS_HDCP_2 ..................................................................................................... 3-526 STATUS_HDCP_3 ..................................................................................................... 3-527 STATUS_HDCP_4 ..................................................................................................... 3-528 STATUS_HDCP_5 ..................................................................................................... 3-529 STATUS_HDCP_6 ..................................................................................................... 3-530 STATUS_HDCP_7 ..................................................................................................... 3-531 STATUS_HDCP_8 ..................................................................................................... 3-532 STATUS_HDCP_9 ..................................................................................................... 3-533 STATUS_HDCP_10 ................................................................................................... 3-534 STATUS_HDCP_11 ................................................................................................... 3-535 STATUS_HDCP_12 ................................................................................................... 3-536 STATUS_HDCP_13 ................................................................................................... 3-537 STATUS_HDCP_14 ................................................................................................... 3-538 STATUS_HDCP_15 ................................................................................................... 3-539 INT_STAT_HDCP....................................................................................................... 3-540 INT_EN_HDCP........................................................................................................... 3-541 INT_SET_HDCP......................................................................................................... 3-542

3.2.5 Embedded Ethernet Register Overview ........................................................................ 3-543 LOCK.......................................................................................................................... 3-544 LOCK_STAT............................................................................................................... 3-545 ENABLE ................................................................................................................. 3-546 RESET_CTRL ........................................................................................................ 3-547 CLEAR_CNT .............................................................................................................. 3-548 RX_CNT_0 ................................................................................................................. 3-549 RX_CNT_1 ................................................................................................................. 3-550 RX_CNT_2 ................................................................................................................. 3-551 RX_CNT_3 ................................................................................................................. 3-552 RX_CNT_4 ................................................................................................................. 3-553 TX_CNT_0.................................................................................................................. 3-554 TX_CNT_1.................................................................................................................. 3-555 SW_FLUSH ................................................................................................................ 3-556 HOST0_TRIG_CTRL ............................................................................................. 3-557 HOST0_TRIG_VAL ................................................................................................ 3-558 HOST1_TRIG_CTRL ............................................................................................. 3-559 HOST1_TRIG_VAL ................................................................................................ 3-560

x rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



IRQ_EN ...................................................................................................................... 3-561 COMMON_CTRL ................................................................................................... 3-562 TX_RX_TARGETID ................................................................................................ 3-563 TX_CFG ................................................................................................................. 3-564 CLIENT_MAC_LO .................................................................................................. 3-565 CLIENT_MAC_HI ................................................................................................... 3-566 CLIENT_MAC_VLAN ............................................................................................. 3-567 CLIENT_IP ............................................................................................................. 3-568 CLIENT_UDP_PORT ............................................................................................. 3-569 CLIENT_RPC_MSGID ........................................................................................... 3-570 CLIENT_RPC_ID ................................................................................................... 3-571 CLIENT_RPC_MISC .............................................................................................. 3-572 HOST_MAC_VLD....................................................................................................... 3-573 HOST0_MAC_LO ................................................................................................... 3-574 HOST0_MAC_HI .................................................................................................... 3-575 HOST0_IP .............................................................................................................. 3-576 HOST0_IP_TTL ...................................................................................................... 3-577 HOST0_UDP .......................................................................................................... 3-578 HOST0_RPC_MSGID ............................................................................................ 3-579 HOST0_RPC_ID .................................................................................................... 3-580 HOST0_RPC_MISC ............................................................................................... 3-581 HOST1_MAC_LO ................................................................................................... 3-582 HOST1_MAC_HI .................................................................................................... 3-583 HOST1_IP .............................................................................................................. 3-584 HOST1_IP_TTL ...................................................................................................... 3-585 HOST1_UDP .......................................................................................................... 3-586 HOST1_RPC_MSGID ............................................................................................ 3-587 HOST1_RPC_ID .................................................................................................... 3-588 HOST1_RPC_MISC ............................................................................................... 3-589

3.3 HS_SPI Interface Registers ................................................................................................... 3-5903.3.1 High-speed SPI Interface Register Overview ................................................................ 3-591

MCTRL ....................................................................................................................... 3-594 PCC0 .......................................................................................................................... 3-596 PCC1 .......................................................................................................................... 3-600 PCC2 .......................................................................................................................... 3-604 PCC3 .......................................................................................................................... 3-608 TXF............................................................................................................................. 3-612 TXE............................................................................................................................. 3-614 TXC ............................................................................................................................ 3-617 RXF ............................................................................................................................ 3-619 RXE ............................................................................................................................ 3-621 RXC ............................................................................................................................ 3-623 FAULTF ...................................................................................................................... 3-625 FAULTC...................................................................................................................... 3-627 DMCFG ......................................................................................................................3-628 DMDMAEN ................................................................................................................. 3-629 SVCFG0 ..................................................................................................................... 3-630 SVCFG1 ..................................................................................................................... 3-631 DMSTART .................................................................................................................. 3-632 DMSTOP .................................................................................................................... 3-633 DMPSEL.....................................................................................................................3-634 DMTRP....................................................................................................................... 3-635 DMBCC ......................................................................................................................3-636 DMBCS....................................................................................................................... 3-637

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 xi



DMSTATUS................................................................................................................ 3-638 TXBITCNT .................................................................................................................. 3-639 RXBITCNT.................................................................................................................. 3-640 RXSHIFT .................................................................................................................... 3-641 FIFOCFG.................................................................................................................... 3-642 TXFIFO0..................................................................................................................... 3-644 TXFIFO1..................................................................................................................... 3-645 TXFIFO2..................................................................................................................... 3-646 TXFIFO3..................................................................................................................... 3-647 TXFIFO4..................................................................................................................... 3-648 TXFIFO5..................................................................................................................... 3-649 TXFIFO6..................................................................................................................... 3-650 TXFIFO7..................................................................................................................... 3-651 TXFIFO8..................................................................................................................... 3-652 TXFIFO9..................................................................................................................... 3-653 TXFIFO10................................................................................................................... 3-654 TXFIFO11................................................................................................................... 3-655 TXFIFO12................................................................................................................... 3-656 TXFIFO13................................................................................................................... 3-657 TXFIFO14................................................................................................................... 3-658 TXFIFO15................................................................................................................... 3-659 RXFIFO0 .................................................................................................................... 3-660 RXFIFO1 .................................................................................................................... 3-661 RXFIFO2 .................................................................................................................... 3-662 RXFIFO3 .................................................................................................................... 3-663 RXFIFO4 .................................................................................................................... 3-664 RXFIFO5 .................................................................................................................... 3-665 RXFIFO6 .................................................................................................................... 3-666 RXFIFO7 .................................................................................................................... 3-667 RXFIFO8 .................................................................................................................... 3-668 RXFIFO9 .................................................................................................................... 3-669 RXFIFO10 .................................................................................................................. 3-670 RXFIFO11 .................................................................................................................. 3-671 RXFIFO12 .................................................................................................................. 3-672 RXFIFO13 .................................................................................................................. 3-673 RXFIFO14 .................................................................................................................. 3-674 RXFIFO15 .................................................................................................................. 3-675 CSCFG ....................................................................................................................... 3-676 CSITIME ..................................................................................................................... 3-678 CSAEXT ..................................................................................................................... 3-679 RDCSDC0 .................................................................................................................. 3-680 RDCSDC1 .................................................................................................................. 3-682 RDCSDC2 .................................................................................................................. 3-684 RDCSDC3 .................................................................................................................. 3-686 RDCSDC4 .................................................................................................................. 3-688 RDCSDC5 .................................................................................................................. 3-690 RDCSDC6 .................................................................................................................. 3-692 RDCSDC7 .................................................................................................................. 3-694 WRCSDC0 ................................................................................................................. 3-696 WRCSDC1 ................................................................................................................. 3-698 WRCSDC2 ................................................................................................................. 3-700 WRCSDC3 ................................................................................................................. 3-702 WRCSDC4 ................................................................................................................. 3-704 WRCSDC5 ................................................................................................................. 3-706

xii rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



WRCSDC6 ................................................................................................................. 3-708 WRCSDC7 ................................................................................................................. 3-710 MID ............................................................................................................................. 3-712

3.4 Programmable CRC Registers .............................................................................................. 3-7133.4.1 Programmable CRC Register Overview ........................................................................ 3-714

PRGCRCn_CRCPOLY............................................................................................... 3-716 PRGCRCn_CRCSEED............................................................................................... 3-717 PRGCRCn_CRCFXOR .............................................................................................. 3-718 PRGCRCn_CRCCFG................................................................................................. 3-719 PRGCRCn_CRCWR .................................................................................................. 3-722 PRGCRCn_CRCRD ................................................................................................... 3-723

3.5 DMAC Registers .................................................................................................................... 3-7243.5.1 DMAC Register Overview .............................................................................................. 3-725

DMAi_A0 .................................................................................................................... 3-727 DMAi_B0 .................................................................................................................... 3-731 DMAi_SA0 .................................................................................................................. 3-735 DMAi_DA0.................................................................................................................. 3-736 DMAi_C0 .................................................................................................................... 3-737 DMAi_D0 .................................................................................................................... 3-738 DMAi_SASHDW0 ....................................................................................................... 3-741 DMAi_DASHDW0....................................................................................................... 3-742 DMAi_A1 .................................................................................................................... 3-743 DMAi_B1 .................................................................................................................... 3-747 DMAi_SA1 .................................................................................................................. 3-751 DMAi_DA1.................................................................................................................. 3-752 DMAi_C1 .................................................................................................................... 3-753 DMAi_D1 .................................................................................................................... 3-754 DMAi_SASHDW1 ....................................................................................................... 3-757 DMAi_DASHDW1....................................................................................................... 3-758 DMAi_R ...................................................................................................................... 3-759 DMAi_DIRQ1.............................................................................................................. 3-761 DMAi_DIRQ2.............................................................................................................. 3-762 DMAi_EDIRQ1 ........................................................................................................... 3-763 DMAi_EDIRQ2 ........................................................................................................... 3-764 DMAi_ID ..................................................................................................................... 3-765 DMAi_CMICIC0 .......................................................................................................... 3-766 DMAi_CMICIC1 .......................................................................................................... 3-767 DMAi_CMICIC2 .......................................................................................................... 3-768 DMAi_CMICIC3 .......................................................................................................... 3-769 DMAi_CMICIC4 .......................................................................................................... 3-770 DMAi_CMICIC5 .......................................................................................................... 3-771 DMAi_CMICIC6 .......................................................................................................... 3-772 DMAi_CMICIC7 .......................................................................................................... 3-773 DMAi_CMICIC8 .......................................................................................................... 3-774 DMAi_CMICIC9 .......................................................................................................... 3-775 DMAi_CMICIC10 ........................................................................................................ 3-776 DMAi_CMICIC11 ........................................................................................................ 3-777 DMAi_CMICIC12 ........................................................................................................ 3-778 DMAi_CMICIC13 ........................................................................................................ 3-779 DMAi_CMICIC14 ........................................................................................................ 3-780 DMAi_CMICIC15 ........................................................................................................ 3-781 DMAi_CMICIC16 ........................................................................................................ 3-782 DMAi_CMICIC17 ........................................................................................................ 3-783 DMAi_CMICIC18 ........................................................................................................ 3-784

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 xiii



DMAi_CMICIC19 ........................................................................................................ 3-785 DMAi_CMICIC20 ........................................................................................................ 3-786 DMAi_CMICIC21 ........................................................................................................ 3-787 DMAi_CMCHIC0......................................................................................................... 3-788 DMAi_CMCHIC1......................................................................................................... 3-789

3.6 Command Sequencer Registers ............................................................................................ 3-7903.6.1 Command Sequencer Register Overview ..................................................................... 3-791

FIFOBuffer .................................................................................................................. 3-792 FIFOStatus ................................................................................................................. 3-793 FIFOControl ................................................................................................................ 3-794 FIFOWatermarkControl .............................................................................................. 3-795 Status ......................................................................................................................... 3-796 Control ........................................................................................................................ 3-797

3.7 Internal Flash Memory Registers ........................................................................................... 3-7983.7.1 Internal Flash Control Register Overview ...................................................................... 3-799

TCFCFG_FCPROTKEY ............................................................................................. 3-800 TCFCFG_FCFGR .................................................................................................. 3-801 TCFCFG_FECCCTRL ............................................................................................ 3-802 TCFCFG_FICTRL0..................................................................................................... 3-803 TCFCFG_FSTAT0...................................................................................................... 3-804 TCFCFG_FSECIR...................................................................................................... 3-806 TCFCFG_FECCEAR.................................................................................................. 3-807

3.8 ConfigFIFO Registers ............................................................................................................ 3-8083.8.1 Configuration FIFO Register Overview .......................................................................... 3-809

FFISTS ....................................................................................................................... 3-819 FFIEN ......................................................................................................................... 3-823 CFG_IDLE .................................................................................................................. 3-825 CHPriority ................................................................................................................... 3-826 SW_RT0 .....................................................................................................................3-827 FFCfg0........................................................................................................................ 3-828 FFB0........................................................................................................................... 3-829 FFT0 ........................................................................................................................... 3-830 DestAddress0 ............................................................................................................. 3-831 AdrCfg0 ...................................................................................................................... 3-832 TransferCfg0............................................................................................................... 3-833 FFStatus0 ................................................................................................................... 3-835 FFISTS_TH0 .............................................................................................................. 3-836 FFIEN_TH0 ................................................................................................................ 3-837 FFIEN_DW0 ............................................................................................................... 3-838 READ_CNT0 .............................................................................................................. 3-839 WRITE_CNT0............................................................................................................. 3-840 INT_READ_ADDR0.................................................................................................... 3-841 INT_WRITE_ADDR0 .................................................................................................. 3-842 FFEDataInL0 .............................................................................................................. 3-843 FFEDataInU0.............................................................................................................. 3-844 FFDataInL0................................................................................................................. 3-845 FFDataInU0 ................................................................................................................ 3-846 FFDataSize0............................................................................................................... 3-847 MetaDestAddress0 ..................................................................................................... 3-848 MetaCfg0 .................................................................................................................... 3-849 SW_RT1 .....................................................................................................................3-851 FFCfg1........................................................................................................................ 3-852 FFB1........................................................................................................................... 3-853 FFT1 ........................................................................................................................... 3-854

xiv rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



DestAddress1 ............................................................................................................. 3-855 AdrCfg1 ...................................................................................................................... 3-856 TransferCfg1............................................................................................................... 3-857 FFStatus1 ................................................................................................................... 3-859 FFISTS_TH1 .............................................................................................................. 3-860 FFIEN_TH1 ................................................................................................................ 3-861 FFIEN_DW1 ............................................................................................................... 3-862 READ_CNT1 .............................................................................................................. 3-863 WRITE_CNT1............................................................................................................. 3-864 INT_READ_ADDR1.................................................................................................... 3-865 INT_WRITE_ADDR1 .................................................................................................. 3-866 FFEDataInL1 .............................................................................................................. 3-867 FFEDataInU1.............................................................................................................. 3-868 FFDataInL1................................................................................................................. 3-869 FFDataInU1 ................................................................................................................ 3-870 FFDataSize1............................................................................................................... 3-871 MetaDestAddress1 ..................................................................................................... 3-872 MetaCfg1 .................................................................................................................... 3-873 SW_RT2 .....................................................................................................................3-875 FFCfg2........................................................................................................................ 3-876 FFB2........................................................................................................................... 3-877 FFT2 ........................................................................................................................... 3-878 DestAddress2 ............................................................................................................. 3-879 AdrCfg2 ...................................................................................................................... 3-880 TransferCfg2............................................................................................................... 3-881 FFStatus2 ................................................................................................................... 3-883 FFISTS_TH2 .............................................................................................................. 3-884 FFIEN_TH2 ................................................................................................................ 3-885 FFIEN_DW2 ............................................................................................................... 3-886 READ_CNT2 .............................................................................................................. 3-887 WRITE_CNT2............................................................................................................. 3-888 INT_READ_ADDR2.................................................................................................... 3-889 INT_WRITE_ADDR2 .................................................................................................. 3-890 FFEDataInL2 .............................................................................................................. 3-891 FFEDataInU2.............................................................................................................. 3-892 FFDataInL2................................................................................................................. 3-893 FFDataInU2 ................................................................................................................ 3-894 FFDataSize2............................................................................................................... 3-895 MetaDestAddress2 ..................................................................................................... 3-896 MetaCfg2 .................................................................................................................... 3-897 SW_RT3 .....................................................................................................................3-899 FFCfg3........................................................................................................................ 3-900 FFB3........................................................................................................................... 3-901 FFT3 ........................................................................................................................... 3-902 DestAddress3 ............................................................................................................. 3-903 AdrCfg3 ...................................................................................................................... 3-904 TransferCfg3............................................................................................................... 3-905 FFStatus3 ................................................................................................................... 3-907 FFISTS_TH3 .............................................................................................................. 3-908 FFIEN_TH3 ................................................................................................................ 3-909 FFIEN_DW3 ............................................................................................................... 3-910 READ_CNT3 .............................................................................................................. 3-911 WRITE_CNT3............................................................................................................. 3-912 INT_READ_ADDR3.................................................................................................... 3-913

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 xv



INT_WRITE_ADDR3 .................................................................................................. 3-914 FFEDataInL3 .............................................................................................................. 3-915 FFEDataInU3.............................................................................................................. 3-916 FFDataInL3................................................................................................................. 3-917 FFDataInU3 ................................................................................................................ 3-918 FFDataSize3............................................................................................................... 3-919 MetaDestAddress3 ..................................................................................................... 3-920 MetaCfg3 .................................................................................................................... 3-921 SW_RT4 .....................................................................................................................3-923 FFCfg4........................................................................................................................ 3-924 FFB4........................................................................................................................... 3-925 FFT4 ........................................................................................................................... 3-926 DestAddress4 ............................................................................................................. 3-927 AdrCfg4 ...................................................................................................................... 3-928 TransferCfg4............................................................................................................... 3-929 FFStatus4 ................................................................................................................... 3-931 FFISTS_TH4 .............................................................................................................. 3-932 FFIEN_TH4 ................................................................................................................ 3-933 FFIEN_DW4 ............................................................................................................... 3-934 READ_CNT4 .............................................................................................................. 3-935 WRITE_CNT4............................................................................................................. 3-936 INT_READ_ADDR4.................................................................................................... 3-937 INT_WRITE_ADDR4 .................................................................................................. 3-938 FFEDataInL4 .............................................................................................................. 3-939 FFEDataInU4.............................................................................................................. 3-940 FFDataInL4................................................................................................................. 3-941 FFDataInU4 ................................................................................................................ 3-942 FFDataSize4............................................................................................................... 3-943 MetaDestAddress4 ..................................................................................................... 3-944 MetaCfg4 .................................................................................................................... 3-945 SW_RT5 .....................................................................................................................3-947 FFCfg5........................................................................................................................ 3-948 FFB5........................................................................................................................... 3-949 FFT5 ........................................................................................................................... 3-950 DestAddress5 ............................................................................................................. 3-951 AdrCfg5 ...................................................................................................................... 3-952 TransferCfg5............................................................................................................... 3-953 FFStatus5 ................................................................................................................... 3-955 FFISTS_TH5 .............................................................................................................. 3-956 FFIEN_TH5 ................................................................................................................ 3-957 FFIEN_DW5 ............................................................................................................... 3-958 READ_CNT5 .............................................................................................................. 3-959 WRITE_CNT5............................................................................................................. 3-960 INT_READ_ADDR5.................................................................................................... 3-961 INT_WRITE_ADDR5 .................................................................................................. 3-962 FFEDataInL5 .............................................................................................................. 3-963 FFEDataInU5.............................................................................................................. 3-964 FFDataInL5................................................................................................................. 3-965 FFDataInU5 ................................................................................................................ 3-966 FFDataSize5............................................................................................................... 3-967 MetaDestAddress5 ..................................................................................................... 3-968 MetaCfg5 .................................................................................................................... 3-969 SW_RT6 .....................................................................................................................3-971 FFCfg6........................................................................................................................ 3-972

xvi rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



FFB6........................................................................................................................... 3-973 FFT6 ........................................................................................................................... 3-974 DestAddress6 ............................................................................................................. 3-975 AdrCfg6 ...................................................................................................................... 3-976 TransferCfg6............................................................................................................... 3-977 FFStatus6 ................................................................................................................... 3-979 FFISTS_TH6 .............................................................................................................. 3-980 FFIEN_TH6 ................................................................................................................ 3-981 FFIEN_DW6 ............................................................................................................... 3-982 READ_CNT6 .............................................................................................................. 3-983 WRITE_CNT6............................................................................................................. 3-984 INT_READ_ADDR6.................................................................................................... 3-985 INT_WRITE_ADDR6 .................................................................................................. 3-986 FFEDataInL6 .............................................................................................................. 3-987 FFEDataInU6.............................................................................................................. 3-988 FFDataInL6................................................................................................................. 3-989 FFDataInU6 ................................................................................................................ 3-990 FFDataSize6............................................................................................................... 3-991 MetaDestAddress6 ..................................................................................................... 3-992 MetaCfg6 .................................................................................................................... 3-993 SW_RT7 .....................................................................................................................3-995 FFCfg7........................................................................................................................ 3-996 FFB7........................................................................................................................... 3-997 FFT7 ........................................................................................................................... 3-998 DestAddress7 ............................................................................................................. 3-999 AdrCfg7 ....................................................................................................................3-1000 TransferCfg7............................................................................................................. 3-1001 FFStatus7 ................................................................................................................. 3-1003 FFISTS_TH7 ............................................................................................................ 3-1004 FFIEN_TH7 .............................................................................................................. 3-1005 FFIEN_DW7 ............................................................................................................. 3-1006 READ_CNT7 ............................................................................................................ 3-1007 WRITE_CNT7........................................................................................................... 3-1008 INT_READ_ADDR7.................................................................................................. 3-1009 INT_WRITE_ADDR7 ................................................................................................ 3-1010 FFEDataInL7 ............................................................................................................ 3-1011 FFEDataInU7............................................................................................................ 3-1012 FFDataInL7............................................................................................................... 3-1013 FFDataInU7 .............................................................................................................. 3-1014 FFDataSize7............................................................................................................. 3-1015 MetaDestAddress7 ................................................................................................... 3-1016 MetaCfg7 .................................................................................................................. 3-1017

3.9 Iris MVL Registers ................................................................................................................ 3-10193.9.1 Iris-MVL Register Overview ......................................................................................... 3-1020

LockUnlock ............................................................................................................... 3-1033 LockStatus................................................................................................................ 3-1034 IPIdentifier ............................................................................................................ 3-1035 InterruptEnable ......................................................................................................... 3-1036 InterruptPreset .......................................................................................................... 3-1037 InterruptClear............................................................................................................ 3-1038 InterruptStatus .......................................................................................................... 3-1039 fetch0_cfg .................................................................................................................3-1040 fetch1_cfg .................................................................................................................3-1041 extsrc0_cfg ............................................................................................................... 3-1042

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 xvii



extdst0_cfg ............................................................................................................... 3-1043 extdst1_cfg ............................................................................................................... 3-1044 clut0_cfg ................................................................................................................... 3-1045 layerblend0_cfg ........................................................................................................ 3-1046 layerblend1_cfg ........................................................................................................ 3-1048 Request_Sequence_Complete................................................................................. 3-1050 Synchronization_Mode ............................................................................................. 3-1051 Synchronization_Status............................................................................................ 3-1052 Synchronization_Trigger........................................................................................... 3-1053 extdst0_clk................................................................................................................3-1054 extdst1_clk................................................................................................................3-1055 PolarityCtrl ................................................................................................................ 3-1056 SigSrcSelect ............................................................................................................. 3-1057 SigPanicColor ........................................................................................................... 3-1058 ClockCtrl ................................................................................................................... 3-1059 StaticControl ............................................................................................................. 3-1060 BurstBufferManagement........................................................................................... 3-1061 BaseAddress ............................................................................................................ 3-1062 SourceBufferStride ................................................................................................... 3-1063 SourceBufferAttributes ............................................................................................. 3-1064 SourceBufferLength.................................................................................................. 3-1065 FrameXOffset ........................................................................................................... 3-1066 FrameYOffset ........................................................................................................... 3-1067 FrameDimensions..................................................................................................... 3-1068 DeltaXX ....................................................................................................................3-1069 DeltaYY ....................................................................................................................3-1070 SkipWindowOffset .................................................................................................... 3-1071 SkipWindowDimensions ........................................................................................... 3-1072 ColorComponentBits ................................................................................................ 3-1073 ColorComponentShift ............................................................................................... 3-1074 ConstantColor........................................................................................................... 3-1075 TransparentColor...................................................................................................... 3-1076 Control ...................................................................................................................... 3-1077 ControlTrigger........................................................................................................... 3-1080 Start .......................................................................................................................... 3-1081 FetchType................................................................................................................. 3-1082 BurstBufferProperties ............................................................................................... 3-1083 StaticControl ............................................................................................................. 3-1084 BitsPerPixel .............................................................................................................. 3-1085 ColorComponentBits ................................................................................................ 3-1086 ColorComponentShift ............................................................................................... 3-1087 Sprite00Address ....................................................................................................... 3-1088 Sprite00Dimension ................................................................................................... 3-1089 Sprite01Address ....................................................................................................... 3-1090 Sprite01Dimension ................................................................................................... 3-1091 Sprite02Address ....................................................................................................... 3-1092 Sprite02Dimension ................................................................................................... 3-1093 Sprite03Address ....................................................................................................... 3-1094 Sprite03Dimension ................................................................................................... 3-1095 Sprite04Address ....................................................................................................... 3-1096 Sprite04Dimension ................................................................................................... 3-1097 Sprite05Address ....................................................................................................... 3-1098 Sprite05Dimension ................................................................................................... 3-1099 Sprite06Address ....................................................................................................... 3-1100

xviii rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



Sprite06Dimension ................................................................................................... 3-1101 Sprite07Address ....................................................................................................... 3-1102 Sprite07Dimension ................................................................................................... 3-1103 Sprite08Address ....................................................................................................... 3-1104 Sprite08Dimension ................................................................................................... 3-1105 Sprite09Address ....................................................................................................... 3-1106 Sprite09Dimension ................................................................................................... 3-1107 Sprite10Address ....................................................................................................... 3-1108 Sprite10Dimension ................................................................................................... 3-1109 Sprite11Address ....................................................................................................... 3-1110 Sprite11Dimension ................................................................................................... 3-1111 Sprite12Address ....................................................................................................... 3-1112 Sprite12Dimension ................................................................................................... 3-1113 Sprite13Address ....................................................................................................... 3-1114 Sprite13Dimension ................................................................................................... 3-1115 Sprite14Address ....................................................................................................... 3-1116 Sprite14Dimension ................................................................................................... 3-1117 Sprite15Address ....................................................................................................... 3-1118 Sprite15Dimension ................................................................................................... 3-1119 BurstBufferManagement........................................................................................... 3-1120 SpriteEnable ............................................................................................................. 3-1121 Sprite00Offset........................................................................................................... 3-1122 Sprite01Offset........................................................................................................... 3-1123 Sprite02Offset........................................................................................................... 3-1124 Sprite03Offset........................................................................................................... 3-1125 Sprite04Offset........................................................................................................... 3-1126 Sprite05Offset........................................................................................................... 3-1127 Sprite06Offset........................................................................................................... 3-1128 Sprite07Offset........................................................................................................... 3-1129 Sprite08Offset........................................................................................................... 3-1130 Sprite09Offset........................................................................................................... 3-1131 Sprite10Offset........................................................................................................... 3-1132 Sprite11Offset........................................................................................................... 3-1133 Sprite12Offset........................................................................................................... 3-1134 Sprite13Offset........................................................................................................... 3-1135 Sprite14Offset........................................................................................................... 3-1136 Sprite15Offset........................................................................................................... 3-1137 FrameDimensions..................................................................................................... 3-1138 ConstantColor........................................................................................................... 3-1139 TransparentColor...................................................................................................... 3-1140 Control ...................................................................................................................... 3-1141 ControlTrigger........................................................................................................... 3-1142 Start .......................................................................................................................... 3-1143 FetchType................................................................................................................. 3-1144 BurstBufferProperties ............................................................................................... 3-1145 StaticControl ............................................................................................................. 3-1146 ClipWindowOffset ..................................................................................................... 3-1147 ClipWindowDimension.............................................................................................. 3-1148 ColorComponentBits ................................................................................................ 3-1149 ColorComponentShift ............................................................................................... 3-1150 ConstantColorRedGreen .......................................................................................... 3-1151 ConstantColorBlueAlpha .......................................................................................... 3-1152 TransparentColor...................................................................................................... 3-1153 Control ...................................................................................................................... 3-1154

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 xix



ControlTrigger........................................................................................................... 3-1155 Start .......................................................................................................................... 3-1156 StaticControl ............................................................................................................. 3-1157 UnshadowedControl ................................................................................................. 3-1158 Control ...................................................................................................................... 3-1159 Status ....................................................................................................................... 3-1160 LastControlWord....................................................................................................... 3-1161 LUT........................................................................................................................... 3-1162 StaticControl ............................................................................................................. 3-1163 Control ...................................................................................................................... 3-1164 Red0 ......................................................................................................................... 3-1165 Red1 ......................................................................................................................... 3-1166 Green0...................................................................................................................... 3-1167 Green1...................................................................................................................... 3-1168 Blue0 ........................................................................................................................ 3-1169 Blue1 ........................................................................................................................ 3-1170 LastControlWord....................................................................................................... 3-1171 StaticControl ............................................................................................................. 3-1172 Control ...................................................................................................................... 3-1173 Position..................................................................................................................... 3-1177 PrimControlWord ...................................................................................................... 3-1178 SecControlWord ....................................................................................................... 3-1179 StaticControl ............................................................................................................. 3-1180 SoftwareKick............................................................................................................. 3-1181 Status ....................................................................................................................... 3-1182 ControlWord ............................................................................................................. 3-1183 CurPixelCnt .............................................................................................................. 3-1184 LastPixelCnt ............................................................................................................. 3-1185 PerfCounter .............................................................................................................. 3-1186 Ctr ............................................................................................................................. 3-1187 Spr ............................................................................................................................ 3-1188 Fdr ............................................................................................................................ 3-1189 Kcr ............................................................................................................................ 3-1190 Scr ............................................................................................................................ 3-1191 Sts ............................................................................................................................ 3-1192 StsClr ........................................................................................................................ 3-1193 FRCnt ....................................................................................................................... 3-1194 LockUnlock ............................................................................................................... 3-1195 LockStatus................................................................................................................ 3-1196 FgStCtrl .................................................................................................................... 3-1197 HtCfg1 ...................................................................................................................... 3-1198 HtCfg2 ...................................................................................................................... 3-1199 VtCfg1....................................................................................................................... 3-1200 VtCfg2....................................................................................................................... 3-1201 Int0Config .................................................................................................................3-1202 Int1Config .................................................................................................................3-1203 Int2Config .................................................................................................................3-1204 Int3Config .................................................................................................................3-1205 PKickConfig .............................................................................................................. 3-1206 SKickConfig .............................................................................................................. 3-1207 SecStatConfig........................................................................................................... 3-1208 FgSRCR1 ................................................................................................................. 3-1209 FgSRCR2 ................................................................................................................. 3-1211 FgSRCR3 ................................................................................................................. 3-1212

xx rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



FgSRCR4 ................................................................................................................. 3-1213 FgSRCR5 ................................................................................................................. 3-1214 FgSRCR6 ................................................................................................................. 3-1215 FgKSDR ................................................................................................................... 3-1216 PaCfg........................................................................................................................ 3-1217 SaCfg........................................................................................................................ 3-1218 FgInCtrl ..................................................................................................................... 3-1219 FgInCtrlPanic ........................................................................................................ 3-1220 FgCCR...................................................................................................................... 3-1221 FgEnable .................................................................................................................. 3-1222 FgSlr ......................................................................................................................... 3-1223 FgEnSts....................................................................................................................3-1224 FgChStat .................................................................................................................. 3-1225 FgChStatClr .............................................................................................................. 3-1226 FgSkewMon.............................................................................................................. 3-1227 FgSFifoMin ............................................................................................................... 3-1228 FgSFifoMax .............................................................................................................. 3-1229 FgSFifoFillClr ............................................................................................................ 3-1230 FgSrEpD................................................................................................................... 3-1231 FgSrFtD ....................................................................................................................3-1232 Control ...................................................................................................................... 3-1233 DitherControl ............................................................................................................ 3-1234 Release ....................................................................................................................3-1236 SSqCnts ................................................................................................................... 3-1237 SSqCycle.................................................................................................................. 3-1238 SWreset ....................................................................................................................3-1239 TCON_CTRL ............................................................................................................ 3-1240 RSDSInvCtrl ............................................................................................................. 3-1243 MapBit3_0 ................................................................................................................ 3-1244 MapBit7_4 ................................................................................................................ 3-1245 MapBit11_8 .............................................................................................................. 3-1246 MapBit15_12 ............................................................................................................ 3-1247 MapBit19_16 ............................................................................................................ 3-1248 MapBit23_20 ............................................................................................................ 3-1249 MapBit27_24 ............................................................................................................ 3-1250 MapBit3_0_Dual ....................................................................................................... 3-1251 MapBit7_4_Dual ....................................................................................................... 3-1252 MapBit11_8_Dual ..................................................................................................... 3-1253 MapBit15_12_Dual ................................................................................................... 3-1254 MapBit19_16_Dual ................................................................................................... 3-1255 MapBit23_20_Dual ................................................................................................... 3-1256 MapBit27_24_Dual ................................................................................................... 3-1257 SPG0PosOn ............................................................................................................. 3-1258 SPG0MaskOn........................................................................................................... 3-1259 SPG0PosOff ............................................................................................................. 3-1260 SPG0MaskOff........................................................................................................... 3-1261 SPG1PosOn ............................................................................................................. 3-1262 SPG1MaskOn........................................................................................................... 3-1263 SPG1PosOff ............................................................................................................. 3-1264 SPG1MaskOff........................................................................................................... 3-1265 SPG2PosOn ............................................................................................................. 3-1266 SPG2MaskOn........................................................................................................... 3-1267 SPG2PosOff ............................................................................................................. 3-1268 SPG2MaskOff........................................................................................................... 3-1269

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 xxi



SPG3PosOn ............................................................................................................. 3-1270 SPG3MaskOn........................................................................................................... 3-1271 SPG3PosOff ............................................................................................................. 3-1272 SPG3MaskOff........................................................................................................... 3-1273 SPG4PosOn ............................................................................................................. 3-1274 SPG4MaskOn........................................................................................................... 3-1275 SPG4PosOff ............................................................................................................. 3-1276 SPG4MaskOff........................................................................................................... 3-1277 SPG5PosOn ............................................................................................................. 3-1278 SPG5MaskOn........................................................................................................... 3-1279 SPG5PosOff ............................................................................................................. 3-1280 SPG5MaskOff........................................................................................................... 3-1281 SPG6PosOn ............................................................................................................. 3-1282 SPG6MaskOn........................................................................................................... 3-1283 SPG6PosOff ............................................................................................................. 3-1284 SPG6MaskOff........................................................................................................... 3-1285 SPG7PosOn ............................................................................................................. 3-1286 SPG7MaskOn........................................................................................................... 3-1287 SPG7PosOff ............................................................................................................. 3-1288 SPG7MaskOff........................................................................................................... 3-1289 SPG8PosOn ............................................................................................................. 3-1290 SPG8MaskOn........................................................................................................... 3-1291 SPG8PosOff ............................................................................................................. 3-1292 SPG8MaskOff........................................................................................................... 3-1293 SPG9PosOn ............................................................................................................. 3-1294 SPG9MaskOn........................................................................................................... 3-1295 SPG9PosOff ............................................................................................................. 3-1296 SPG9MaskOff........................................................................................................... 3-1297 SPG10PosOn ........................................................................................................... 3-1298 SPG10MaskOn......................................................................................................... 3-1299 SPG10PosOff ........................................................................................................... 3-1300 SPG10MaskOff......................................................................................................... 3-1301 SPG11PosOn ........................................................................................................... 3-1302 SPG11MaskOn......................................................................................................... 3-1303 SPG11PosOff ........................................................................................................... 3-1304 SPG11MaskOff......................................................................................................... 3-1305 SMx0Sigs ................................................................................................................. 3-1306 SMx0FctTable .......................................................................................................... 3-1307 SMx1Sigs ................................................................................................................. 3-1308 SMx1FctTable .......................................................................................................... 3-1309 SMx2Sigs ................................................................................................................. 3-1310 SMx2FctTable .......................................................................................................... 3-1311 SMx3Sigs ................................................................................................................. 3-1312 SMx3FctTable .......................................................................................................... 3-1313 SMx4Sigs ................................................................................................................. 3-1314 SMx4FctTable .......................................................................................................... 3-1315 SMx5Sigs ................................................................................................................. 3-1316 SMx5FctTable .......................................................................................................... 3-1317 SMx6Sigs ................................................................................................................. 3-1318 SMx6FctTable .......................................................................................................... 3-1319 SMx7Sigs ................................................................................................................. 3-1320 SMx7FctTable .......................................................................................................... 3-1321 SMx8Sigs ................................................................................................................. 3-1322 SMx8FctTable .......................................................................................................... 3-1323

xxii rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



SMx9Sigs ................................................................................................................. 3-1324 SMx9FctTable .......................................................................................................... 3-1325 SMx10Sigs ............................................................................................................... 3-1326 SMx10FctTable ........................................................................................................ 3-1327 SMx11Sigs ............................................................................................................... 3-1328 SMx11FctTable ........................................................................................................ 3-1329 SigLockUnlock.......................................................................................................... 3-1330 SigLockStatus........................................................................................................... 3-1331 SigEnable ............................................................................................................. 3-1332 StaticControl ......................................................................................................... 3-1333 ThrSumRed .......................................................................................................... 3-1335 ThrSumGreen ....................................................................................................... 3-1336 ThrSumBlue ......................................................................................................... 3-1337 ErrorThreshold ..................................................................................................... 3-1338 EvalUpperLeft ....................................................................................................... 3-1339 EvalLowerRight .................................................................................................... 3-1340 SkipUpperLeft ....................................................................................................... 3-1341 SkipLowerRight .................................................................................................... 3-1342 SigCRCRefRed .................................................................................................... 3-1343 SigCRCRefGreen ................................................................................................. 3-1344 SigCRCRefBlue .................................................................................................... 3-1345 SigSumRefRed ..................................................................................................... 3-1346 SigSumRefGreen ................................................................................................. 3-1347 SigSumRefBlue .................................................................................................... 3-1348 Load_Shadow ...................................................................................................... 3-1349 SoftwareKick ........................................................................................................ 3-1350 PanicFlag ............................................................................................................. 3-1351 Status ................................................................................................................... 3-1352 SigErrCount .......................................................................................................... 3-1354 SigCRCRed .......................................................................................................... 3-1355 SigCRCGreen ...................................................................................................... 3-1356 SigCRCBlue ......................................................................................................... 3-1357 SigSumRed .......................................................................................................... 3-1358 SigSumGreen ....................................................................................................... 3-1359 SigSumBlue .......................................................................................................... 3-1360

3.10 Stepper Motor Controller Registers ................................................................................... 3-13613.10.1 Stepper Motor Controller Core Register Overview .................................................... 3-1362

SMCn_PWC ............................................................................................................. 3-1363 SMCn_PWCS........................................................................................................... 3-1364 SMCn_PWCC........................................................................................................... 3-1365 SMCn_PWC1 ........................................................................................................... 3-1366 SMCn_PWC2 ........................................................................................................... 3-1367 SMCn_PWS ............................................................................................................. 3-1368 SMCn_PWSS ........................................................................................................... 3-1370 SMCn_PTRGDL ....................................................................................................... 3-1371

3.10.2 Stepper Motor Controller Trigger Register Overview ................................................. 3-1372 SMCTGg_PTRGS .................................................................................................... 3-1373 SMCTGg_PTRG....................................................................................................... 3-1376 SMCTGg_SHD1_SMC0 ........................................................................................... 3-1377 SMCTGg_SHD2_SMC0 ........................................................................................... 3-1378 SMCTGg_SHD1_SMC1 ........................................................................................... 3-1379 SMCTGg_SHD2_SMC1 ........................................................................................... 3-1380 SMCTGg_SHD1_SMC2 ........................................................................................... 3-1381 SMCTGg_SHD2_SMC2 ........................................................................................... 3-1382

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 xxiii



SMCTGg_SHD1_SMC3 ........................................................................................... 3-1383 SMCTGg_SHD2_SMC3 ........................................................................................... 3-1384 SMCTGg_SHD1_SMC4 ........................................................................................... 3-1385 SMCTGg_SHD2_SMC4 ........................................................................................... 3-1386 SMCTGg_SHD1_SMC5 ........................................................................................... 3-1387 SMCTGg_SHD2_SMC5 ........................................................................................... 3-1388

3.11 PWM-PPG Registers ......................................................................................................... 3-13893.11.1 Programmable Pulse Generator Core Register Overview ......................................... 3-1390

PPGn_PCN .............................................................................................................. 3-1391 PPGn_IRQCLR ........................................................................................................ 3-1393 PPGn_SWTRIG........................................................................................................ 3-1394 PPGn_OE................................................................................................................. 3-1395 PPGn_CNTEN.......................................................................................................... 3-1396 PPGn_OPTMSK....................................................................................................... 3-1397 PPGn_RMPCFG ...................................................................................................... 3-1399 PPGn_STRD ............................................................................................................ 3-1401 PPGn_TRIGCLR ...................................................................................................... 3-1402 PPGn_EPCN1 .......................................................................................................... 3-1403 PPGn_EPCN2 .......................................................................................................... 3-1405 PPGn_GCN1 ............................................................................................................ 3-1409 PPGn_GCN3 ............................................................................................................ 3-1411 PPGn_GCN4 ............................................................................................................ 3-1412 PPGn_GCN5 ............................................................................................................ 3-1413 PPGn_PCSR ............................................................................................................ 3-1414 PPGn_PDUT ............................................................................................................ 3-1415 PPGn_PTMR............................................................................................................ 3-1417 PPGn_PSDR ............................................................................................................ 3-1418 PPGn_PTPC ............................................................................................................ 3-1419 PPGn_PEDR ............................................................................................................ 3-1420 PPGn_DMACFG ...................................................................................................... 3-1422

3.11.2 Programmable Pulse Generators Control Register Overview ................................... 3-1423 PPGGRPp_GCTRL .................................................................................................. 3-1424 PPGGLCg_GCNR .................................................................................................... 3-1425

3.12 I2C Registers ...................................................................................................................... 3-14263.12.1 I2C Register Overview ............................................................................................... 3-1427

I2Cn_IBCSR ............................................................................................................. 3-1428 I2Cn_IODAR............................................................................................................. 3-1436 I2Cn_ICCR ............................................................................................................... 3-1437 I2Cn_ICDIDAR ......................................................................................................... 3-1438 I2Cn_IEICR .............................................................................................................. 3-1439 I2Cn_DDMACFG...................................................................................................... 3-1441 I2Cn_IEIER............................................................................................................... 3-1442

3.13 U(S)ART-LIN Registers ..................................................................................................... 3-14433.13.1 Lin-USART Register Overview .................................................................................. 3-1444

USARTn_SMR ......................................................................................................... 3-1446 USARTn_SCR.......................................................................................................... 3-1448 USARTn_SMSR ....................................................................................................... 3-1450 USARTn_SCSR ....................................................................................................... 3-1451 USARTn_SCCR ....................................................................................................... 3-1452 USARTn_TDR .......................................................................................................... 3-1453 USARTn_SSR .......................................................................................................... 3-1454 USARTn_RDR.......................................................................................................... 3-1458 USARTn_SSSR........................................................................................................ 3-1459 USARTn_SSCR ....................................................................................................... 3-1460

xxiv rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



USARTn_ECCR ....................................................................................................... 3-1461 USARTn_ESCR ....................................................................................................... 3-1464 USARTn_ECCSR..................................................................................................... 3-1466 USARTn_ESCSR ..................................................................................................... 3-1467 USARTn_ECCCR..................................................................................................... 3-1468 USARTn_ESCCR..................................................................................................... 3-1469 USARTn_ESIR ......................................................................................................... 3-1470 USARTn_EIER ......................................................................................................... 3-1473 USARTn_ESISR....................................................................................................... 3-1475 USARTn_EIESR....................................................................................................... 3-1476 USARTn_ESICR ...................................................................................................... 3-1478 USARTn_EIECR ...................................................................................................... 3-1479 USARTn_EFERL...................................................................................................... 3-1481 USARTn_EFERH ..................................................................................................... 3-1483 USARTn_RFCR........................................................................................................ 3-1484 USARTn_TFCR........................................................................................................ 3-1486 USARTn_RFCSR ..................................................................................................... 3-1488 USARTn_TFCSR...................................................................................................... 3-1489 USARTn_RFCCR..................................................................................................... 3-1490 USARTn_TFCCR ..................................................................................................... 3-1491 USARTn_RFSR........................................................................................................ 3-1492 USARTn_TFSR ........................................................................................................ 3-1493 USARTn_CSCR ....................................................................................................... 3-1494 USARTn_ESR .......................................................................................................... 3-1496 USARTn_CSCSR..................................................................................................... 3-1498 USARTn_CSCCR..................................................................................................... 3-1499 USARTn_ESCLR ..................................................................................................... 3-1500 USARTn_BGRLL...................................................................................................... 3-1501 USARTn_BGRLM..................................................................................................... 3-1502 USARTn_BGRLH ..................................................................................................... 3-1503 USARTn_BGRL........................................................................................................ 3-1504 USARTn_BGRM....................................................................................................... 3-1505 USARTn_BGRH ....................................................................................................... 3-1506 USARTn_STXDR ..................................................................................................... 3-1507 USARTn_SRXDR..................................................................................................... 3-1508 USARTn_STXDSR................................................................................................... 3-1509 USARTn_SRXDSR................................................................................................... 3-1510 USARTn_STXDCR................................................................................................... 3-1511 USARTn_SRXDCR .................................................................................................. 3-1512 USARTn_SFTRL ...................................................................................................... 3-1513 USARTn_SFTRM ..................................................................................................... 3-1514 USARTn_SFTRH...................................................................................................... 3-1515 USARTn_FIDR ......................................................................................................... 3-1516

3.14 Sound Generator Registers ............................................................................................... 3-15173.14.1 Sound Generator Register Overview ......................................................................... 3-1518

SGn_CR0 ................................................................................................................. 3-1519 SGn_CR1 ................................................................................................................. 3-1522 SGn_ECRL............................................................................................................... 3-1524 SGn_FRL.................................................................................................................. 3-1527 SGn_ARL ................................................................................................................. 3-1528 SGn_AR ................................................................................................................... 3-1529 SGn_TARL ............................................................................................................... 3-1530 SGn_TCRLIDRL....................................................................................................... 3-1531 SGn_NRL ................................................................................................................. 3-1532

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 xxv



SGn_DER................................................................................................................. 3-1533 SGn_DMAR.............................................................................................................. 3-1536

3.15 Analog-Digital Converter Registers .................................................................................... 3-15373.15.1 Analog-Digital Converter Register Overview ............................................................. 3-1538

ADCn_ER32 ............................................................................................................. 3-1543 ADCn_ER10 ............................................................................................................. 3-1544 ADCn_CS0 ............................................................................................................... 3-1545 ADCn_CS1 ............................................................................................................... 3-1547 ADCn_CS2 ............................................................................................................... 3-1550 ADCn_CS3 ............................................................................................................... 3-1551 ADCn_CSS1............................................................................................................. 3-1552 ADCn_CSC1 ............................................................................................................ 3-1553 ADCn_CSS3............................................................................................................. 3-1554 ADCn_CSC3 ............................................................................................................ 3-1555 ADCn_CR................................................................................................................. 3-1556 ADCn_MIR_CS0 ...................................................................................................... 3-1557 ADCn_MIR_CS3 ...................................................................................................... 3-1558 ADCn_CD0............................................................................................................... 3-1559 ADCn_CD1............................................................................................................... 3-1560 ADCn_CD2............................................................................................................... 3-1561 ADCn_CD3............................................................................................................... 3-1562 ADCn_CD4............................................................................................................... 3-1563 ADCn_CD5............................................................................................................... 3-1564 ADCn_CD6............................................................................................................... 3-1565 ADCn_CD7............................................................................................................... 3-1566 ADCn_CD8............................................................................................................... 3-1567 ADCn_CD9............................................................................................................... 3-1568 ADCn_CD10............................................................................................................. 3-1569 ADCn_CD11............................................................................................................. 3-1570 ADCn_CD12............................................................................................................. 3-1571 ADCn_CD13............................................................................................................. 3-1572 ADCn_CD14............................................................................................................. 3-1573 ADCn_CD15............................................................................................................. 3-1574 ADCn_CD16............................................................................................................. 3-1575 ADCn_CD17............................................................................................................. 3-1576 ADCn_CD18............................................................................................................. 3-1577 ADCn_CD19............................................................................................................. 3-1578 ADCn_CD20............................................................................................................. 3-1579 ADCn_CD21............................................................................................................. 3-1580 ADCn_CD22............................................................................................................. 3-1581 ADCn_CD23............................................................................................................. 3-1582 ADCn_CD24............................................................................................................. 3-1583 ADCn_CD25............................................................................................................. 3-1584 ADCn_CD26............................................................................................................. 3-1585 ADCn_CD27............................................................................................................. 3-1586 ADCn_CT ................................................................................................................. 3-1587 ADCn_SCH .............................................................................................................. 3-1588 ADCn_ECH .............................................................................................................. 3-1589 ADCn_MAR .............................................................................................................. 3-1590 ADCn_MACR ........................................................................................................... 3-1591 ADCn_MASR............................................................................................................ 3-1592 ADCn_RCOL0 .......................................................................................................... 3-1593 ADCn_RCOH0 ......................................................................................................... 3-1594 ADCn_RCOL1 .......................................................................................................... 3-1595

xxvi rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



ADCn_RCOH1 ......................................................................................................... 3-1596 ADCn_RCOL2 .......................................................................................................... 3-1597 ADCn_RCOH2 ......................................................................................................... 3-1598 ADCn_RCOL3 .......................................................................................................... 3-1599 ADCn_RCOH3 ......................................................................................................... 3-1600 ADCn_CC0............................................................................................................... 3-1601 ADCn_CC1............................................................................................................... 3-1603 ADCn_CC2............................................................................................................... 3-1605 ADCn_CC3............................................................................................................... 3-1607 ADCn_CC4............................................................................................................... 3-1609 ADCn_CC5............................................................................................................... 3-1611 ADCn_CC6............................................................................................................... 3-1613 ADCn_CC7............................................................................................................... 3-1615 ADCn_CC8............................................................................................................... 3-1617 ADCn_CC9............................................................................................................... 3-1619 ADCn_CC10............................................................................................................. 3-1621 ADCn_CC11............................................................................................................. 3-1623 ADCn_CC12............................................................................................................. 3-1625 ADCn_CC13............................................................................................................. 3-1627 ADCn_RCOIRS32 .................................................................................................... 3-1629 ADCn_RCOIRS10 .................................................................................................... 3-1630 ADCn_RCOOF32 ..................................................................................................... 3-1631 ADCn_RCOOF10 ..................................................................................................... 3-1632 ADCn_RCOINT32 .................................................................................................... 3-1633 ADCn_RCOINT10 .................................................................................................... 3-1634 ADCn_RCOINTC32.................................................................................................. 3-1635 ADCn_RCOINTC10.................................................................................................. 3-1636 ADCn_PCTPRL0...................................................................................................... 3-1637 ADCn_PCTNRL0...................................................................................................... 3-1638 ADCn_PCTPCT0...................................................................................................... 3-1639 ADCn_PCTNCT0...................................................................................................... 3-1640 ADCn_PCTPRL1...................................................................................................... 3-1641 ADCn_PCTNRL1...................................................................................................... 3-1642 ADCn_PCTPCT1...................................................................................................... 3-1643 ADCn_PCTNCT1...................................................................................................... 3-1644 ADCn_PCTPRL2...................................................................................................... 3-1645 ADCn_PCTNRL2...................................................................................................... 3-1646 ADCn_PCTPCT2...................................................................................................... 3-1647 ADCn_PCTNCT2...................................................................................................... 3-1648 ADCn_PCTPRL3...................................................................................................... 3-1649 ADCn_PCTNRL3...................................................................................................... 3-1650 ADCn_PCTPCT3...................................................................................................... 3-1651 ADCn_PCTNCT3...................................................................................................... 3-1652 ADCn_PCTPRL4...................................................................................................... 3-1653 ADCn_PCTNRL4...................................................................................................... 3-1654 ADCn_PCTPCT4...................................................................................................... 3-1655 ADCn_PCTNCT4...................................................................................................... 3-1656 ADCn_PCTPRL5...................................................................................................... 3-1657 ADCn_PCTNRL5...................................................................................................... 3-1658 ADCn_PCTPCT5...................................................................................................... 3-1659 ADCn_PCTNCT5...................................................................................................... 3-1660 ADCn_PCTPRL6...................................................................................................... 3-1661 ADCn_PCTNRL6...................................................................................................... 3-1662 ADCn_PCTPCT6...................................................................................................... 3-1663

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 xxvii



ADCn_PCTNCT6...................................................................................................... 3-1664 ADCn_PCTPRL7...................................................................................................... 3-1665 ADCn_PCTNRL7...................................................................................................... 3-1666 ADCn_PCTPCT7...................................................................................................... 3-1667 ADCn_PCTNCT7...................................................................................................... 3-1668 ADCn_PCTPRL8...................................................................................................... 3-1669 ADCn_PCTNRL8...................................................................................................... 3-1670 ADCn_PCTPCT8...................................................................................................... 3-1671 ADCn_PCTNCT8...................................................................................................... 3-1672 ADCn_PCTPRL9...................................................................................................... 3-1673 ADCn_PCTNRL9...................................................................................................... 3-1674 ADCn_PCTPCT9...................................................................................................... 3-1675 ADCn_PCTNCT9...................................................................................................... 3-1676 ADCn_PCTPRL10.................................................................................................... 3-1677 ADCn_PCTNRL10.................................................................................................... 3-1678 ADCn_PCTPCT10.................................................................................................... 3-1679 ADCn_PCTNCT10.................................................................................................... 3-1680 ADCn_PCTPRL11.................................................................................................... 3-1681 ADCn_PCTNRL11.................................................................................................... 3-1682 ADCn_PCTPCT11.................................................................................................... 3-1683 ADCn_PCTNCT11.................................................................................................... 3-1684 ADCn_PCTPRL12.................................................................................................... 3-1685 ADCn_PCTNRL12.................................................................................................... 3-1686 ADCn_PCTPCT12.................................................................................................... 3-1687 ADCn_PCTNCT12.................................................................................................... 3-1688 ADCn_PCTPRL13.................................................................................................... 3-1689 ADCn_PCTNRL13.................................................................................................... 3-1690 ADCn_PCTPCT13.................................................................................................... 3-1691 ADCn_PCTNCT13.................................................................................................... 3-1692 ADCn_PCTPRL14.................................................................................................... 3-1693 ADCn_PCTNRL14.................................................................................................... 3-1694 ADCn_PCTPCT14.................................................................................................... 3-1695 ADCn_PCTNCT14.................................................................................................... 3-1696 ADCn_PCTPRL15.................................................................................................... 3-1697 ADCn_PCTNRL15.................................................................................................... 3-1698 ADCn_PCTPCT15.................................................................................................... 3-1699 ADCn_PCTNCT15.................................................................................................... 3-1700 ADCn_PCTPRL16.................................................................................................... 3-1701 ADCn_PCTNRL16.................................................................................................... 3-1702 ADCn_PCTPCT16.................................................................................................... 3-1703 ADCn_PCTNCT16.................................................................................................... 3-1704 ADCn_PCTPRL17.................................................................................................... 3-1705 ADCn_PCTNRL17.................................................................................................... 3-1706 ADCn_PCTPCT17.................................................................................................... 3-1707 ADCn_PCTNCT17.................................................................................................... 3-1708 ADCn_PCTPRL18.................................................................................................... 3-1709 ADCn_PCTNRL18.................................................................................................... 3-1710 ADCn_PCTPCT18.................................................................................................... 3-1711 ADCn_PCTNCT18.................................................................................................... 3-1712 ADCn_PCTPRL19.................................................................................................... 3-1713 ADCn_PCTNRL19.................................................................................................... 3-1714 ADCn_PCTPCT19.................................................................................................... 3-1715 ADCn_PCTNCT19.................................................................................................... 3-1716 ADCn_PCTPRL20.................................................................................................... 3-1717

xxviii rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014



ADCn_PCTNRL20.................................................................................................... 3-1718 ADCn_PCTPCT20.................................................................................................... 3-1719 ADCn_PCTNCT20.................................................................................................... 3-1720 ADCn_PCTPRL21.................................................................................................... 3-1721 ADCn_PCTNRL21.................................................................................................... 3-1722 ADCn_PCTPCT21.................................................................................................... 3-1723 ADCn_PCTNCT21.................................................................................................... 3-1724 ADCn_PCTPRL22.................................................................................................... 3-1725 ADCn_PCTNRL22.................................................................................................... 3-1726 ADCn_PCTPCT22.................................................................................................... 3-1727 ADCn_PCTNCT22.................................................................................................... 3-1728 ADCn_PCTPRL23.................................................................................................... 3-1729 ADCn_PCTNRL23.................................................................................................... 3-1730 ADCn_PCTPCT23.................................................................................................... 3-1731 ADCn_PCTNCT23.................................................................................................... 3-1732 ADCn_PCTPRL24.................................................................................................... 3-1733 ADCn_PCTNRL24.................................................................................................... 3-1734 ADCn_PCTPCT24.................................................................................................... 3-1735 ADCn_PCTNCT24.................................................................................................... 3-1736 ADCn_PCTPRL25.................................................................................................... 3-1737 ADCn_PCTNRL25.................................................................................................... 3-1738 ADCn_PCTPCT25.................................................................................................... 3-1739 ADCn_PCTNCT25.................................................................................................... 3-1740 ADCn_PCTPRL26.................................................................................................... 3-1741 ADCn_PCTNRL26.................................................................................................... 3-1742 ADCn_PCTPCT26.................................................................................................... 3-1743 ADCn_PCTNCT26.................................................................................................... 3-1744 ADCn_PCTPRL27.................................................................................................... 3-1745 ADCn_PCTNRL27.................................................................................................... 3-1746 ADCn_PCTPCT27.................................................................................................... 3-1747 ADCn_PCTNCT27.................................................................................................... 3-1748 ADCn_PCZF10......................................................................................................... 3-1749 ADCn_PCZF32......................................................................................................... 3-1750 ADCn_PCZFC10 ...................................................................................................... 3-1751 ADCn_PCZFC32 ...................................................................................................... 3-1752 ADCn_PCIE10.......................................................................................................... 3-1753 ADCn_PCIE32.......................................................................................................... 3-1754 ADCn_PCIES10 ....................................................................................................... 3-1755 ADCn_PCIES32 ....................................................................................................... 3-1756 ADCn_PCIEC10 ....................................................................................................... 3-1757 ADCn_PCIEC32 ....................................................................................................... 3-1758

3.16 Reload Timer Registers ..................................................................................................... 3-17593.16.1 Reload Timer Register Overview ............................................................................... 3-1760

RLTn_DMACFG ....................................................................................................... 3-1761 RLTn_TMCSR .......................................................................................................... 3-1762 RLTn_TMRLR .......................................................................................................... 3-1765 RLTn_TMR ............................................................................................................... 3-1766

3.17 GPIO Registers .................................................................................................................. 3-17673.17.1 General Purposes IO Register Overview ................................................................... 3-1768

POSR0 Low.............................................................................................................. 3-1769 POSR0 High ............................................................................................................. 3-1770 POCR0 Low.............................................................................................................. 3-1771 POCR0 High............................................................................................................. 3-1772 DDSR0 Low.............................................................................................................. 3-1773

June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 xxix



DDSR0 High ............................................................................................................. 3-1774 DDCR0 Low.............................................................................................................. 3-1775 DDCR0 High............................................................................................................. 3-1776 POSR1 Low.............................................................................................................. 3-1777 POSR1 High ............................................................................................................. 3-1778 POCR1 Low.............................................................................................................. 3-1779 POCR1 High............................................................................................................. 3-1780 DDSR1 Low.............................................................................................................. 3-1781 DDSR1 High ............................................................................................................. 3-1782 DDCR1 Low.............................................................................................................. 3-1783 DDCR1 High............................................................................................................. 3-1784 PODR0 Low.............................................................................................................. 3-1785 PODR0 High............................................................................................................. 3-1786 DDR0 Low ................................................................................................................ 3-1787 DDR0 High ............................................................................................................... 3-1788 PODR1 Low.............................................................................................................. 3-1789 PODR1 High............................................................................................................. 3-1790 DDR1 Low ................................................................................................................ 3-1791 DDR1 High ............................................................................................................... 3-1792 PIDR0 Low ............................................................................................................... 3-1793 PIDR0 High............................................................................................................... 3-1794 PIDR1 Low ............................................................................................................... 3-1795 PIDR1 High............................................................................................................... 3-1796 PPER0 Low .............................................................................................................. 3-1797 PPER0 High ............................................................................................................. 3-1798 PPER1 Low .............................................................................................................. 3-1799 PPER1 High ............................................................................................................. 3-1800

3.18 External Interrupt Registers ............................................................................................... 3-18013.18.1 External Interrupt Register Overview ......................................................................... 3-1802

ENIRn ....................................................................................................................... 3-1803 ENISRn.....................................................................................................................3-1804 ENICRn .................................................................................................................... 3-1805 EIRRn ....................................................................................................................... 3-1806 EIRCRn .................................................................................................................... 3-1807 NFERn...................................................................................................................... 3-1808 NFESRn ................................................................................................................... 3-1809 NFECRn ................................................................................................................... 3-1810 ELVR0n .................................................................................................................... 3-1811 DRERn ..................................................................................................................... 3-1813 DRESRn ................................................................................................................... 3-1814 DRECRn................................................................................................................... 3-1815 DRFRn...................................................................................................................... 3-1816

xxx rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014


Chapter 1: Memory Map

The table below shows all instances with the respective base address offset.

Table 1-1: Indigo2 Memory Map

Instance Base Address Offset

Global Control 0x00000000

APIX2 PHY 0x00020000

APIX2 RX 0x00021000

Ashell remote handler 0x00022000

E2IP 0x00023000

E2IP remote handler 0x00024000

HDCP Decoder control 0x00025000

SPI Interface for Flash 0x00026000

Programmable CRC checker 0x00027000

DMA Controller 0x00028000

Command Sequencer 0x0002C000

Control for internal Flash 0x0002D000

Configuration Fifo 0x0002E000

IRIS MVL global control 0x00030000

IRIS MVL pixel engine toplevel 0x00030800

IRIS MVL pixel engine Fetch RLD 0x00030C00

IRIS MVL pixel engine Fetch Sprite 0x00031000

IRIS MVL pixel engine ExtSrc (APIX input stream) 0x00031400

IRIS MVL pixel engine ExtDst0 (Memory stream) 0x00031800

IRIS MVL pixel engine ExtDst1 (Capture stream) 0x00031C00

IRIS MVL pixel engine CLUT 0x00032000

IRIS MVL pixel engine Layerblend0 (Foreground) 0x00032800

IRIS MVL pixel engine Layerblend1 (Sprite) 0x00032C00

IRIS MVL display engine toplevel 0x00033000

IRIS MVL display engine Frame Generator 0x00033400

IRIS MVL display engine Display Matrix 0x00033800

IRIS MVL display engine CLUT 0x00033C00

IRIS MVL display engine Dither 0x00034400

IRIS MVL display engine Timing Controller 0x00034800

IRIS MVL display engine signature unit 0 0x00035000



IRIS MVL display engine signature unit 3 0x00035C00

IRIS MVL capture engine 0x00036800

Stepper Motor Controller 0 0x00080000



Stepper Motor Controller 3 0x00080C00



Stepper Motor Controller Trigger 0x00081C00

Pulse Width Modulator 0 0x00088000


June 17, 2014 rd-mb88F33x-indigo2(-x)-rev1-20 1 - 1



Pulse Width Modulator 3 0x00088C00

Pulse Width Modulator Group 0-3 0x00089000

Pulse Width Modulator 4 0x0008A000



Pulse Width Modulator 7 0x0008AC00

Pulse Width Modulator Group 4-7 0x0008B000




Pulse Width Modulator 11 0x0008CC00

Pulse Width Modulator Group 8-11 0x0008D000

Pulse Width Modulator 12 0x0008E000



Pulse Width Modulator 15 0x0008EC00

Pulse Width Modulator Group 12-15 0x0008F000

Pulse Width Modulator Common Control 0x00090000

I2C Interface 0 0x00094000

I2C Interface 1 0x00095000

LIN interface 0x00096000

Sound Generator 0x00097000

Analog Digital Converter 0x00098000

Error Collection Unit for RBUS Modules 0x00099000

Reload timer 0 0x000A0000
















GPIO control 0x000A8000

Error Collection Unit for eRBUS Modules 0x000A9000

External Interrupt Controller 0x000B0000

SPI Interface for external devices 0x000B1000

Table 1-1: Indigo2 Memory Map

Instance Base Address Offset

1 - 2 rd-mb88F33x-indigo2(-x)-rev1-20 June 17, 2014


Chapter 2: General Information

The purpose of this document is to provide information about all registers of the MB88F33x ‘Indigo2(-x)’.It contains Register Overview tables, description of each registers, including the lock/unlock registers,as well as information about the format and the meaning of the register tables.

2.1 Format

The register descriptions tables in this document use the format shown below to describe each bitfield of a register.

2.2 Meaning of Items and Sign

Base Address: Gives the register block address(es) for that specific module. Please refer to theaddress map for more information.

Register Address: Register address shows the address (Offset address) of the register.

Bit Position: Bit number shows the bit position of the register.

Bit Field Name: Field name shows bit name of the register.

Type: It shows the read/write attribute of each bit field:

R: Read

W: Write

W1C: Writing a value of "1" clears the register.

R0:Read value is always "0"

R1: Read value is always "1"

W0: Write value is always "0", and write access of "1" is ignored

W1: Write value is always "1", and write access of "0" is ignored

Reset: Reset value indicates the value of each bit field immediately after reset.

0:Initial value is "0"

1:Initial value is "1"

X:Undefined

Locked (): Locked registers (Locked == yes) can only be written if the register has been previouslyunlocked by writing the unlock key to the lock/unlock key register (Locked == key) first. They can bemade non-writable again by writing the lock key to the lock/unlock register. The current lock status canbe gotten from the Locked == status register.

Please note, that access to an address with no register or writing to a currently locked (Locked==yes)register results in a bus error. This will generate either an interrupt or an error response at the used hostinterface

Table 2-1: Example of a register description table

Bit Position Bit Field Name Type Reset Bit Description

[31:27] Reserved - - -

[26:1] Status R 0x0 Status register

[0] Error0 R 0x0 Execution of core #0 stopped after illegal instruction



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Chapter 3: Registers Descriptions

In this chapter, all registers of the MB88F33x ‘Indigo2(-x)’ are described.



3.1 Global Control Registers

In this section, the ‘Register Overview’ table summarizes all global control registers, including baseaddress of the module and name, description, and the absolute address of each register, which are thendescribed separately in the following tables.


3.1.1 Global Control Register Overview

Table 3-1: Registers Overview

Base Address(es) Instance no 0: BASEADDR="00000000"

Absolute Address Register Name Register Description

BASEADDR + 0x0000 CHIP_ID CHIP Identification

BASEADDR + 0x0004 CHIP_INFO CHIP Information

BASEADDR + 0x0008 GC_TEST Test register

BASEADDR + 0x000C GC_PROGID Programming ID

BASEADDR + 0x0010 LockUnlockRegister to lock or unlock write access to registers of this unit with lock property.

BASEADDR + 0x0014 LockStatusLock status for write access to registers of this unit with lock property.

BASEADDR + 0x0018 IFC_CTRL Interface control

BASEADDR + 0x001C LVD Low voltage detection

BASEADDR + 0x0020 SYSWD_RES System Watchdog reset

BASEADDR + 0x0024 SYSWD_CTL System Watchdog control

BASEADDR + 0x0028 SYSWD_CNT System Watchdog counter value

BASEADDR + 0x002C SYSWD_WNDW System Watchdog counter window

BASEADDR + 0x0030 SYSWD_STS System Watchdog counter value

BASEADDR + 0x0034 ALVSND_CTL Alive Sender control

BASEADDR + 0x0038 ALVSND_MEN Alive Sender Mask enable

BASEADDR + 0x003C ALVSND_STS Alive Sender mask status

BASEADDR + 0x0040 Reserved Do not modify



BASEADDR + 0x004C Reserved Do not modify




BASEADDR + 0x0080 CLOCK_SELECTION Clock selection Register

BASEADDR + 0x0084 CLOCK_DIV Clock divider ratio Register

BASEADDR + 0x0088 PLL_CTRL PLL Control

BASEADDR + 0x008C PLL_PIXCLOCK Clock control for PLL Pixel clock

BASEADDR + 0x0090 PLL_CLOCK_DIV Clock divider ratio for PLL clock


BASEADDR + 0x0098 PWR_CTRL Power Down Control Reset

BASEADDR + 0x0100 DISP_CTL Control of display output.

BASEADDR + 0x0104 DISP0_PN0_CTL Control of DISP0 P0/N0 output pad.


BASEADDR + 0x010C DISP0_PN2_CTL Control of DISP0 P2/N2 output pad.


























BASEADDR + 0x016C TSIG0_3_CTL Control of TSIG0-3 output pads.

BASEADDR + 0x0170 TSIG4_7_CTL Control of TSIG4-7 output pads.

BASEADDR + 0x0174 TSIG8_11_CTL Control of TSIG8-11 output pads.

BASEADDR + 0x0178 DSPINV_CTL Control of DSPINV output pad.

BASEADDR + 0x0200 ADC3_CTL Control of ADC3 pad



BASEADDR + 0x020C ADC0_CTL Control of ADC0 pad

BASEADDR + 0x0210 SMC_1M_0_CTL Control of SMC_1M_0 pad

BASEADDR + 0x0214 SMC_1P_0_CTL Control of SMC_1P_0 pad


BASEADDR + 0x021C SMC_2P_0_CTL Control of SMC_2P_0 pad





















BASEADDR + 0x0270 CFG5_CTL Control of CFG5 pad



BASEADDR + 0x027C CFG2_CTL Control of CFG2 pad



Table 3-1: Registers Overview (Continued)





BASEADDR + 0x0288 DISP1_0_CTL Control of DISP1_0 pad

BASEADDR + 0x028C DISP1_1_CTL Control of DISP1_1 pad





BASEADDR + 0x02A0 DISP1_6_CTL Control of DISP1_6 pad



BASEADDR + 0x02AC DISP1_9_CTL Control of DISP1_9 pad

BASEADDR + 0x02B0 DISP1_10_CTL Control of DISP1_10 pad



BASEADDR + 0x02BC TSIG11_CTL Control of TSIG11 pad

BASEADDR + 0x02C0 TSIG10_CTL Control of TSIG10 pad



BASEADDR + 0x02CC TSIG7_CTL Control of TSIG7 pad

BASEADDR + 0x02D0 TSIG6_CTL Control of TSIG6 pad



BASEADDR + 0x02DC TSIG3_CTL Control of TSIG3 pad

BASEADDR + 0x02E0 TSIG2_CTL Control of TSIG2 pad



BASEADDR + 0x02EC DISP0_0_CTL Control of DISP0_0 pad

BASEADDR + 0x02F0 DISP0_1_CTL Control of DISP0_1 pad



BASEADDR + 0x02FC DISP0_4_CTL Control of DISP0_4 pad









BASEADDR + 0x0320 SG_SGO_CTL Control of SG_SGO pad

BASEADDR + 0x0324 SG_SGA_CTL Control of SG_SGA pad

BASEADDR + 0x0328 I2C0_SDA_CTL Control of I2C0_SDA pad

BASEADDR + 0x032C I2C0_SCL_CTL Control of I2C0_SCL pad

BASEADDR + 0x0330 I2C1_SDA_CTL Control of I2C1_SDA pad

BASEADDR + 0x0334 I2C1_SCL_CTL Control of I2C1_SCL pad












BASEADDR + 0x0400 MODULE_IRQ_STS Interrupt status for submodule

BASEADDR + 0x0404 APIX_CLR Interrupt clear for APIX interrupts

BASEADDR + 0x0408 APIX_SET Interrupt set for APIX interrupts

BASEADDR + 0x040C APIX_STS Interrupt status for APIX interrupts

BASEADDR + 0x0410 ASHELL_RH_CLR Interrupt clear for ASHELL_RH interrupts

BASEADDR + 0x0414 ASHELL_RH_SET Interrupt set for ASHELL_RH interrupts

BASEADDR + 0x0418 ASHELL_RH_STS Interrupt status for ASHELL_RH interrupts

BASEADDR + 0x041C E2IP_CLR Interrupt clear for E2IP interrupts

BASEADDR + 0x0420 E2IP_SET Interrupt set for E2IP interrupts

BASEADDR + 0x0424 E2IP_STS Interrupt status for E2IP interrupts

BASEADDR + 0x0428 CFF_CTRL_CLR Interrupt clear for CFF_CTRL interrupts

BASEADDR + 0x042C CFF_CTRL_SET Interrupt set for CFF_CTRL interrupts

BASEADDR + 0x0430 CFF_CTRL_STS Interrupt status for CFF_CTRL interrupts

BASEADDR + 0x0434 CFF_FIFO_CLR Interrupt clear for CFF_FIFO interrupts

BASEADDR + 0x0438 CFF_FIFO_SET Interrupt set for CFF_FIFO interrupts

BASEADDR + 0x043C CFF_FIFO_STS Interrupt status for CFF_FIFO interrupts

BASEADDR + 0x0440 RLT_STS Interrupt status for RLT interrupts

BASEADDR + 0x0444 LIN_STS Interrupt status for LIN interrupts

BASEADDR + 0x0448 PPG_STS Interrupt status for PPG interrupts

BASEADDR + 0x044C I2C0_STS Interrupt status for I2C0 interrupts

BASEADDR + 0x0450 I2C1_STS Interrupt status for I2C1 interrupts

BASEADDR + 0x0454 SGE_CLR Interrupt clear for SGE interrupts

BASEADDR + 0x0458 SGE_SET Interrupt set for SGE interrupts

BASEADDR + 0x045C SGE_STS Interrupt status for SGE interrupts

BASEADDR + 0x0460 ADC_STS Interrupt status for ADC interrupts

BASEADDR + 0x0464 EIRQ_STS Interrupt status for EIRQ interrupts

BASEADDR + 0x0468 ESPI_STS Interrupt status for ESPI interrupts

BASEADDR + 0x046C IRIS_CLR Interrupt clear for IRIS interrupts

BASEADDR + 0x0470 IRIS_SET Interrupt set for IRIS interrupts

BASEADDR + 0x0474 IRIS_STS Interrupt status for IRIS interrupts

BASEADDR + 0x0478 CMDSEQ_CLR Interrupt clear for CMDSEQ interrupts

BASEADDR + 0x047C CMDSEQ_SET Interrupt set for CMDSEQ interrupts

BASEADDR + 0x0480 CMDSEQ_STS Interrupt status for CMDSEQ interrupts

BASEADDR + 0x0484 GC_CLR Interrupt clear for GC interrupts

BASEADDR + 0x0488 GC_SET Interrupt set for GC interrupts

BASEADDR + 0x048C GC_STS Interrupt status for GC interrupts

BASEADDR + 0x0490 DMAC_STS Interrupt status for DMAC interrupts

BASEADDR + 0x0494 FSPI_STS Interrupt status for FSPI interrupts

BASEADDR + 0x0498 PRGCRC_STS Interrupt status for PRGCRC interrupts

BASEADDR + 0x049C INTERCONNECT_CLR Interrupt clear for INTERCONNECT interrupts

BASEADDR + 0x04A0 INTERCONNECT_SET Interrupt set for INTERCONNECT interrupts

BASEADDR + 0x04A4 INTERCONNECT_STS Interrupt status for INTERCONNECT interrupts

BASEADDR + 0x04A8 IRQ_CMDSEQ_SEL0 Interrupt select for command sequencer

BASEADDR + 0x04AC IRQ_CMDSEQ_SEL1 Interrupt select for command sequencer

BASEADDR + 0x04B0 CFF_TRG_SEL0 Trigger select for Config Fifo

BASEADDR + 0x04B4 CFF_TRG_SEL1 Trigger select for Config Fifo

BASEADDR + 0x04B8 HIRQ_CTL Host interrupt control

BASEADDR + 0x04BC APIX_HIEN Host interrupt enable for APIX interrupts

BASEADDR + 0x04C0 ASHELL_RH_HIEN Host interrupt enable for ASHELL_RH interrupts

BASEADDR + 0x04C4 E2IP_HIEN Host interrupt enable for E2IP interrupts






BASEADDR + 0x04C8 CFF_CTRL_HIEN Host interrupt enable for CFF_CTRL interrupts

BASEADDR + 0x04CC CFF_FIFO_HIEN Host interrupt enable for CFF_FIFO interrupts

BASEADDR + 0x04D0 RLT_HIEN Host interrupt enable for RLT interrupts

BASEADDR + 0x04D4 LIN_HIEN Host interrupt enable for LIN interrupts

BASEADDR + 0x04D8 PPG_HIEN Host interrupt enable for PPG interrupts

BASEADDR + 0x04DC I2C0_HIEN Host interrupt enable for I2C0 interrupts

BASEADDR + 0x04E0 I2C1_HIEN Host interrupt enable for I2C1 interrupts

BASEADDR + 0x04E4 SGE_HIEN Host interrupt enable for SGE interrupts

BASEADDR + 0x04E8 ADC_HIEN Host interrupt enable for ADC interrupts

BASEADDR + 0x04EC EIRQ_HIEN Host interrupt enable for EIRQ interrupts

BASEADDR + 0x04F0 ESPI_HIEN Host interrupt enable for ESPI interrupts

BASEADDR + 0x04F4 IRIS_HIEN Host interrupt enable for IRIS interrupts

BASEADDR + 0x04F8 CMDSEQ_HIEN Host interrupt enable for CMDSEQ interrupts

BASEADDR + 0x04FC GC_HIEN Host interrupt enable for GC interrupts

BASEADDR + 0x0500 DMAC_HIEN Host interrupt enable for DMAC interrupts

BASEADDR + 0x0504 FSPI_HIEN Host interrupt enable for FSPI interrupts

BASEADDR + 0x0508 PRGCRC_HIEN Host interrupt enable for PRGCRC interrupts

BASEADDR + 0x050C INTERCONNECT_HIEN Host interrupt enable for INTERCONNECT interrupts

BASEADDR + 0x0510 PNCSW_CTL Panic Switch control

BASEADDR + 0x0514 APIX_PSEN Panic switch enable for APIX interrupts

BASEADDR + 0x0518 ASHELL_RH_PSEN Panic switch enable for ASHELL_RH interrupts

BASEADDR + 0x051C E2IP_PSEN Panic switch enable for E2IP interrupts

BASEADDR + 0x0520 CFF_CTRL_PSEN Panic switch enable for CFF_CTRL interrupts

BASEADDR + 0x0524 CFF_FIFO_PSEN Panic switch enable for CFF_FIFO interrupts

BASEADDR + 0x0528 RLT_PSEN Panic switch enable for RLT interrupts

BASEADDR + 0x052C LIN_PSEN Panic switch enable for LIN interrupts

BASEADDR + 0x0530 PPG_PSEN Panic switch enable for PPG interrupts

BASEADDR + 0x0534 I2C0_PSEN Panic switch enable for I2C0 interrupts

BASEADDR + 0x0538 I2C1_PSEN Panic switch enable for I2C1 interrupts

BASEADDR + 0x053C SGE_PSEN Panic switch enable for SGE interrupts

BASEADDR + 0x0540 ADC_PSEN Panic switch enable for ADC interrupts

BASEADDR + 0x0544 EIRQ_PSEN Panic switch enable for EIRQ interrupts

BASEADDR + 0x0548 ESPI_PSEN Panic switch enable for ESPI interrupts

BASEADDR + 0x054C IRIS_PSEN Panic switch enable for IRIS interrupts

BASEADDR + 0x0550 CMDSEQ_PSEN Panic switch enable for CMDSEQ interrupts

BASEADDR + 0x0554 GC_PSEN Panic switch enable for GC interrupts

BASEADDR + 0x0558 DMAC_PSEN Panic switch enable for DMAC interrupts

BASEADDR + 0x055C FSPI_PSEN Panic switch enable for FSPI interrupts

BASEADDR + 0x0560 PRGCRC_PSEN Panic switch enable for PRGCRC interrupts

BASEADDR + 0x0564 INTERCONNECT_PSEN Panic switch enable for INTERCONNECT interrupts

BASEADDR + 0x0568 DMA_CNTRL Control for Interrupt base DMA requests






CHIP_ID

Description: CHIP Identification

Absolute Register Address(es):

Instance no 0: 0x00000000

Table 3-2: CHIP_ID Register


[31:0] CID R 0x88463341

Chip ID number

0x88463341: Indigo2 - Full feature

0x88463351: Indigo2_S - Subset

0x88463361: Indigo2_N - No HDCP



CHIP_INFO

Description: CHIP Information



Table 3-3: CHIP_INFO Register


[31:12] Reserved R 0x0 -

[11] ProgIDvalid R 0x0 Programming ID for HDCP keys valid.

[10:5] CFG R 0x0 Bootstrap configuration pin status.

[4] HDCP R 0x0 HDCP keys stored in flash.

0x0: NO - No Keys stored

0x1: YES - Keys stored




GC_TEST

Description: Test register



Table 3-4: GC_TEST Register


[31:0] test RW 0x0 Test register, readback will be inverted write value.



GC_PROGID

Description: Programming ID


Instance no 0: 0x0000000C

Table 3-5: GC_PROGID Register


[31:0] progID R 0x0 Programming ID for HDCP keys.



LockUnlock

Description: Register to lock or unlock write access to registers of this unit with lock property.



Table 3-6: LockUnlock Register


[31:0] LockUnlock W 0x0 Write lock key (0xa82be775) or unlock key (0x69b309b8) to this field in order to change lock status.

Writing the lock key when unit is locked or the unlock key when unit is unlocked or an invalid key value generates an error response.



LockStatus

Description: Lock status for write access to registers of this unit with lock property.



Table 3-7: LockStatus Register



[0] LockStatus R 0x1 Current lock status.

0: Unlocked - Unlocked

1: Locked - Locked



IFC_CTRL

Description: Interface control



Table 3-8: IFC_CTRL Register



[9:8] mii_mux RW 0x0 MII mux control

0: APX_E2IP - Ethernet from APIX con-nected to E2IP module

1: APX_IO - Ethernet from APIX connected to external

2: IO_E2IP - Ethernet from external con-nected to E2IP

[7] Reserved R 0x0 -

[6] zpd_adc_en RW 0x0 Enable for ADC channels at stepper motor IOs (channel 16 to 27)

If ADC channels 16 to 27 are enabled when HVDD is not equal AVCC this will destroy the chip!

0: DISABLE - Disable ADC channel 16 to 27

1: ENABLE - Enable ADC channel 16 to 27

[5] apix_gpio1_oen RW 0x0 APIX GPIO1 output enable

0: input - APIX GPIO 1 is input

1: output - APIX GPIO 1 in output

[4] apix_gpio0_oen RW 0x0 APIX GPIO0 output enable

0: input - APIX GPIO 0 is input

1: output - APIX GPIO 0 in output


[2:1] Reserved RW 0x0 -

[0] hifc_disable RW 0x0 Disable Host interface



LVD

Description: Low voltage detection



Table 3-9: LVD Register



[12] lvdl R 0x0 Low voltage detection (VDD)

0x0: LOW - below detection voltage

0x1: HIGH - more than detection voltage

[11:9] svl RW 0x5 Detection voltage

0x0: V_0v5 - threshold 0.4V - 0.6V








[8] pdlvdl RW 0x1 Power down of low voltage detection for core supply (VDD)

0x0: ON - operation

0x1: OFF - power down


[4] lvdh R 0x0 Low voltage detection (VDP5)

0x0: LOW - below detection voltage

0x1: HIGH - more than detection voltage

[3:1] svh RW 0x7 Detection voltage threshold setting









[0] pdlvdh RW 0x1 Power down of low voltage detection for GPIO supply (VDP5)

0x0: ON - operation

0x1: OFF - power down



SYSWD_RES

Description: System Watchdog reset



Table 3-10: SYSWD_RES Register



[0] wdg_reset R0W1

0x0 Watchdog reset, writing a 1 will reset the watchdog counter

Writing this register requires to do an unlock first.



SYSWD_CTL

Description: System Watchdog control



Table 3-11: SYSWD_CTL Register



[7:4] wdg_prediv RW 0xF Clock predivider for the watchdog counter, the clock is predivided by 2 power wdg_prediv


[1] wdg_test R0W1

0x0 Watchdog interrupt test, writing a 1 will trig-ger an watchdog interrupt

[0] wdg_enable RW 0x0 Watchdog enable

0x0: DISABLE - counter and interrupt dis-abled

0x1: ENABLE - counter and interrupt enabled



SYSWD_CNT

Description: System Watchdog counter value



Table 3-12: SYSWD_CNT Register



[27:0] wdg_count_start RW 0xFFFFFFF

Watchdog counter start value, the counter is set to this value with every wdg_reset and decremented afterwards with every clock



SYSWD_WNDW

Description: System Watchdog counter window



Table 3-13: SYSWD_WNDW Register



[27:0] wdg_resetwindow_start RW 0xFFFFFFF

Watchdog counter reset window start value, if the counter is reset before the wdg_resetwindow_start value is reached an error irq will be issued



SYSWD_STS

Description: System Watchdog counter value



Table 3-14: SYSWD_STS Register



[27:0] wdg_count R 0x0 Current counter value of watchdog counter



ALVSND_CTL

Description: Alive Sender control



Table 3-15: ALVSND_CTL Register



[6:4] as_select RW 0x0 Select for periodic alive signal

0x0: IRS_FG_P0 - IRIS FrameGen0 pro-grammable interrupt

0x1: IRS_SIG0_RDY - IRIS SIG0 Mea-surement complete interrupt




0x5: RLT_15 - RLT timer 15 output pulse


[1] as_maskreset R0W1

0x0 Writing a 1 will reset all stored mask condi-tions

[0] as_enable RW 0x0 Alive sender enable

0x0: DISABLE - disabled

0x1: ENABLE - enabled



ALVSND_MEN

Description: Alive Sender Mask enable



Table 3-16: ALVSND_MEN Register


[31:0] as_maskenable RW 0x0 Enable of alive signal mask bit

Bit 0: system watchdog

Bit 1: cmdseq watchdog

Bit 2: panic switch

Bit 3: sig 0 error

Bit 4: sig 1 error

Bit 5: sig 2 error

Bit 6: sig 3 error

Bit 7: ext irq 0

Bit 8: ext irq 1

Bit 9: ext irq 2

Bit10: ext irq 3

Bit11: ext irq 4

Bit12: ext irq 5

Bit13: ext irq 6

Bit14: ext irq 7

Bit15: APIX link error

Bit16: APIX link fatal error

Bit17: APIX ashell error

Bit18: APIX ashell fatal error

Bit19: APIX pixel fifo error

Bit20: APIX pixel fifo fatal error

Bit21: IRIS primary framegenerator sync loss

Bit22: IRIS secondary framegenerator sync loss

Bit23: IRIS frame capture sync error

Bit24: Command Sequencer error

Bit25: low voltage detection core supply low

Bit26: low voltage detection IO supply low

Bit27: Ashell Remote handler read error

Bit28: Ashell Remote handler write error

Bit29: E2IP Remote handler read error

Bit30: E2IP Remote handler write error

Bit31: config fifo error



ALVSND_STS

Description: Alive Sender mask status



Table 3-17: ALVSND_STS Register


[31:0] as_mask R 0x0 Current status of mask bits



CLOCK_SELECTION

Description: Clock selection Register



Table 3-18: CLOCK_SELECTION Register



[12] i2s_pllsel RW 0x0 Select i2s clock; 1=pll_clk, 0=apix_clk

0x0: SEL_APIX - APIX clock is selected (default).

0x1: SEL_PLL - PLL clock is selected.

[11] mii_pllsel RW 0x0 Select mii clock; 1=pll_clk, 0=apix_clk



[10] sys_pllsel RW 0x0 Select system clock; 1=pll_clk, 0=apix_clk



[9] peri_pllsel RW 0x0 Select peripheral clock; 1=pll_clk, 0=apix_clk



[8] vid_pllsel RW 0x0 Select video clock; 1=pll_clk, 0=apix_clk




[6] i2s_clksel RW 0x0 Select APIX Audio (i2s_clk) clock

0x0: SEL_OSC - osc clock (osc_clk) is selected (default).

0x1: SEL_MCLK - mclk clock (mclk_clk) is selected.

[5] mii_clksel RW 0x0 Select APIX MII clock


0x1: SEL_MII - MII clock (mii_clk) is selected.

[4] apix_clksel RW 0x0 Select APIX core clock (core_clk)


0x1: SEL_CDR - recovered APIX clock (rx_base_clk) is selected.



[3] sys_clksel RW 0x0 Select system clock (AXI/AHB clock)


0x1: SEL_SYS - system clock (sys_clk) is selected.

[2] peri_clksel RW 0x0 Select periphery clock


0x1: SEL_PERI - periphery clock (peri_clk) is selected.

[1] vid_clksel RW 0x0 Select non shift video clock


0x1: SEL_VID - non shift video clock (vid_clk) is selected.

[0] vids_clksel RW 0x0 Select shift video clock


0x1: SEL_VIDS - shift video clock (vids_clk) is selected.

Table 3-18: CLOCK_SELECTION Register




CLOCK_DIV

Description: Clock divider ratio Register



Table 3-19: CLOCK_DIV Register



[6] FLASH_div RW 0x1 Divider ratio to generate Flash clock from sys_clock.

0x0: OFF - no division is performed (flsha_clock = flshb_clock = sys_clock).

0x1: DIV2 - division by 2 is performed (flsha_clock and flshb_clock have phase offset) (default).

[5:4] AHB_div RW 0x1 Divider ratio to generate AHB clock from sys_clock.

0x0: OFF - no division is performed (ahb_clock = sys_clock).

0x1: DIV2 - division by 2 is performed (default).

0x2: DIV4 - division by 4 is performed.

0x3: RSVD - same like above, division by 4 is performed.

[3:2] rbus_div RW 0x1 Divider ratio to generate rbus clock from periphery clock.

0x0: OFF - no division is performed (rbus clock = periphery clock).

0x1: DIV2 - division by 2 is performed (default).



[1:0] erbus_div RW 0x1 Divider ratio to generate erbus clock from periphery clock.

0x0: OFF - no division is performed (erbus clock = periphery clock).

0x1: DIV2 - division by 2 is performed (default) .





PLL_CTRL

Description: PLL Control



Table 3-20: PLL_CTRL Register



[23:22] pll_loopfilter RW 0x1 PLL Loop filter capacitance

[21:16] pll_crgpmpctrl RW 0xF PLL Charge pump current control


[11:8] pll_idiv RW 0xA PLL feedback divider

Only even numbers are allowed

Value 0 - feedback divider ratio = 32




Value ...




[5:4] pll_vcobias RW 0x0 Select VCO bias


[2] pll_lock R 0x0 PLL lock flag

[1] pll_clksel RW 0x0 Select PLLinput clock

0x0: SEL_OSC - Oscillator clock is selected (default).

0x1: SEL_VID - Vid clock from clock syn-thesis is selected.

[0] pll_enable RW 0x0 Enable operation of PLL

0x0: DISABLE - disable PLL

0x1: ENABLE - enable PLL



PLL_PIXCLOCK

Description: Clock control for PLL Pixel clockPLL clock (see PLL_CTRL) has to be enabled and stable before writing this register.



Table 3-21: PLL_PIXCLOCK Register



[15:8] pll_pixofs RW 0x0 PLL Shift Pixel clock offset

Output clock is shifted by n pll_clock cycles

Maximum allowed value is pll_pixdiv

[7:0] pll_pixdiv RW 0xFF PLL Pixel clock divider

Output frequency is input frequency divided by register_value + 1

Register value 0 is not allowed



PLL_CLOCK_DIV

Description: Clock divider ratio for PLL clockPLL clock (see PLL_CTRL) has to be enabled and stable before writing this register.



Table 3-22: PLL_CLOCK_DIV Register


[31:24] pll_i2sdiv RW 0xFF PLL I2S clock divider



[23:16] pll_miidiv RW 0xFF PLL MII clock divider

MII clock has to be 25MHz



[15:8] pll_sysdiv RW 0xFF PLL System clock divider



[7:0] pll_peridiv RW 0xFF PLL Peripheral clock divider





PWR_CTRL

Description: Power Down Control Reset



Table 3-23: PWR_CTRL Register



[18] dmac_pd_rdy R 0x0 Power down ready for DMA Controller.

If ready clock can be disabled.

[17] dmac_pd_req RW 0x0 Power down request for DMA Controller.

[16] dmac_clk_dis RW 0x0 Disable of the clock for the DMA Controller.

Software has to ensure, that the module is idle before disabling it.

0x0: ENABLE - -

0x1: DISABLE - -


[14] cff_pd_rdy R 0x0 Power down ready for Config Fifo.

If ready clock can be disabled.

[13] cff_pd_req RW 0x0 Power down request for Config Fifo.

[12] cff_clk_dis RW 0x0 Disable of the clock for the Config fifo.

Software has to ensure, that the module is idle before disabling it.

0x0: ENABLE - -

0x1: DISABLE - -


[9] diff_clk_dis RW 0x0 Disable of the clock for TTL panel output.

0x0: ENABLE - -

0x1: DISABLE - -

[8] dual_clk_dis RW 0x0 Disable of the clock for the second (dual) panel output.

0x0: ENABLE - -

0x1: DISABLE - -


[5] Reserved R0W1

0x0 -

[4] Reserved R0W1

0x0 -

[3] rh_ahb_active R 0x0 Current status of clocks in the Ashell remote handler.



[2] rh_ahb_enable RW 0x1 Enable of the clock for the Ashell remote handler.

The Hardware checks for currently running AHB cycles before switching the clocks.

0x0: DISABLE - -

0x1: ENABLE - -

[1] e2ip_ahb_active R 0x0 Current status of clocks in E2IP modules.

[0] e2ip_ahb_enable RW 0x1 Enable of the clock for the E2IP modules.

The Hardware checks for currently running AHB cycles before switching the clocks.

0x0: DISABLE - -

0x1: ENABLE - -

Table 3-23: PWR_CTRL Register




DISP_CTL

Description: Control of display output.



Table 3-24: DISP_CTL Register



[21] Reserved RW 0x1 -


[19] PAD_EXTREFEN RW 0x0 Bandgap reference enable.

0x0: DISABLE - Use core voltage as refer-ence (for RSDS mode)

0x1: ENABLE - Use bandgap as referece (for LVDS or mini LVDS modes)

[18:16] PAD_CTRLB RW 0x0 Drive mode of differential pads.

0x0: RSDS100 - RSDS mode with 100 Ohm termination resistance

0x2: LVDS100_RSDS50 - LVDS mode with 100 Ohm or RSDS with 50 Ohm termina-tion resistance

0x3: MLVDS_100 - mini LVDS mode with 100 Ohm termination resistance


[12] LVDS_2X_MODE RW 0x0 Use double clock for LVDS mode.

This allows shifting of the ouput by 0.5 UI.

[11] D1_TSIG2_ON_CLKN RW 0x0 Output TSIG2 on CLKN output.

Match timing of TSIG2 with CLKN.

[10] D0_TSIG2_ON_CLKN RW 0x0 Output TSIG2 on CLKN output.

Match timing of TSIG2 with CLKN.

[9:8] DSP_IFC RW 0x0 Display interface mode.

0x0: TTL - select TTL mode

0x2: RSDS - select RSDS mode

0x3: LVDS - select LVDS mode

[7] PHASE_SYNC RW 0x0 Sync phase to incomming clock control from IRIS.

Only needed for LVDS.

[6] CLK_2X RW 0x0 Double the output clock.

Only needed for LVDS.

[5:2] DSP_DIV RW 0xF Display clock divider value.

Legal values from 0x2 to 0xF.

For LVDS set to 0x6.

For correct setup in TTL or RSDS mode see functional description.



[1] DIV_BYPASS RW 0x1 Display clock divider bypass enable.

0x0: DIV - Use clock divider

0x1: BYP - Bypass clock divider

[0] PLL_BYPASS RW 0x1 PLL bypass enable.

0x0: PLL - Use PLL clock

0x1: BYP - Bypass PLL

Table 3-24: DISP_CTL Register




DISP0_PN0_CTL

Description: Control of DISP0 P0/N0 output pad.



Table 3-25: DISP0_PN0_CTL Register



[18] D0_LVDS_SHIFT_0 RW 0x0 shift of LVDS output by 0.5 UI.

0x0: OFF - -

0x1: ON - -

[17:16] D0_0N_CYCLE_SEL RW 0x0 Set cycle shift for DISP0 N0 output (only for TTL mode).

Maximum legal value depends on clock and interface setup.

[15:12] D0_0N_PHASE_SEL RW 0x0 Set phase shift for DISP0 N0 output (only for TTL mode).

Maximum legal value is value of field DSP_DIV.


[9:8] D0_0P_CYCLE_SEL RW 0x0 Set cycle shift for DISP0 P0 output in TTL mode or for DISP0 P0/N0 output in RSDS mode.


[7:4] D0_0P_PHASE_SEL RW 0x0 Set phase shift for DISP0 P0 output in TTL mode or for DISP0 P0/N0 output in RSDS mode.



[2] D0_SWAP_0 RW 0x0 Swap P and N output in differential mode.

0x0: OFF - no swap

0x1: ON - P and N are swapped

[1:0] D0_CLKSEL_0 RW 0x0 Select data or clock for DISP0 P0/N0 out-put.

0x0: DA0 - select DISP0 0 data

0x1: MLVDS - select DISP0 1 data (for MLVDS)

0x2: CLK - select CLK



DISP0_PN1_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap








DISP0_PN2_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap








DISP0_PN3_CTL







[18] D0_LVDS_SHIFT_3 RW 0x0 Shift of LVDS output by 0.5 UI.

0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap








DISP0_PN4_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap








DISP0_PN5_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap








DISP0_PN6_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap








DISP0_PN7_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap








DISP0_PN8_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap








DISP0_PN9_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap








DISP0_PN10_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap


[1:0] D0_CLKSEL_10 RW 0x0 Select data or clock for DISP0 P10/N10 output.






DISP0_PN11_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap








DISP0_PN12_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap







DISP1_PN0_CTL


















0x0: OFF - no swap







DISP1_PN1_CTL


















0x0: OFF - no swap








DISP1_PN2_CTL


















0x0: OFF - no swap








DISP1_PN3_CTL


















0x0: OFF - no swap








DISP1_PN4_CTL


















0x0: OFF - no swap








DISP1_PN5_CTL


















0x0: OFF - no swap








DISP1_PN6_CTL


















0x0: OFF - no swap








DISP1_PN7_CTL


















0x0: OFF - no swap








DISP1_PN8_CTL


















0x0: OFF - no swap








DISP1_PN9_CTL


















0x0: OFF - no swap








DISP1_PN10_CTL


















0x0: OFF - no swap








DISP1_PN11_CTL


















0x0: OFF - no swap








DISP1_PN12_CTL








0x0: OFF - -

0x1: ON - -












0x0: OFF - no swap



0x0: MLVDS - select DISP0 0 data (for MLVDS)





TSIG0_3_CTL

Description: Control of TSIG0-3 output pads.



Table 3-51: TSIG0_3_CTL Register


[31] T3_CLK_INV RW 0x0 Invert clock for TSIG3 output.

For legal clock setup see functional description.

0x0: NOINV - Non inverted

0x1: INV - Inverted

[30] T3_CLK_SEL RW 0x1 Select clock for TSIG3 output.


0x0: VIDS - Use vids_clk

0x1: PLL - Use pll_clk

[29:28] T3_CYCLE_SEL RW 0x0 Set cycle shift for TSIG3 output.


[27:24] T3_PHASE_SEL RW 0x0 Set phase shift for TSIG3 output.





0x1: INV - Inverted












0x1: INV - Inverted














0x1: INV - Inverted













TSIG4_7_CTL









0x1: INV - Inverted












0x1: INV - Inverted












0x1: INV - Inverted














0x1: INV - Inverted













TSIG8_11_CTL









0x1: INV - Inverted












0x1: INV - Inverted












0x1: INV - Inverted














0x1: INV - Inverted













DSPINV_CTL

Description: Control of DSPINV output pad.



Table 3-54: DSPINV_CTL Register



[15] DSP1INV_CLK_INV RW 0x0 Invert clock for Display inversion output.



0x1: INV - Inverted

[14] DSP1INV_CLK_SEL RW 0x1 Select clock for Display inversion output.




[13:12] DSP1INV_CYCLE_SEL RW 0x0 Set cycle shift for Display inversion output.


[11:8] DSP1INV_PHASE_SEL RW 0x0 Set phase shift for Display inversion output.


[7] DSP0INV_CLK_INV RW 0x0 Invert clock for Display inversion output.



0x1: INV - Inverted

[6] DSP0INV_CLK_SEL RW 0x1 Select clock for Display inversion output.




[5:4] DSP0INV_CYCLE_SEL RW 0x0 Set cycle shift for Display inversion output.


[3:0] DSP0INV_PHASE_SEL RW 0x0 Set phase shift for Display inversion output.




ADC3_CTL

Description: Control of ADC3 padMultifunction pad



Table 3-55: ADC3_CTL Register



[9] ADC3_PUD RW 0x1 Pull up disable

0: Enable - Pull up enabled

1: Disable - Pull up disabled

[8] ADC3_PDD RW 0x0 Pull down disable

0: Enable - Pull down enabled

1: Disable - Pull down disabled

[7:6] ADC3_ODR RW 0x0 Drive strength

0: DRV_1mA - Drive strength 1mA




[2:0] adc3_mode RW 0x0 Pinmux select for ADC3 pin

0: GPIO_0 - -

1: ADC_3 - -

2: PPG_12 - -

3: PPG_13B - -

4: HOST_INT - -

5: EIRQ_3 - -



ADC2_CTL



















0: GPIO_1 - -

1: ADC_2 - -

2: PPG_13 - -

3: PPG_12B - -

4: USART_DO - -

5: EIRQ_2 - -



ADC1_CTL



















0: GPIO_2 - -

1: ADC_1 - -

2: PPG_14 - -

3: PPG_15B - -

4: USART_DI - -

5: EIRQ_1 - -



ADC0_CTL



















0: GPIO_3 - -

1: ADC_0 - -

2: PPG_15 - -

3: PPG_14B - -

4: USART_CLK - -

5: EIRQ_0 - -



SMC_1M_0_CTL

Description: Control of SMC_1M_0 pad



Table 3-59: SMC_1M_0_CTL Register



[9] SMC_1M_0_PUD RW 0x1 Pull up disable



[8] SMC_1M_0_PDD RW 0x0 Pull down disable



[7:6] SMC_1M_0_ODR RW 0x0 Drive strength






[2:0] smc_1m_0_mode RW 0x0 Pinmux select for SMC_1M_0 pin

0: GPIO_4 - -

1: SMC_1M_0 - -

2: PPG_0 - -

3: PPG_1B - -

4: AGPIO_0 - -

5: HOST_INT - -



SMC_1P_0_CTL

Description: Control of SMC_1P_0 pad



Table 3-60: SMC_1P_0_CTL Register



[9] SMC_1P_0_PUD RW 0x1 Pull up disable



[8] SMC_1P_0_PDD RW 0x0 Pull down disable



[7:6] SMC_1P_0_ODR RW 0x0 Drive strength






[2:0] smc_1p_0_mode RW 0x0 Pinmux select for SMC_1P_0 pin

0: GPIO_5 - -

1: SMC_1P_0 - -

2: PPG_1 - -

3: PPG_0B - -

4: ADC_24 - -

5: USART_CLK - -



SMC_2M_0_CTL




















0: GPIO_6 - -

1: SMC_2M_0 - -

2: PPG_2 - -

3: PPG_3B - -

4: ADC_25 - -

5: USART_DI - -



SMC_2P_0_CTL




















0: GPIO_7 - -

1: SMC_2P_0 - -

2: PPG_3 - -

3: PPG_2B - -

4: AGPIO_1 - -

5: USART_DO - -



SMC_1M_1_CTL




















0: GPIO_8 - -

1: SMC_1M_1 - -

2: PPG_4 - -

3: PPG_5B - -

4: SG_SGA - -

5: I2S_MCLK - -



SMC_1P_1_CTL




















0: GPIO_9 - -

1: SMC_1P_1 - -

2: PPG_5 - -

3: PPG_4B - -

4: ADC_26 - -

5: I2S_WS - -



SMC_2M_1_CTL




















0: GPIO_10 - -

1: SMC_2M_1 - -

2: PPG_6 - -

3: PPG_7B - -

4: ADC_27 - -

5: I2S_SD - -



SMC_2P_1_CTL




















0: GPIO_11 - -

1: SMC_2P_1 - -

2: PPG_7 - -

3: PPG_6B - -

4: SG_SGO - -

5: I2S_SCLK - -



SMC_1M_2_CTL




















0: GPIO_12 - -

1: SMC_1M_2 - -

2: PPG_8 - -

3: PPG_9B - -

4: EIRQ_7 - -

5: MII_RXD0 - -



SMC_1P_2_CTL




















0: GPIO_13 - -

1: SMC_1P_2 - -

2: PPG_9 - -

3: PPG_8B - -

4: ADC_16 - -

5: MII_RXD1 - -



SMC_2M_2_CTL




















0: GPIO_14 - -

1: SMC_2M_2 - -

2: PPG_10 - -

3: PPG_11B - -

4: ADC_17 - -

5: MII_RXD2 - -



SMC_2P_2_CTL




















0: GPIO_15 - -

1: SMC_2P_2 - -

2: PPG_11 - -

3: PPG_10B - -

4: EIRQ_6 - -

5: MII_RXD3 - -



SMC_1M_3_CTL




















0: GPIO_16 - -

1: SMC_1M_3 - -

2: PPG_12 - -

3: PPG_13B - -

4: EIRQ_5 - -

5: MII_RX_DV - -



SMC_1P_3_CTL




















0: GPIO_17 - -

1: SMC_1P_3 - -

2: PPG_13 - -

3: PPG_12B - -

4: ADC_18 - -

5: MII_RX_CLK - -



SMC_2M_3_CTL




















0: GPIO_18 - -

1: SMC_2M_3 - -

2: PPG_14 - -

3: PPG_15B - -

4: ADC_19 - -

5: MII_TXD0 - -



SMC_2P_3_CTL




















0: GPIO_19 - -

1: SMC_2P_3 - -

2: PPG_15 - -

3: PPG_14B - -

4: EIRQ_4 - -

5: MII_TXD1 - -



SMC_1M_4_CTL




















0: GPIO_20 - -

1: SMC_1M_4 - -

2: PPG_0 - -

3: PPG_1B - -

4: EIRQ_3 - -

5: MII_TXD2 - -



SMC_1P_4_CTL




















0: GPIO_21 - -

1: SMC_1P_4 - -

2: PPG_1 - -

3: PPG_0B - -

4: ADC_20 - -

5: MII_TXD3 - -



SMC_2M_4_CTL




















0: GPIO_22 - -

1: SMC_2M_4 - -

2: PPG_2 - -

3: PPG_3B - -

4: ADC_21 - -

5: MII_TX_EN - -



SMC_2P_4_CTL




















0: GPIO_23 - -

1: SMC_2P_4 - -

2: PPG_3 - -

3: PPG_2B - -

4: EIRQ_2 - -

5: MII_TX_CLK - -



SMC_1M_5_CTL




















0: GPIO_24 - -

1: SMC_1M_5 - -

2: PPG_4 - -

3: PPG_5B - -

4: EIRQ_1 - -

5: MII_RX_ER - -



SMC_1P_5_CTL




















0: GPIO_25 - -

1: SMC_1P_5 - -

2: PPG_5 - -

3: PPG_4B - -

4: ADC_22 - -

5: MII_COL - -



SMC_2M_5_CTL




















0: GPIO_26 - -

1: SMC_2M_5 - -

2: PPG_6 - -

3: PPG_7B - -

4: ADC_23 - -

5: MII_CRS - -



SMC_2P_5_CTL




















0: GPIO_27 - -

1: SMC_2P_5 - -

2: PPG_7 - -

3: PPG_6B - -

4: EIRQ_0 - -



CFG5_CTL

Description: Control of CFG5 pad



Table 3-83: CFG5_CTL Register



[9] CFG5_PUD RW 0x1 Pull up disable



[8] CFG5_PDD RW 0x0 Pull down disable




[2:0] cfg5_mode RW 0x0 Pinmux select for CFG5 pin

0: CFG_5 - -

1: GPIO_28 - -

2: PPG_0 - -

3: SPI_CS2 - -

4: SPI0_SDI - -

5: SPI_SDIO3 - -



CFG4_CTL















0: CFG_4 - -

1: GPIO_29 - -

2: PPG_1 - -

3: SPI_CS1 - -

4: SPI0_SDO - -

5: SPI_SDIO2 - -



CFG3_CTL















0: CFG_3 - -

1: GPIO_30 - -

2: PPG_2 - -

3: PPG_3B - -

4: SPI0_SCLK - -

5: SPI_CS0 - -



CFG2_CTL















0: CFG_2 - -

1: GPIO_31 - -

2: PPG_3 - -

3: PPG_2B - -

4: SPI1_SDI - -

5: SPI_SDIO1 - -



CFG1_CTL















0: CFG_1 - -

1: GPIO_32 - -

2: PPG_4 - -

3: EIRQ_0 - -

4: SPI1_SDO - -

5: SPI_SDIO0 - -



CFG0_CTL















0: CFG_0 - -

1: GPIO_33 - -

2: PPG_5 - -

3: EIRQ_1 - -

4: SPI1_SCLK - -

5: SPI_SCLK - -



DISP1_0_CTL

Description: Control of DISP1_0 pad



Table 3-89: DISP1_0_CTL Register



[27] DISP1_0_PUD_N RW 0x1 Pull up disable



[26] DISP1_0_PDD_N RW 0x0 Pull down disable



[25:24] DISP1_0_ODR_N RW 0x0 Drive strength in TTL mode






[19] DISP1_0_PUD_P RW 0x1 Pull up disable



[18] DISP1_0_PDD_P RW 0x0 Pull down disable



[17:16] DISP1_0_ODR_P RW 0x0 Drive strength in TTL mode






[13] DISP1_0_HCN RW 0x0 Half cycle delay for N pad.

0: DISABLE - no delay

1: ENABLE - delayed by half clock cycle

[12] DISP1_0_HCP RW 0x0 Half cycle delay for P pad.






[8] DISP1_0_IOMODE RW 0x0 IO mode selection (only valid when display output is selected)

0: TTL - TTL mode

1: RSDS_LVDS - differential mode


[6:4] disp1p0_mode RW 0x0 Pinmux select for DISP1P0 pin

0: GPIO_35 - -

1: DISP1_0P - -

2: PPG_7 - -

3: PPG_6B - -

4: I2S_SD - -

5: FLSH_SDIO0 - -


[2:0] disp1n0_mode RW 0x0 Pinmux select for DISP1N0 pin

0: GPIO_34 - -

1: DISP1_0N - -

2: PPG_6 - -

3: PPG_7B - -

4: I2S_SCLK - -

5: FLSH_SDIO1 - -





DISP1_1_CTL









































0: TTL - TTL mode




0: GPIO_37 - -

1: DISP1_1P - -

2: PPG_9 - -

3: PPG_8B - -

4: I2S_MCLK - -

5: MII_COL - -



0: GPIO_36 - -

1: DISP1_1N - -

2: PPG_8 - -

3: PPG_9B - -

4: I2S_WS - -

5: FLSH_SCLK - -





DISP1_2_CTL









































0: TTL - TTL mode




0: GPIO_39 - -

1: DISP1_2P - -

2: PPG_11 - -

3: PPG_10B - -

4: FLSH_CS3 - -

5: MII_RXD1 - -



0: GPIO_38 - -

1: DISP1_2N - -

2: PPG_10 - -

3: PPG_11B - -

5: MII_RXD0 - -





DISP1_3_CTL









































0: TTL - TTL mode




0: GPIO_41 - -

1: DISP1_3P - -

2: PPG_13 - -

3: PPG_12B - -

4: FLSH_CS1 - -

5: MII_RXD3 - -



0: GPIO_40 - -

1: DISP1_3N - -

2: PPG_12 - -

3: PPG_13B - -

4: FLSH_CS2 - -

5: MII_RXD2 - -





DISP1_4_CTL









































0: TTL - TTL mode




0: GPIO_43 - -

1: DISP1_4P - -

2: PPG_15 - -

3: PPG_14B - -

4: FLSH_SCLK - -

5: MII_RX_CLK - -



0: GPIO_42 - -

1: DISP1_4N - -

2: PPG_14 - -

3: PPG_15B - -

4: FLSH_CS0 - -

5: MII_RX_DV - -





DISP1_5_CTL









































0: TTL - TTL mode




0: GPIO_45 - -

1: DISP1_5P - -

2: PPG_1 - -

3: SPI_CS3 - -

4: FLSH_SDIO1 - -

5: MII_TXD1 - -



0: GPIO_44 - -

1: DISP1_5N - -

2: PPG_0 - -

3: PPG_1B - -

4: FLSH_SDIO0 - -

5: MII_TXD0 - -





DISP1_6_CTL



Instance no 0: 0x000002A0






































0: TTL - TTL mode




0: GPIO_47 - -

1: DISP1_6P - -

2: PPG_3 - -

3: PPG_2B - -

4: FLSH_SDIO3 - -

5: MII_TXD3 - -



0: GPIO_46 - -

1: DISP1_6N - -

2: PPG_2 - -

3: PPG_3B - -

4: FLSH_SDIO2 - -

5: MII_TXD2 - -





DISP1_7_CTL









































0: TTL - TTL mode




0: GPIO_49 - -

1: DISP1_7P - -

2: PPG_5 - -

3: PPG_4B - -

4: SPI3_SDO - -

5: MII_TX_CLK - -



0: GPIO_48 - -

1: DISP1_7N - -

2: PPG_4 - -

3: PPG_5B - -

4: SPI3_SCLK - -

5: MII_TX_EN - -





DISP1_8_CTL









































0: TTL - TTL mode




0: GPIO_51 - -

1: DISP1_8P - -

2: PPG_7 - -

3: PPG_6B - -

4: SPI2_SDI - -

5: MII_CRS - -



0: GPIO_50 - -

1: DISP1_8N - -

2: PPG_6 - -

3: PPG_7B - -

4: SPI3_SDI - -

5: MII_RX_ER - -





DISP1_9_CTL



Instance no 0: 0x000002AC






































0: TTL - TTL mode




0: GPIO_53 - -

1: DISP1_9P - -

2: PPG_9 - -

3: PPG_8B - -

4: SPI2_SCLK - -

5: SPI_CS1 - -



0: GPIO_52 - -

1: DISP1_9N - -

2: PPG_8 - -

3: PPG_9B - -

4: SPI2_SDO - -

5: SPI_CS2 - -





DISP1_10_CTL



Instance no 0: 0x000002B0






































0: TTL - TTL mode




0: GPIO_55 - -

1: DISP1_10P - -

2: PPG_11 - -

3: PPG_10B - -

4: SPI1_SDO - -

5: SPI_SCLK - -



0: GPIO_54 - -

1: DISP1_10N - -

2: PPG_10 - -

3: PPG_11B - -

4: SPI1_SCLK - -

5: SPI_CS0 - -





DISP1_11_CTL









































0: TTL - TTL mode




0: GPIO_57 - -

1: DISP1_11P - -

2: PPG_13 - -

3: PPG_12B - -

4: SPI0_SDI - -

5: SPI_SDIO1 - -



0: GPIO_56 - -

1: DISP1_11N - -

2: PPG_12 - -

3: PPG_13B - -

4: SPI1_SDI - -

5: SPI_SDIO0 - -





DISP1_12_CTL









































0: TTL - TTL mode




0: GPIO_59 - -

1: DISP1_12P - -

2: PPG_15 - -

3: PPG_14B - -

4: SPI0_SCLK - -

5: SPI_SDIO3 - -



0: GPIO_58 - -

1: DISP1_12N - -

2: PPG_14 - -

3: PPG_15B - -

4: SPI0_SDO - -

5: SPI_SDIO2 - -





TSIG11_CTL

Description: Control of TSIG11 pad


Instance no 0: 0x000002BC

Table 3-102: TSIG11_CTL Register



[9] TSIG11_PUD RW 0x1 Pull up disable



[8] TSIG11_PDD RW 0x0 Pull down disable



[7:6] TSIG11_ODR RW 0x0 Drive strength






[2:0] tsig11_mode RW 0x0 Pinmux select for TSIG11 pin

0: GPIO_60 - -

1: TSIG_11 - -

2: PPG_0 - -

3: PPG_1B - -

4: DISP1_INV - -

5: SPI3_SCLK - -



TSIG10_CTL



Instance no 0: 0x000002C0

















0: GPIO_61 - -

1: TSIG_10 - -

2: PPG_1 - -

3: PPG_0B - -

4: EIRQ_2 - -

5: SPI3_SDO - -



TSIG9_CTL




















0: GPIO_62 - -

1: TSIG_9 - -

2: PPG_2 - -

3: PPG_3B - -

4: EIRQ_3 - -

5: SPI3_SDI - -



TSIG8_CTL




















0: GPIO_63 - -

1: TSIG_8 - -

2: PPG_3 - -

3: PPG_2B - -

4: FLSH_CS3 - -

5: SPI2_SCLK - -



TSIG7_CTL



Instance no 0: 0x000002CC

















0: GPIO_64 - -

1: TSIG_7 - -

2: PPG_4 - -

3: PPG_5B - -

4: FLSH_CS2 - -

5: SPI2_SDO - -



TSIG6_CTL



Instance no 0: 0x000002D0

















0: GPIO_65 - -

1: TSIG_6 - -

2: PPG_5 - -

3: PPG_4B - -

4: FLSH_CS1 - -

5: SPI2_SDI - -



TSIG5_CTL




















0: GPIO_66 - -

1: TSIG_5 - -

2: PPG_6 - -

3: PPG_7B - -

4: FLSH_CS0 - -

5: EIRQ_6 - -



TSIG4_CTL




















0: GPIO_67 - -

1: TSIG_4 - -

2: PPG_7 - -

3: PPG_6B - -

4: FLSH_SCLK - -

5: EIRQ_7 - -



TSIG3_CTL



Instance no 0: 0x000002DC

















0: GPIO_68 - -

1: TSIG_3 - -

2: PPG_8 - -

3: PPG_9B - -

4: FLSH_SDIO0 - -

5: DISP0_INV - -



TSIG2_CTL



Instance no 0: 0x000002E0

















0: GPIO_69 - -

1: TSIG_2 - -

2: PPG_9 - -

3: PPG_8B - -

4: FLSH_SDIO1 - -



TSIG1_CTL




















0: GPIO_70 - -

1: TSIG_1 - -

2: PPG_10 - -

3: PPG_11B - -

4: FLSH_SDIO2 - -

5: EIRQ_4 - -



TSIG0_CTL




















0: GPIO_71 - -

1: TSIG_0 - -

2: PPG_11 - -

3: PPG_10B - -

4: FLSH_SDIO3 - -

5: EIRQ_5 - -



DISP0_0_CTL



Instance no 0: 0x000002EC






































0: TTL - TTL mode




0: GPIO_73 - -

1: DISP0_0P - -

2: PPG_13 - -

3: PPG_12B - -

4: I2S_SD - -



0: GPIO_72 - -

1: DISP0_0N - -

2: PPG_12 - -

3: PPG_13B - -

4: I2S_SCLK - -





DISP0_1_CTL



Instance no 0: 0x000002F0






































0: TTL - TTL mode




0: GPIO_75 - -

1: DISP0_1P - -

2: PPG_15 - -

3: PPG_14B - -

4: I2S_MCLK - -



0: GPIO_74 - -

1: DISP0_1N - -

2: PPG_14 - -

3: PPG_15B - -

4: I2S_WS - -





DISP0_2_CTL









































0: TTL - TTL mode




0: GPIO_77 - -

1: DISP0_2P - -

2: PPG_1 - -

3: PPG_0B - -



0: GPIO_76 - -

1: DISP0_2N - -

2: PPG_0 - -

3: PPG_1B - -





DISP0_3_CTL









































0: TTL - TTL mode



[4] disp0p3_mode RW 0x0 Pinmux select for DISP0P3 pin

0: GPIO_79 - -

1: DISP0_3P - -


[0] disp0n3_mode RW 0x0 Pinmux select for DISP0N3 pin

0: GPIO_78 - -

1: DISP0_3N - -





DISP0_4_CTL



Instance no 0: 0x000002FC






































0: TTL - TTL mode




0: GPIO_81 - -

1: DISP0_4P - -



0: GPIO_80 - -

1: DISP0_4N - -





DISP0_5_CTL









































0: TTL - TTL mode




0: GPIO_83 - -

1: DISP0_5P - -



0: GPIO_82 - -

1: DISP0_5N - -





DISP0_6_CTL









































0: TTL - TTL mode




0: GPIO_85 - -

1: DISP0_6P - -



0: GPIO_84 - -

1: DISP0_6N - -





DISP0_7_CTL









































0: TTL - TTL mode




0: GPIO_87 - -

1: DISP0_7P - -



0: GPIO_86 - -

1: DISP0_7N - -





DISP0_8_CTL









































0: TTL - TTL mode




0: GPIO_89 - -

1: DISP0_8P - -



0: GPIO_88 - -

1: DISP0_8N - -





DISP0_9_CTL









































0: TTL - TTL mode




0: GPIO_91 - -

1: DISP0_9P - -



0: GPIO_90 - -

1: DISP0_9N - -





DISP0_10_CTL









































0: TTL - TTL mode




0: GPIO_93 - -

1: DISP0_10P - -



0: GPIO_92 - -

1: DISP0_10N - -





DISP0_11_CTL









































0: TTL - TTL mode




0: GPIO_95 - -

1: DISP0_11P - -



0: GPIO_94 - -

1: DISP0_11N - -





DISP0_12_CTL









































0: TTL - TTL mode




0: GPIO_97 - -

1: DISP0_12P - -



0: GPIO_96 - -

1: DISP0_12N - -





SG_SGO_CTL

Description: Control of SG_SGO padMultifunction pad



Table 3-127: SG_SGO_CTL Register



[9] SG_SGO_PUD RW 0x1 Pull up disable



[8] SG_SGO_PDD RW 0x0 Pull down disable



[7:6] SG_SGO_ODR RW 0x0 Drive strength





[2:0] sg_sgo_mode RW 0x0 Pinmux select for SG_SGO pin

0: GPIO_98 - -

1: SG_SGO - -

2: PPG_0 - -

3: PPG_1B - -

4: ADC_15 - -



SG_SGA_CTL

Description: Control of SG_SGA padMultifunction pad



Table 3-128: SG_SGA_CTL Register



[9] SG_SGA_PUD RW 0x1 Pull up disable



[8] SG_SGA_PDD RW 0x0 Pull down disable



[7:6] SG_SGA_ODR RW 0x0 Drive strength





[2:0] sg_sga_mode RW 0x0 Pinmux select for SG_SGA pin

0: GPIO_99 - -

1: SG_SGA - -

2: PPG_1 - -

3: PPG_0B - -

4: ADC_14 - -



I2C0_SDA_CTL

Description: Control of I2C0_SDA padMultifunction pad with I2C mode



Table 3-129: I2C0_SDA_CTL Register



[9] I2C0_SDA_PUD RW 0x0 Pull up disable



[8] I2C0_SDA_PDD RW 0x1 Pull down disable



[7:6] I2C0_SDA_ODR RW 0x0 Drive strength





[2:0] i2c0_sda_mode RW 0x0 Pinmux select for I2C0_SDA pin

0: GPIO_100 - -

1: I2C0_SDA - -

2: PPG_2 - -

3: PPG_3B - -

4: ADC_13 - -



I2C0_SCL_CTL

Description: Control of I2C0_SCL padMultifunction pad with I2C mode



Table 3-130: I2C0_SCL_CTL Register



[9] I2C0_SCL_PUD RW 0x0 Pull up disable



[8] I2C0_SCL_PDD RW 0x1 Pull down disable



[7:6] I2C0_SCL_ODR RW 0x0 Drive strength





[2:0] i2c0_scl_mode RW 0x0 Pinmux select for I2C0_SCL pin

0: GPIO_101 - -

1: I2C0_SCL - -

2: PPG_3 - -

3: PPG_2B - -

4: ADC_12 - -



I2C1_SDA_CTL

Description: Control of I2C1_SDA padMultifunction pad with I2C mode



Table 3-131: I2C1_SDA_CTL Register



[9] I2C1_SDA_PUD RW 0x0 Pull up disable



[8] I2C1_SDA_PDD RW 0x1 Pull down disable



[7:6] I2C1_SDA_ODR RW 0x0 Drive strength





[2:0] i2c1_sda_mode RW 0x0 Pinmux select for I2C1_SDA pin

0: GPIO_102 - -

1: I2C1_SDA - -

2: PPG_4 - -

3: PPG_5B - -

4: ADC_11 - -

5: SG_SGO - -



I2C1_SCL_CTL

Description: Control of I2C1_SCL padMultifunction pad with I2C mode



Table 3-132: I2C1_SCL_CTL Register



[9] I2C1_SCL_PUD RW 0x0 Pull up disable



[8] I2C1_SCL_PDD RW 0x1 Pull down disable



[7:6] I2C1_SCL_ODR RW 0x0 Drive strength





[2:0] i2c1_scl_mode RW 0x0 Pinmux select for I2C1_SCL pin

0: GPIO_103 - -

1: I2C1_SCL - -

2: PPG_5 - -

3: PPG_4B - -

4: ADC_10 - -

5: SG_SGA - -



ADC9_CTL



















0: GPIO_104 - -

1: ADC_9 - -

2: PPG_6 - -

3: PPG_7B - -

4: AGPIO_1 - -



ADC8_CTL



















0: GPIO_105 - -

1: ADC_8 - -

2: PPG_7 - -

3: PPG_6B - -

4: AGPIO_0 - -



ADC7_CTL



















0: GPIO_106 - -

1: ADC_7 - -

2: PPG_8 - -

3: PPG_9B - -

4: I2S_SCLK - -

5: EIRQ_7 - -



ADC6_CTL



















0: GPIO_107 - -

1: ADC_6 - -

2: PPG_9 - -

3: PPG_8B - -

4: I2S_SD - -

5: EIRQ_6 - -



ADC5_CTL



















0: GPIO_108 - -

1: ADC_5 - -

2: PPG_10 - -

3: PPG_11B - -

4: I2S_WS - -

5: EIRQ_5 - -



ADC4_CTL



















0: GPIO_109 - -

1: ADC_4 - -

2: PPG_11 - -

3: PPG_10B - -

4: I2S_MCLK - -

5: EIRQ_4 - -



MODULE_IRQ_STS

Description: Interrupt status for submodule



Table 3-139: MODULE_IRQ_STS Register



[20] INTERCONNECT_STS R 0x0 Status for interrupts of INTERCONNECT sub module

[19] PRGCRC_STS R 0x0 Status for interrupts of PRGCRC sub mod-ule

[18] FSPI_STS R 0x0 Status for interrupts of FSPI sub module

[17] DMAC_STS R 0x0 Status for interrupts of DMAC sub module

[16] GC_STS R 0x0 Status for interrupts of GC sub module

[15] CMDSEQ_STS R 0x0 Status for interrupts of CMDSEQ sub mod-ule

[14] IRIS_STS R 0x0 Status for interrupts of IRIS sub module

[13] ESPI_STS R 0x0 Status for interrupts of ESPI sub module

[12] EIRQ_STS R 0x0 Status for interrupts of EIRQ sub module

[11] ADC_STS R 0x0 Status for interrupts of ADC sub module

[10] SGE_STS R 0x0 Status for interrupts of SGE sub module

[9] I2C1_STS R 0x0 Status for interrupts of I2C1 sub module

[8] I2C0_STS R 0x0 Status for interrupts of I2C0 sub module

[7] PPG_STS R 0x0 Status for interrupts of PPG sub module

[6] LIN_STS R 0x0 Status for interrupts of LIN sub module

[5] RLT_STS R 0x0 Status for interrupts of RLT sub module

[4] CFF_FIFO_STS R 0x0 Status for interrupts of CFF_FIFO sub module

[3] CFF_CTRL_STS R 0x0 Status for interrupts of CFF_CTRL sub module

[2] E2IP_STS R 0x0 Status for interrupts of E2IP sub module

[1] ASHELL_RH_STS R 0x0 Status for interrupts of ASHELL_RH sub module

[0] APIX_STS R 0x0 Status for interrupts of APIX sub module



APIX_CLR

Description: Interrupt clear for APIX interrupts



Table 3-140: APIX_CLR Register



[10] APIX_PHY_RES_CLR R0W1

0x0 Clear for APIX_PHY_RES interrupt status

(APIX PHY reset request)

[9] APIX_PHY_ARS_CLR R0W1

0x0 Clear for APIX_PHY_ARS interrupt status

(APIX PHY recalibration request)




APIX_SET

Description: Interrupt set for APIX interrupts



Table 3-141: APIX_SET Register



[10] APIX_PHY_RES_SET R0W1

0x0 Set for APIX_PHY_RES interrupt status (for debugging)


[9] APIX_PHY_ARS_SET R0W1

0x0 Set for APIX_PHY_ARS interrupt status (for debugging)





APIX_STS

Description: Interrupt status for APIX interrupts



Table 3-142: APIX_STS Register



[14] APIX_HDCP_ERR_STS R 0x0 Status for APIX_HDCP_ERR interrupt

(APIX HDCP error)

[13] APIX_HDCP_FUNC_STS

R 0x0 Status for APIX_HDCP_FUNC interrupt

(APIX HDCP functional)

[12] APIX_PHY_NC2_STS R 0x0 Status for APIX_PHY_NC2 interrupt

(APIX PHY interface (not connected))

[11] APIX_PHY_NC1_STS R 0x0 Status for APIX_PHY_NC1 interrupt


[10] APIX_PHY_RES_STS R 0x0 Status for APIX_PHY_RES interrupt


[9] APIX_PHY_ARS_STS R 0x0 Status for APIX_PHY_ARS interrupt


[8] APIX_PIX_FATAL_STS R 0x0 Status for APIX_PIX_FATAL interrupt

(APIX Ashell Pixel fatal error)

[7] APIX_PIX_ERR_STS R 0x0 Status for APIX_PIX_ERR interrupt

(APIX Ashell Pixel error)

[6] APIX_ASHELL_FATAL_STS

R 0x0 Status for APIX_ASHELL_FATAL interrupt

(APIX Ashell fatal error)

[5] APIX_ASHELL_ERR_STS

R 0x0 Status for APIX_ASHELL_ERR interrupt

(APIX Ashell error)

[4] APIX_ASHELL_FUNC_STS

R 0x0 Status for APIX_ASHELL_FUNC interrupt

(APIX Ashell functional)

[3] APIX_ASHELL_REQ_STS

R 0x0 Status for APIX_ASHELL_REQ interrupt

(APIX Ashell request)

[2] APIX_LINK_FATAL_STS R 0x0 Status for APIX_LINK_FATAL interrupt

(APIX link fatal error)

[1] APIX_LINK_ERR_STS R 0x0 Status for APIX_LINK_ERR interrupt

(APIX link error)

[0] APIX_LINK_FUNC_STS R 0x0 Status for APIX_LINK_FUNC interrupt

(APIX link functional)



ASHELL_RH_CLR

Description: Interrupt clear for ASHELL_RH interrupts



Table 3-143: ASHELL_RH_CLR Register



[11] ARH_T_TOUT_CLR R0W1

0x0 Clear for ARH_T_TOUT interrupt status

(Ashell Remote Handler TCTRL timeout (loss of message))

[10] ARH_T_OVL_CLR R0W1

0x0 Clear for ARH_T_OVL interrupt status

(Ashell Remote Handler TX-fifo overflow (loss of message))

[9] ARH_T_THRESH_CLR R0W1

0x0 Clear for ARH_T_THRESH interrupt status

(Ashell Remote Handler TX-fifo threshold reached)

[8] ARH_R_OVL_CLR R0W1

0x0 Clear for ARH_R_OVL interrupt status

(Ashell Remote Handler RX-fifo overflow (loss of message))

[7] ARH_R_THRESH_CLR R0W1

0x0 Clear for ARH_R_THRESH interrupt status

(Ashell Remote Handler RX-fifo threshold reached)

[6] ARH_WRLOCK_CLR R0W1

0x0 Clear for ARH_WRLOCK interrupt status

(Ashell Remote Handler RX interrupt, receive write message while locked)

[5] ARH_WERR_CLR R0W1

0x0 Clear for ARH_WERR interrupt status

(Ashell Remote Handler AHB bus write bus error interrupt)

[4] ARH_RERR_CLR R0W1

0x0 Clear for ARH_RERR interrupt status

(Ashell Remote Handler AHB bus read bus error interrupt)

[3] ARH_PUSH_ACK_CLR R0W1

0x0 Clear for ARH_PUSH_ACK interrupt status

(Ashell Remote Handler Push message request done interrupt)

[2] ARH_PUSH_REQ_CLR R0W1

0x0 Clear for ARH_PUSH_REQ interrupt status

(Ashell Remote Handler Push message request interrupt)

[1] ARH_MAIL_ACK_CLR R0W1

0x0 Clear for ARH_MAIL_ACK interrupt status

(Ashell Remote Handler Mailbox request done interrupt)

[0] ARH_MAIL_REQ_CLR R0W1

0x0 Clear for ARH_MAIL_REQ interrupt status

(Ashell Remote Handler Mailbox request interrupt)



ASHELL_RH_SET

Description: Interrupt set for ASHELL_RH interrupts



Table 3-144: ASHELL_RH_SET Register



[11] ARH_T_TOUT_SET R0W1

0x0 Set for ARH_T_TOUT interrupt status (for debugging)


[10] ARH_T_OVL_SET R0W1

0x0 Set for ARH_T_OVL interrupt status (for debugging)


[9] ARH_T_THRESH_SET R0W1

0x0 Set for ARH_T_THRESH interrupt status (for debugging)


[8] ARH_R_OVL_SET R0W1

0x0 Set for ARH_R_OVL interrupt status (for debugging)


[7] ARH_R_THRESH_SET R0W1

0x0 Set for ARH_R_THRESH interrupt status (for debugging)


[6] ARH_WRLOCK_SET R0W1

0x0 Set for ARH_WRLOCK interrupt status (for debugging)


[5] ARH_WERR_SET R0W1

0x0 Set for ARH_WERR interrupt status (for debugging)


[4] ARH_RERR_SET R0W1

0x0 Set for ARH_RERR interrupt status (for debugging)


[3] ARH_PUSH_ACK_SET R0W1

0x0 Set for ARH_PUSH_ACK interrupt status (for debugging)


[2] ARH_PUSH_REQ_SET R0W1

0x0 Set for ARH_PUSH_REQ interrupt status (for debugging)




[1] ARH_MAIL_ACK_SET R0W1

0x0 Set for ARH_MAIL_ACK interrupt status (for debugging)


[0] ARH_MAIL_REQ_SET R0W1

0x0 Set for ARH_MAIL_REQ interrupt status (for debugging)


Table 3-144: ASHELL_RH_SET Register




ASHELL_RH_STS

Description: Interrupt status for ASHELL_RH interrupts



Table 3-145: ASHELL_RH_STS Register



[11] ARH_T_TOUT_STS R 0x0 Status for ARH_T_TOUT interrupt


[10] ARH_T_OVL_STS R 0x0 Status for ARH_T_OVL interrupt


[9] ARH_T_THRESH_STS R 0x0 Status for ARH_T_THRESH interrupt


[8] ARH_R_OVL_STS R 0x0 Status for ARH_R_OVL interrupt


[7] ARH_R_THRESH_STS R 0x0 Status for ARH_R_THRESH interrupt


[6] ARH_WRLOCK_STS R 0x0 Status for ARH_WRLOCK interrupt


[5] ARH_WERR_STS R 0x0 Status for ARH_WERR interrupt


[4] ARH_RERR_STS R 0x0 Status for ARH_RERR interrupt


[3] ARH_PUSH_ACK_STS R 0x0 Status for ARH_PUSH_ACK interrupt


[2] ARH_PUSH_REQ_STS R 0x0 Status for ARH_PUSH_REQ interrupt


[1] ARH_MAIL_ACK_STS R 0x0 Status for ARH_MAIL_ACK interrupt


[0] ARH_MAIL_REQ_STS R 0x0 Status for ARH_MAIL_REQ interrupt




E2IP_CLR

Description: Interrupt clear for E2IP interrupts



Table 3-146: E2IP_CLR Register



[16] E2IP_MAC1_UDT_CLR R0W1

0x0 Clear for E2IP_MAC1_UDT interrupt status

(E2IP MAC address of Host 1 updated)

[15] E2IP_MAC0_UDT_CLR R0W1

0x0 Clear for E2IP_MAC0_UDT interrupt status


[14] E2IP_RX_OVWR_CLR R0W1

0x0 Clear for E2IP_RX_OVWR interrupt status

(E2IP RX frame dropped, while not already processed)

[13] E2IP_TX_DROP_CLR R0W1

0x0 Clear for E2IP_TX_DROP interrupt status

(E2IP TX frame dropped)

[12] E2IP_RX_DROP_CLR R0W1

0x0 Clear for E2IP_RX_DROP interrupt status

(E2IP RX frame dropped)

[11] ERH_T_TOUT_CLR R0W1

0x0 Clear for ERH_T_TOUT interrupt status

(E2IP Remote Handler TCTRL timeout (loss of message))

[10] ERH_T_OVL_CLR R0W1

0x0 Clear for ERH_T_OVL interrupt status

(E2IP Remote Handler TX-fifo overflow (loss of message))

[9] ERH_T_THRESH_CLR R0W1

0x0 Clear for ERH_T_THRESH interrupt status

(E2IP Remote Handler TX-fifo threshold reached)

[8] ERH_R_OVL_CLR R0W1

0x0 Clear for ERH_R_OVL interrupt status

(E2IP Remote Handler RX-fifo overflow (loss of message))

[7] ERH_R_THRESH_CLR R0W1

0x0 Clear for ERH_R_THRESH interrupt status

(E2IP Remote Handler RX-fifo threshold reached)

[6] ERH_WRLOCK_CLR R0W1

0x0 Clear for ERH_WRLOCK interrupt status

(E2IP Remote Handler RX interrupt, receive write message while locked)

[5] ERH_WERR_CLR R0W1

0x0 Clear for ERH_WERR interrupt status

(E2IP Remote Handler AHB bus write bus error interrupt)

[4] ERH_RERR_CLR R0W1

0x0 Clear for ERH_RERR interrupt status

(E2IP Remote Handler AHB bus read bus error interrupt)



[3] ERH_PUSH_ACK_CLR R0W1

0x0 Clear for ERH_PUSH_ACK interrupt status

(E2IP Remote Handler Push message request done interrupt)

[2] ERH_PUSH_REQ_CLR R0W1

0x0 Clear for ERH_PUSH_REQ interrupt status

(E2IP Remote Handler Push message request interrupt)

[1] ERH_MAIL_ACK_CLR R0W1

0x0 Clear for ERH_MAIL_ACK interrupt status

(E2IP Remote Handler Mailbox request done interrupt)

[0] ERH_MAIL_REQ_CLR R0W1

0x0 Clear for ERH_MAIL_REQ interrupt status

(E2IP Remote Handler Mailbox request interrupt)

Table 3-146: E2IP_CLR Register




E2IP_SET

Description: Interrupt set for E2IP interrupts



Table 3-147: E2IP_SET Register



[16] E2IP_MAC1_UDT_SET R0W1

0x0 Set for E2IP_MAC1_UDT interrupt status (for debugging)


[15] E2IP_MAC0_UDT_SET R0W1

0x0 Set for E2IP_MAC0_UDT interrupt status (for debugging)


[14] E2IP_RX_OVWR_SET R0W1

0x0 Set for E2IP_RX_OVWR interrupt status (for debugging)


[13] E2IP_TX_DROP_SET R0W1

0x0 Set for E2IP_TX_DROP interrupt status (for debugging)


[12] E2IP_RX_DROP_SET R0W1

0x0 Set for E2IP_RX_DROP interrupt status (for debugging)


[11] ERH_T_TOUT_SET R0W1

0x0 Set for ERH_T_TOUT interrupt status (for debugging)


[10] ERH_T_OVL_SET R0W1

0x0 Set for ERH_T_OVL interrupt status (for debugging)


[9] ERH_T_THRESH_SET R0W1

0x0 Set for ERH_T_THRESH interrupt status (for debugging)


[8] ERH_R_OVL_SET R0W1

0x0 Set for ERH_R_OVL interrupt status (for debugging)


[7] ERH_R_THRESH_SET R0W1

0x0 Set for ERH_R_THRESH interrupt status (for debugging)




[6] ERH_WRLOCK_SET R0W1

0x0 Set for ERH_WRLOCK interrupt status (for debugging)


[5] ERH_WERR_SET R0W1

0x0 Set for ERH_WERR interrupt status (for debugging)


[4] ERH_RERR_SET R0W1

0x0 Set for ERH_RERR interrupt status (for debugging)


[3] ERH_PUSH_ACK_SET R0W1

0x0 Set for ERH_PUSH_ACK interrupt status (for debugging)


[2] ERH_PUSH_REQ_SET R0W1

0x0 Set for ERH_PUSH_REQ interrupt status (for debugging)


[1] ERH_MAIL_ACK_SET R0W1

0x0 Set for ERH_MAIL_ACK interrupt status (for debugging)


[0] ERH_MAIL_REQ_SET R0W1

0x0 Set for ERH_MAIL_REQ interrupt status (for debugging)


Table 3-147: E2IP_SET Register




E2IP_STS

Description: Interrupt status for E2IP interrupts



Table 3-148: E2IP_STS Register



[16] E2IP_MAC1_UDT_STS R 0x0 Status for E2IP_MAC1_UDT interrupt


[15] E2IP_MAC0_UDT_STS R 0x0 Status for E2IP_MAC0_UDT interrupt


[14] E2IP_RX_OVWR_STS R 0x0 Status for E2IP_RX_OVWR interrupt


[13] E2IP_TX_DROP_STS R 0x0 Status for E2IP_TX_DROP interrupt


[12] E2IP_RX_DROP_STS R 0x0 Status for E2IP_RX_DROP interrupt


[11] ERH_T_TOUT_STS R 0x0 Status for ERH_T_TOUT interrupt


[10] ERH_T_OVL_STS R 0x0 Status for ERH_T_OVL interrupt


[9] ERH_T_THRESH_STS R 0x0 Status for ERH_T_THRESH interrupt


[8] ERH_R_OVL_STS R 0x0 Status for ERH_R_OVL interrupt


[7] ERH_R_THRESH_STS R 0x0 Status for ERH_R_THRESH interrupt


[6] ERH_WRLOCK_STS R 0x0 Status for ERH_WRLOCK interrupt


[5] ERH_WERR_STS R 0x0 Status for ERH_WERR interrupt


[4] ERH_RERR_STS R 0x0 Status for ERH_RERR interrupt




[3] ERH_PUSH_ACK_STS R 0x0 Status for ERH_PUSH_ACK interrupt


[2] ERH_PUSH_REQ_STS R 0x0 Status for ERH_PUSH_REQ interrupt


[1] ERH_MAIL_ACK_STS R 0x0 Status for ERH_MAIL_ACK interrupt


[0] ERH_MAIL_REQ_STS R 0x0 Status for ERH_MAIL_REQ interrupt


Table 3-148: E2IP_STS Register




CFF_CTRL_CLR

Description: Interrupt clear for CFF_CTRL interrupts



Table 3-149: CFF_CTRL_CLR Register



[9] CFF_DW0_CLR R0W1

0x0 Clear for CFF_DW0 interrupt status

(Config FIFO Data written channel 0 inter-rupt)






















[1] CFF_RERR_CLR R0W1

0x0 Clear for CFF_RERR interrupt status

(Config FIFO AHB Master received ERROR response interrupt)

[0] CFF_ALL_CLR R0W1

0x0 Clear for CFF_ALL interrupt status

(Combination of all Config FIFO interrupts)



CFF_CTRL_SET

Description: Interrupt set for CFF_CTRL interrupts



Table 3-150: CFF_CTRL_SET Register



[9] CFF_DW0_SET R0W1

0x0 Set for CFF_DW0 interrupt status (for debugging)























[1] CFF_RERR_SET R0W1

0x0 Set for CFF_RERR interrupt status (for debugging)


[0] CFF_ALL_SET R0W1

0x0 Set for CFF_ALL interrupt status (for debugging)




CFF_CTRL_STS

Description: Interrupt status for CFF_CTRL interrupts



Table 3-151: CFF_CTRL_STS Register



[9] CFF_DW0_STS R 0x0 Status for CFF_DW0 interrupt
















[1] CFF_RERR_STS R 0x0 Status for CFF_RERR interrupt


[0] CFF_ALL_STS R 0x0 Status for CFF_ALL interrupt




CFF_FIFO_CLR

Description: Interrupt clear for CFF_FIFO interrupts



Table 3-152: CFF_FIFO_CLR Register


[31] CFF_LTHD0_CLR R0W1

0x0 Clear for CFF_LTHD0 interrupt status

(Config FIFO Lower Threshold channel 0 interrupt)

[30] CFF_UTHD0_CLR R0W1

0x0 Clear for CFF_UTHD0 interrupt status

(Config FIFO Upper Threshold channel 0 interrupt)

[29] CFF_OFLW0_CLR R0W1

0x0 Clear for CFF_OFLW0 interrupt status

(Config FIFO Overflow channel 0 interrupt)

[28] CFF_UFLW0_CLR R0W1

0x0 Clear for CFF_UFLW0 interrupt status

(Config FIFO Underflow channel 0 inter-rupt)






























CFF_FIFO_SET

Description: Interrupt set for CFF_FIFO interrupts



Table 3-153: CFF_FIFO_SET Register


[31] CFF_LTHD0_SET R0W1

0x0 Set for CFF_LTHD0 interrupt status (for debugging)


[30] CFF_UTHD0_SET R0W1

0x0 Set for CFF_UTHD0 interrupt status (for debugging)


[29] CFF_OFLW0_SET R0W1

0x0 Set for CFF_OFLW0 interrupt status (for debugging)


[28] CFF_UFLW0_SET R0W1

0x0 Set for CFF_UFLW0 interrupt status (for debugging)






















CFF_FIFO_STS

Description: Interrupt status for CFF_FIFO interrupts



Table 3-154: CFF_FIFO_STS Register


[31] CFF_LTHD0_STS R 0x0 Status for CFF_LTHD0 interrupt


[30] CFF_UTHD0_STS R 0x0 Status for CFF_UTHD0 interrupt


[29] CFF_OFLW0_STS R 0x0 Status for CFF_OFLW0 interrupt


[28] CFF_UFLW0_STS R 0x0 Status for CFF_UFLW0 interrupt






















RLT_STS

Description: Interrupt status for RLT interrupts



Table 3-155: RLT_STS Register



[15] RLT15_STS R 0x0 Status for RLT15 interrupt

(Reload timer 15 interrupt)

































LIN_STS

Description: Interrupt status for LIN interrupts



Table 3-156: LIN_STS Register



[2] LIN_E_STS R 0x0 Status for LIN_E interrupt

(LIN Error interrupt)

[1] LIN_T_STS R 0x0 Status for LIN_T interrupt

(LIN Transmission interrupt)

[0] LIN_R_STS R 0x0 Status for LIN_R interrupt

(LIN Reception interrupt)



PPG_STS

Description: Interrupt status for PPG interrupts



Table 3-157: PPG_STS Register



[15] PPG33_STS R 0x0 Status for PPG33 interrupt

(PPG / PWM module 3 interrupt 3)

































I2C0_STS

Description: Interrupt status for I2C0 interrupts



Table 3-158: I2C0_STS Register



[1] I2C0_ERIRQ_STS R 0x0 Status for I2C0_ERIRQ interrupt

(I2C0 Error interrupt)

[0] I2C0_IRQ_STS R 0x0 Status for I2C0_IRQ interrupt

(I2C0 Operational interrupt)



I2C1_STS

Description: Interrupt status for I2C1 interrupts



Table 3-159: I2C1_STS Register



[1] I2C1_ERIRQ_STS R 0x0 Status for I2C1_ERIRQ interrupt


[0] I2C1_IRQ_STS R 0x0 Status for I2C1_IRQ interrupt




SGE_CLR

Description: Interrupt clear for SGE interrupts



Table 3-160: SGE_CLR Register



[1] SGE_RLD_CLR R0W1

0x0 Clear for SGE_RLD interrupt status

(Sound generator register reload interrupt)




SGE_SET

Description: Interrupt set for SGE interrupts



Table 3-161: SGE_SET Register



[1] SGE_RLD_SET R0W1

0x0 Set for SGE_RLD interrupt status (for debugging)





SGE_STS

Description: Interrupt status for SGE interrupts



Table 3-162: SGE_STS Register



[1] SGE_RLD_STS R 0x0 Status for SGE_RLD interrupt


[0] SGE_IRQ_STS R 0x0 Status for SGE_IRQ interrupt

(Sound generator interrupt)



ADC_STS

Description: Interrupt status for ADC interrupts



Table 3-163: ADC_STS Register



[3] ADC_ADPIRQ_STS R 0x0 Status for ADC_ADPIRQ interrupt

(ADC pulse detection interrupt)

[2] ADC_RCOIRQ_STS R 0x0 Status for ADC_RCOIRQ interrupt

(ADC Range comparator interrupt)

[1] ADC2_IRQ_STS R 0x0 Status for ADC2_IRQ interrupt

(ADC Scan end interrupt)

[0] ADC_IRQ_STS R 0x0 Status for ADC_IRQ interrupt

(ADC Conversion end interrupt)



EIRQ_STS

Description: Interrupt status for EIRQ interrupts



Table 3-164: EIRQ_STS Register



[7] EIRQ_7_STS R 0x0 Status for EIRQ_7 interrupt

(external IRQ pin 7 interrupt)

















ESPI_STS

Description: Interrupt status for ESPI interrupts



Table 3-165: ESPI_STS Register



[2] ESPI_FAULT_STS R 0x0 Status for ESPI_FAULT interrupt

(External device SPI Fault interrupt)

[1] ESPI_TX_STS R 0x0 Status for ESPI_TX interrupt

(External device SPI Transmission inter-rupt)

[0] ESPI_RX_STS R 0x0 Status for ESPI_RX interrupt

(External device SPI Reception interrupt)



IRIS_CLR

Description: Interrupt clear for IRIS interrupts



Table 3-166: IRIS_CLR Register


[31] IRS_FC_SYNCERR_CLR

R0W1

0x0 Clear for IRS_FC_SYNCERR interrupt sta-tus

(Iris-MVL frame capture synchronization loss)

[30] IRS_FC_SYNC_CLR R0W1

0x0 Clear for IRS_FC_SYNC interrupt status

(Iris-MVL frame capture synchronization stable)

[29] IRS_FG_SYNCERR_S_CLR

R0W1

0x0 Clear for IRS_FG_SYNCERR_S interrupt status

(Iris-MVL frame generator synchronization loss (secondary input))

[28] IRS_FG_SYNC_S_CLR R0W1

0x0 Clear for IRS_FG_SYNC_S interrupt status

(Iris-MVL frame generator synchronization stable (secondary input))

[27] IRS_FG_SYNCERR_P_CLR

R0W1

0x0 Clear for IRS_FG_SYNCERR_P interrupt status

(Iris-MVL frame generator synchronization loss (primary input))

[26] IRS_FG_SYNC_P_CLR R0W1

0x0 Clear for IRS_FG_SYNC_P interrupt status

(Iris-MVL frame generator synchronization stable (primary input))

[25] IRS_SIG3_ERR_CLR R0W1

0x0 Clear for IRS_SIG3_ERR interrupt status

(Iris-MVL signature unit 3 signature error)

[24] IRS_SIG3_RDY_CLR R0W1

0x0 Clear for IRS_SIG3_RDY interrupt status

(Iris-MVL signature unit 3 measurement complete)

[23] IRS_SIG3_SL_CLR R0W1

0x0 Clear for IRS_SIG3_SL interrupt status

(Iris-MVL signature unit 3 shadow loaded)






























[13] IRS_FG_SL_S_CLR R0W1

0x0 Clear for IRS_FG_SL_S interrupt status

(Iris-MVL frame generator shadow register loaded (secondary input))

[12] IRS_FG_SL_P_CLR R0W1

0x0 Clear for IRS_FG_SL_P interrupt status

(Iris-MVL frame generator shadow register loaded (primary input))

[11] IRS_FG_P3_CLR R0W1

0x0 Clear for IRS_FG_P3 interrupt status

(Iris-MVL frame generator programmable interrupt 3)










[7] IRS_DE_SC_CLR R0W1

0x0 Clear for IRS_DE_SC interrupt status

(Iris-MVL display engine sequence com-plete)

[6] IRS_DE_SL_CLR R0W1

0x0 Clear for IRS_DE_SL interrupt status

(Iris-MVL display engine top shadow loaded)

[5] IRS_LB1_SL_CLR R0W1

0x0 Clear for IRS_LB1_SL interrupt status

(Iris-MVL layerblend 1 shadow loaded)

[4] IRS_LB0_SL_CLR R0W1

0x0 Clear for IRS_LB0_SL interrupt status

(Iris-MVL layerblend 0 shadow register loaded)





[3] IRS_PE_FC1_CLR R0W1

0x0 Clear for IRS_PE_FC1 interrupt status

(Iris-MVL pixel engine frame complete (extdst 1))

[2] IRS_PE_FC0_CLR R0W1

0x0 Clear for IRS_PE_FC0 interrupt status


[1] IRS_PE_SC1_CLR R0W1

0x0 Clear for IRS_PE_SC1 interrupt status

(Iris-MVL pixel engine sequence complete (synchronizer 1))

[0] IRS_PE_SC0_CLR R0W1

0x0 Clear for IRS_PE_SC0 interrupt status






IRIS_SET

Description: Interrupt set for IRIS interrupts



Table 3-167: IRIS_SET Register


[31] IRS_FC_SYNCERR_SET

R0W1

0x0 Set for IRS_FC_SYNCERR interrupt status (for debugging)


[30] IRS_FC_SYNC_SET R0W1

0x0 Set for IRS_FC_SYNC interrupt status (for debugging)


[29] IRS_FG_SYNCERR_S_SET

R0W1

0x0 Set for IRS_FG_SYNCERR_S interrupt status (for debugging)


[28] IRS_FG_SYNC_S_SET R0W1

0x0 Set for IRS_FG_SYNC_S interrupt status (for debugging)


[27] IRS_FG_SYNCERR_P_SET

R0W1

0x0 Set for IRS_FG_SYNCERR_P interrupt status (for debugging)


[26] IRS_FG_SYNC_P_SET R0W1

0x0 Set for IRS_FG_SYNC_P interrupt status (for debugging)


[25] IRS_SIG3_ERR_SET R0W1

0x0 Set for IRS_SIG3_ERR interrupt status (for debugging)


[24] IRS_SIG3_RDY_SET R0W1

0x0 Set for IRS_SIG3_RDY interrupt status (for debugging)


[23] IRS_SIG3_SL_SET R0W1

0x0 Set for IRS_SIG3_SL interrupt status (for debugging)































[13] IRS_FG_SL_S_SET R0W1

0x0 Set for IRS_FG_SL_S interrupt status (for debugging)


[12] IRS_FG_SL_P_SET R0W1

0x0 Set for IRS_FG_SL_P interrupt status (for debugging)


[11] IRS_FG_P3_SET R0W1

0x0 Set for IRS_FG_P3 interrupt status (for debugging)















[7] IRS_DE_SC_SET R0W1

0x0 Set for IRS_DE_SC interrupt status (for debugging)


[6] IRS_DE_SL_SET R0W1

0x0 Set for IRS_DE_SL interrupt status (for debugging)


[5] IRS_LB1_SL_SET R0W1

0x0 Set for IRS_LB1_SL interrupt status (for debugging)


[4] IRS_LB0_SL_SET R0W1

0x0 Set for IRS_LB0_SL interrupt status (for debugging)


[3] IRS_PE_FC1_SET R0W1

0x0 Set for IRS_PE_FC1 interrupt status (for debugging)


[2] IRS_PE_FC0_SET R0W1

0x0 Set for IRS_PE_FC0 interrupt status (for debugging)


[1] IRS_PE_SC1_SET R0W1

0x0 Set for IRS_PE_SC1 interrupt status (for debugging)


[0] IRS_PE_SC0_SET R0W1

0x0 Set for IRS_PE_SC0 interrupt status (for debugging)






IRIS_STS

Description: Interrupt status for IRIS interrupts



Table 3-168: IRIS_STS Register


[31] IRS_FC_SYNCERR_STS

R 0x0 Status for IRS_FC_SYNCERR interrupt


[30] IRS_FC_SYNC_STS R 0x0 Status for IRS_FC_SYNC interrupt


[29] IRS_FG_SYNCERR_S_STS

R 0x0 Status for IRS_FG_SYNCERR_S interrupt


[28] IRS_FG_SYNC_S_STS R 0x0 Status for IRS_FG_SYNC_S interrupt


[27] IRS_FG_SYNCERR_P_STS

R 0x0 Status for IRS_FG_SYNCERR_P interrupt


[26] IRS_FG_SYNC_P_STS R 0x0 Status for IRS_FG_SYNC_P interrupt


[25] IRS_SIG3_ERR_STS R 0x0 Status for IRS_SIG3_ERR interrupt


[24] IRS_SIG3_RDY_STS R 0x0 Status for IRS_SIG3_RDY interrupt


[23] IRS_SIG3_SL_STS R 0x0 Status for IRS_SIG3_SL interrupt






















[13] IRS_FG_SL_S_STS R 0x0 Status for IRS_FG_SL_S interrupt


[12] IRS_FG_SL_P_STS R 0x0 Status for IRS_FG_SL_P interrupt


[11] IRS_FG_P3_STS R 0x0 Status for IRS_FG_P3 interrupt








[7] IRS_DE_SC_STS R 0x0 Status for IRS_DE_SC interrupt


[6] IRS_DE_SL_STS R 0x0 Status for IRS_DE_SL interrupt


[5] IRS_LB1_SL_STS R 0x0 Status for IRS_LB1_SL interrupt


[4] IRS_LB0_SL_STS R 0x0 Status for IRS_LB0_SL interrupt


[3] IRS_PE_FC1_STS R 0x0 Status for IRS_PE_FC1 interrupt






[2] IRS_PE_FC0_STS R 0x0 Status for IRS_PE_FC0 interrupt


[1] IRS_PE_SC1_STS R 0x0 Status for IRS_PE_SC1 interrupt


[0] IRS_PE_SC0_STS R 0x0 Status for IRS_PE_SC0 interrupt






CMDSEQ_CLR

Description: Interrupt clear for CMDSEQ interrupts



Table 3-169: CMDSEQ_CLR Register



[7] CMDSEQ_FULL_CLR R0W1

0x0 Clear for CMDSEQ_FULL interrupt status

(Command Sequencer command buffer fifo full interrupt)

[6] CMDSEQ_EMPTY_CLR R0W1

0x0 Clear for CMDSEQ_EMPTY interrupt sta-tus

(Command Sequencer command buffer fifo empty interrupt)

[5] CMDSEQ_HALT_CLR R0W1

0x0 Clear for CMDSEQ_HALT interrupt status

(Command Sequencer halt interrupt (core is in halt state))

[4] CMDSEQ_ERROR_CLR R0W1

0x0 Clear for CMDSEQ_ERROR interrupt sta-tus

(Command Sequencer error interrupt (error on illegal instruction))

[3] CMDSEQ_HWM_CLR R0W1

0x0 Clear for CMDSEQ_HWM interrupt status

(Command Sequencer command buffer high watermark interrupt (counter reaches high water mark))

[2] CMDSEQ_LWM_CLR R0W1

0x0 Clear for CMDSEQ_LWM interrupt status

(Command Sequencer command buffer low watermark interrupt (counter reaches low water mark))

[1] CMDSEQ_SWINT_CLR R0W1

0x0 Clear for CMDSEQ_SWINT interrupt status

(Command Sequencer software interrupt)

[0] CMDSEQ_WDG_CLR R0W1

0x0 Clear for CMDSEQ_WDG interrupt status

(Command Sequencer watchdog interrupt (watchdog status))



CMDSEQ_SET

Description: Interrupt set for CMDSEQ interrupts



Table 3-170: CMDSEQ_SET Register



[7] CMDSEQ_FULL_SET R0W1

0x0 Set for CMDSEQ_FULL interrupt status (for debugging)


[6] CMDSEQ_EMPTY_SET R0W1

0x0 Set for CMDSEQ_EMPTY interrupt status (for debugging)


[5] CMDSEQ_HALT_SET R0W1

0x0 Set for CMDSEQ_HALT interrupt status (for debugging)


[4] CMDSEQ_ERROR_SET R0W1

0x0 Set for CMDSEQ_ERROR interrupt status (for debugging)


[3] CMDSEQ_HWM_SET R0W1

0x0 Set for CMDSEQ_HWM interrupt status (for debugging)


[2] CMDSEQ_LWM_SET R0W1

0x0 Set for CMDSEQ_LWM interrupt status (for debugging)


[1] CMDSEQ_SWINT_SET R0W1

0x0 Set for CMDSEQ_SWINT interrupt status (for debugging)


[0] CMDSEQ_WDG_SET R0W1

0x0 Set for CMDSEQ_WDG interrupt status (for debugging)




CMDSEQ_STS

Description: Interrupt status for CMDSEQ interrupts



Table 3-171: CMDSEQ_STS Register



[7] CMDSEQ_FULL_STS R 0x0 Status for CMDSEQ_FULL interrupt


[6] CMDSEQ_EMPTY_STS R 0x0 Status for CMDSEQ_EMPTY interrupt


[5] CMDSEQ_HALT_STS R 0x0 Status for CMDSEQ_HALT interrupt


[4] CMDSEQ_ERROR_STS R 0x0 Status for CMDSEQ_ERROR interrupt


[3] CMDSEQ_HWM_STS R 0x0 Status for CMDSEQ_HWM interrupt


[2] CMDSEQ_LWM_STS R 0x0 Status for CMDSEQ_LWM interrupt


[1] CMDSEQ_SWINT_STS R 0x0 Status for CMDSEQ_SWINT interrupt


[0] CMDSEQ_WDG_STS R 0x0 Status for CMDSEQ_WDG interrupt




GC_CLR

Description: Interrupt clear for GC interrupts



Table 3-172: GC_CLR Register



[5] LVD_H_F_CLR R0W1

0x0 Clear for LVD_H_F interrupt status

(Low voltage detection core voltage high threshold comparator going low interrupt)

[4] LVD_H_R_CLR R0W1

0x0 Clear for LVD_H_R interrupt status

(Low voltage detection core voltage high threshold comparator going high interrupt)

[3] LVD_L_F_CLR R0W1

0x0 Clear for LVD_L_F interrupt status

(Low voltage detection core voltage low threshold comparator going low interrupt)

[2] LVD_L_R_CLR R0W1

0x0 Clear for LVD_L_R interrupt status

(Low voltage detection core voltage low threshold comparator going high interrupt)

[1] GC_WDG_CLR R0W1

0x0 Clear for GC_WDG interrupt status

(System Watchdog interrupt)

[0] GC_ALV_CLR R0W1

0x0 Clear for GC_ALV interrupt status

(Global Control Alive sender IRQ)



GC_SET

Description: Interrupt set for GC interrupts



Table 3-173: GC_SET Register



[5] LVD_H_F_SET R0W1

0x0 Set for LVD_H_F interrupt status (for debugging)


[4] LVD_H_R_SET R0W1

0x0 Set for LVD_H_R interrupt status (for debugging)


[3] LVD_L_F_SET R0W1

0x0 Set for LVD_L_F interrupt status (for debugging)


[2] LVD_L_R_SET R0W1

0x0 Set for LVD_L_R interrupt status (for debugging)


[1] GC_WDG_SET R0W1

0x0 Set for GC_WDG interrupt status (for debugging)


[0] GC_ALV_SET R0W1

0x0 Set for GC_ALV interrupt status (for debug-ging)




GC_STS

Description: Interrupt status for GC interrupts



Table 3-174: GC_STS Register



[8] FLSH_STS R 0x0 Status for FLSH interrupt

(Flash interface interrupt (ready, hang or single bit error))

[7] HIFC_STS R 0x0 Status for HIFC interrupt

(Host interface AHB bus error interrupt)

[6] PANIC_SWITCH_STS R 0x0 Status for PANIC_SWITCH interrupt

(Panic switch was asserted)

[5] LVD_H_F_STS R 0x0 Status for LVD_H_F interrupt


[4] LVD_H_R_STS R 0x0 Status for LVD_H_R interrupt


[3] LVD_L_F_STS R 0x0 Status for LVD_L_F interrupt


[2] LVD_L_R_STS R 0x0 Status for LVD_L_R interrupt


[1] GC_WDG_STS R 0x0 Status for GC_WDG interrupt


[0] GC_ALV_STS R 0x0 Status for GC_ALV interrupt




DMAC_STS

Description: Interrupt status for DMAC interrupts



Table 3-175: DMAC_STS Register



[5] DMAC_EIRQ1_STS R 0x0 Status for DMAC_EIRQ1 interrupt

(DMA Controller error DMA channel 1)

[4] DMAC_EIRQ0_STS R 0x0 Status for DMAC_EIRQ0 interrupt


[3] DMAC_EIRQ_STS R 0x0 Status for DMAC_EIRQ interrupt

(DMA Controller single ORed output of all the EIRQx generated from each Channel)

[2] DMAC_DIRQ1_STS R 0x0 Status for DMAC_DIRQ1 interrupt

(DMA Controller end of DMA transfer chan-nel 1)

[1] DMAC_DIRQ0_STS R 0x0 Status for DMAC_DIRQ0 interrupt


[0] DMAC_DIRQ_STS R 0x0 Status for DMAC_DIRQ interrupt

(DMA Controller single ORed output of all the DIRQx generated from each Channel)



FSPI_STS

Description: Interrupt status for FSPI interrupts



Table 3-176: FSPI_STS Register



[2] FSPI_FAULT_STS R 0x0 Status for FSPI_FAULT interrupt

(External Flash SPI Fault interrupt)

[1] FSPI_TX_STS R 0x0 Status for FSPI_TX interrupt

(External Flash SPI Transmission interrupt)

[0] FSPI_RX_STS R 0x0 Status for FSPI_RX interrupt

(External Flash SPI Reception interrupt)



PRGCRC_STS

Description: Interrupt status for PRGCRC interrupts



Table 3-177: PRGCRC_STS Register



[0] PRGCRC_IRQ_STS R 0x0 Status for PRGCRC_IRQ interrupt

(Programmable CRC completion interrupt)



INTERCONNECT_CLR

Description: Interrupt clear for INTERCONNECT interrupts



Table 3-178: INTERCONNECT_CLR Register



[7] IFLASH_TCBUSERR_CLR

R0W1

0x0 Clear for IFLASH_TCBUSERR interrupt status

(Internal Flash interface signals TC inter-face error)

[6] IFLASH_BUSERR_CLR R0W1

0x0 Clear for IFLASH_BUSERR interrupt status

(Internal Flash interface signals AHB inter-face error)

[5] PRGCRC_BUSERR_CLR

R0W1

0x0 Clear for PRGCRC_BUSERR interrupt sta-tus

(Programmable CRC unit signals AHB interface error)

[4] FSPI_BUSERR_CLR R0W1

0x0 Clear for FSPI_BUSERR interrupt status

(External Flash SPI unit signals AHB inter-face error)

[3] ESPI_BUSERR_CLR R0W1

0x0 Clear for ESPI_BUSERR interrupt status

(External device SPI unit signals AHB inter-face error)

[2] EXTIRQ_BUSERR_CLR R0W1

0x0 Clear for EXTIRQ_BUSERR interrupt sta-tus

(External IRQ unit signals AHB interface error)




INTERCONNECT_SET

Description: Interrupt set for INTERCONNECT interrupts



Table 3-179: INTERCONNECT_SET Register



[7] IFLASH_TCBUSERR_SET

R0W1

0x0 Set for IFLASH_TCBUSERR interrupt sta-tus (for debugging)


[6] IFLASH_BUSERR_SET R0W1

0x0 Set for IFLASH_BUSERR interrupt status (for debugging)


[5] PRGCRC_BUSERR_SET

R0W1

0x0 Set for PRGCRC_BUSERR interrupt status (for debugging)


[4] FSPI_BUSERR_SET R0W1

0x0 Set for FSPI_BUSERR interrupt status (for debugging)


[3] ESPI_BUSERR_SET R0W1

0x0 Set for ESPI_BUSERR interrupt status (for debugging)


[2] EXTIRQ_BUSERR_SET R0W1

0x0 Set for EXTIRQ_BUSERR interrupt status (for debugging)





INTERCONNECT_STS

Description: Interrupt status for INTERCONNECT interrupts



Table 3-180: INTERCONNECT_STS Register



[7] IFLASH_TCBUSERR_STS

R 0x0 Status for IFLASH_TCBUSERR interrupt


[6] IFLASH_BUSERR_STS R 0x0 Status for IFLASH_BUSERR interrupt


[5] PRGCRC_BUSERR_STS

R 0x0 Status for PRGCRC_BUSERR interrupt


[4] FSPI_BUSERR_STS R 0x0 Status for FSPI_BUSERR interrupt


[3] ESPI_BUSERR_STS R 0x0 Status for ESPI_BUSERR interrupt


[2] EXTIRQ_BUSERR_STS R 0x0 Status for EXTIRQ_BUSERR interrupt


[1] ERBUS_BUSERR_STS R 0x0 Status for ERBUS_BUSERR interrupt

(eRBUS interconnect error (signaled by eRBUS error collection unit))

[0] RBUS_BUSERR_STS R 0x0 Status for RBUS_BUSERR interrupt

(RBUS interconnect error (signaled by RBUS error collection unit))



IRQ_CMDSEQ_SEL0

Description: Interrupt select for command sequencer



Detailed description of bit field cmdseq_irqsel0 values:

0: APIX_LINK_FUNC - APIX link functional

1: APIX_LINK_ERR - APIX link error

2: APIX_LINK_FATAL - APIX link fatal error

3: APIX_ASHELL_REQ - APIX Ashell request

4: APIX_ASHELL_FUNC - APIX Ashell functional

5: APIX_ASHELL_ERR - APIX Ashell error

6: APIX_ASHELL_FATAL - APIX Ashell fatal error

7: APIX_PIX_ERR - APIX Ashell Pixel error

8: APIX_PIX_FATAL - APIX Ashell Pixel fatal error

9: APIX_PHY_ARS - APIX PHY recalibration request

10: APIX_PHY_RES - APIX PHY reset request

11: APIX_PHY_NC1 - APIX PHY interface (not connected)


13: APIX_HDCP_FUNC - APIX HDCP functional

14: APIX_HDCP_ERR - APIX HDCP error

15: ARH_MAIL_REQ - Ashell Remote Handler Mailbox request interrupt

16: ARH_MAIL_ACK - Ashell Remote Handler Mailbox request done interrupt

17: ARH_PUSH_REQ - Ashell Remote Handler Push message request interrupt

18: ARH_PUSH_ACK - Ashell Remote Handler Push message request done interrupt

19: ARH_RERR - Ashell Remote Handler AHB bus read bus error interrupt

20: ARH_WERR - Ashell Remote Handler AHB bus write bus error interrupt

21: ARH_WRLOCK - Ashell Remote Handler RX interrupt, receive write message while locked

22: ARH_R_THRESH - Ashell Remote Handler RX-fifo threshold reached

23: ARH_R_OVL - Ashell Remote Handler RX-fifo overflow (loss of message)

Table 3-181: IRQ_CMDSEQ_SEL0 Register


[31:24] cmdseq_irqsel3 RW 0xFF Select interrupt for command sequencer event input 3






24: ARH_T_THRESH - Ashell Remote Handler TX-fifo threshold reached

25: ARH_T_OVL - Ashell Remote Handler TX-fifo overflow (loss of message)

26: ARH_T_TOUT - Ashell Remote Handler TCTRL timeout (loss of message)

27: ERH_MAIL_REQ - E2IP Remote Handler Mailbox request interrupt

28: ERH_MAIL_ACK - E2IP Remote Handler Mailbox request done interrupt

29: ERH_PUSH_REQ - E2IP Remote Handler Push message request interrupt

30: ERH_PUSH_ACK - E2IP Remote Handler Push message request done interrupt

31: ERH_RERR - E2IP Remote Handler AHB bus read bus error interrupt

32: ERH_WERR - E2IP Remote Handler AHB bus write bus error interrupt

33: ERH_WRLOCK - E2IP Remote Handler RX interrupt, receive write message while locked

34: ERH_R_THRESH - E2IP Remote Handler RX-fifo threshold reached

35: ERH_R_OVL - E2IP Remote Handler RX-fifo overflow (loss of message)

36: ERH_T_THRESH - E2IP Remote Handler TX-fifo threshold reached

37: ERH_T_OVL - E2IP Remote Handler TX-fifo overflow (loss of message)

38: ERH_T_TOUT - E2IP Remote Handler TCTRL timeout (loss of message)

39: E2IP_RX_DROP - E2IP RX frame dropped

40: E2IP_TX_DROP - E2IP TX frame dropped

41: E2IP_RX_OVWR - E2IP RX frame dropped, while not already processed

42: E2IP_MAC0_UDT - E2IP MAC address of Host 0 updated


44: CFF_ALL - Combination of all Config FIFO interrupts

45: CFF_RERR - Config FIFO AHB Master received ERROR response interrupt

46: CFF_DW7 - Config FIFO Data written channel 7 interrupt








54: CFF_UFLW7 - Config FIFO Underflow channel 7 interrupt

55: CFF_OFLW7 - Config FIFO Overflow channel 7 interrupt

56: CFF_UTHD7 - Config FIFO Upper Threshold channel 7 interrupt

57: CFF_LTHD7 - Config FIFO Lower Threshold channel 7 interrupt































86: RLT0 - Reload timer 0 interrupt


















102: LIN_R - LIN Reception interrupt

103: LIN_T - LIN Transmission interrupt

104: LIN_E - LIN Error interrupt

105: PPG00 - PPG / PWM module 0 interrupt 0
















121: I2C0_IRQ - I2C0 Operational interrupt

122: I2C0_ERIRQ - I2C0 Error interrupt



125: SGE_IRQ - Sound generator interrupt

126: SGE_RLD - Sound generator register reload interrupt

127: ADC_IRQ - ADC Conversion end interrupt

128: ADC2_IRQ - ADC Scan end interrupt

129: ADC_RCOIRQ - ADC Range comparator interrupt

130: ADC_ADPIRQ - ADC pulse detection interrupt

131: EIRQ_0 - external IRQ pin 0 interrupt








139: ESPI_RX - External device SPI Reception interrupt

140: ESPI_TX - External device SPI Transmission interrupt



141: ESPI_FAULT - External device SPI Fault interrupt

142: IRS_PE_SC0 - Iris-MVL pixel engine sequence complete (synchronizer 0)


144: IRS_PE_FC0 - Iris-MVL pixel engine frame complete (extdst 0)


146: IRS_LB0_SL - Iris-MVL layerblend 0 shadow register loaded

147: IRS_LB1_SL - Iris-MVL layerblend 1 shadow loaded

148: IRS_DE_SL - Iris-MVL display engine top shadow loaded

149: IRS_DE_SC - Iris-MVL display engine sequence complete

150: IRS_FG_P0 - Iris-MVL frame generator programmable interrupt 0




154: IRS_FG_SL_P - Iris-MVL frame generator shadow register loaded (primary input)

155: IRS_FG_SL_S - Iris-MVL frame generator shadow register loaded (secondary input)

156: IRS_SIG0_SL - Iris-MVL signature unit 0 shadow loaded

157: IRS_SIG0_RDY - Iris-MVL signature unit 0 measurement complete

158: IRS_SIG0_ERR - Iris-MVL signature unit 0 signature error










168: IRS_FG_SYNC_P - Iris-MVL frame generator synchronization stable (primary input)

169: IRS_FG_SYNCERR_P - Iris-MVL frame generator synchronization loss (primary input)

170: IRS_FG_SYNC_S - Iris-MVL frame generator synchronization stable (secondary input)

171: IRS_FG_SYNCERR_S - Iris-MVL frame generator synchronization loss (secondary input)

172: IRS_FC_SYNC - Iris-MVL frame capture synchronization stable

173: IRS_FC_SYNCERR - Iris-MVL frame capture synchronization loss

174: CMDSEQ_WDG - Command Sequencer watchdog interrupt (watchdog status)

175: CMDSEQ_SWINT - Command Sequencer software interrupt

176: CMDSEQ_LWM - Command Sequencer command buffer low watermark interrupt (counterreaches low water mark)

177: CMDSEQ_HWM - Command Sequencer command buffer high watermark interrupt (counterreaches high water mark)

178: CMDSEQ_ERROR - Command Sequencer error interrupt (error on illegal instruction)



179: CMDSEQ_HALT - Command Sequencer halt interrupt (core is in halt state)

180: CMDSEQ_EMPTY - Command Sequencer command buffer fifo empty interrupt

181: CMDSEQ_FULL - Command Sequencer command buffer fifo full interrupt

182: GC_ALV - Global Control Alive sender IRQ

183: GC_WDG - System Watchdog interrupt

184: LVD_L_R - Low voltage detection core voltage low threshold comparator going high interrupt

185: LVD_L_F - Low voltage detection core voltage low threshold comparator going low interrupt

186: LVD_H_R - Low voltage detection core voltage high threshold comparator going high interrupt

187: LVD_H_F - Low voltage detection core voltage high threshold comparator going low interrupt

188: PANIC_SWITCH - Panic switch was asserted

189: HIFC - Host interface AHB bus error interrupt

190: FLSH - Flash interface interrupt (ready, hang or single bit error)

191: DMAC_DIRQ - DMA Controller single ORed output of all the DIRQx generated from each Channel

192: DMAC_DIRQ0 - DMA Controller end of DMA transfer channel 0


194: DMAC_EIRQ - DMA Controller single ORed output of all the EIRQx generated from each Channel

195: DMAC_EIRQ0 - DMA Controller error DMA channel 0


197: FSPI_RX - External Flash SPI Reception interrupt

198: FSPI_TX - External Flash SPI Transmission interrupt

199: FSPI_FAULT - External Flash SPI Fault interrupt

200: PRGCRC_IRQ - Programmable CRC completion interrupt

201: RBUS_BUSERR - RBUS interconnect error (signaled by RBUS error collection unit)

202: ERBUS_BUSERR - eRBUS interconnect error (signaled by eRBUS error collection unit)

203: EXTIRQ_BUSERR - External IRQ unit signals AHB interface error

204: ESPI_BUSERR - External device SPI unit signals AHB interface error

205: FSPI_BUSERR - External Flash SPI unit signals AHB interface error

206: PRGCRC_BUSERR - Programmable CRC unit signals AHB interface error

207: IFLASH_BUSERR - Internal Flash interface signals AHB interface error

208: IFLASH_TCBUSERR - Internal Flash interface signals TC interface error

255: DISABLE - disable interrupt to command sequencer










IRQ_CMDSEQ_SEL1

Description: Interrupt select for command sequencer




























Table 3-182: IRQ_CMDSEQ_SEL1 Register








CFF_TRG_SEL0

Description: Trigger select for Config Fifo



Detailed description of bit field cff0_trgsel values:



























Table 3-183: CFF_TRG_SEL0 Register


[31:24] cff3_trgsel RW 0xDC Select trigger input for config fifo 3

[23:16] cff2_trgsel RW 0xDB Select trigger input for config fifo 2

[15:8] cff1_trgsel RW 0xDA Select trigger input for config fifo 1

[7:0] cff0_trgsel RW 0xD9 Select trigger input for config fifo 0































209: RLT0_POUT - reload timer 0 output pulse


















255: DISABLE - disable trigger pulse to config fifo 0



































CFF_TRG_SEL1

Description: Trigger select for Config Fifo






























Table 3-184: CFF_TRG_SEL1 Register


[31:24] cff7_trgsel RW 0xE0 Select trigger input for config fifo 7

[23:16] cff6_trgsel RW 0xDF Select trigger input for config fifo 6

[15:8] cff5_trgsel RW 0xDE Select trigger input for config fifo 5

[7:0] cff4_trgsel RW 0xDD Select trigger input for config fifo 4



HIRQ_CTL

Description: Host interrupt control



Table 3-185: HIRQ_CTL Register



[1] host_irq_sts R 0x0 Status of host interrupt

[0] clear_host_irq R0W1

0x0 Clear host interrupt for one cycle, to pro-duce edge at outside when input is still present



APIX_HIEN

Description: Host interrupt enable for APIX interrupts



Table 3-186: APIX_HIEN Register



[14] APIX_HDCP_ERR_HIEN RW 0x0 Host interrupt enable for APIX_HDCP_ERR interrupt

(APIX HDCP error)

[13] APIX_HDCP_FUNC_HIEN

RW 0x0 Host interrupt enable for APIX_HDCP_FUNC interrupt


[12] APIX_PHY_NC2_HIEN RW 0x0 Host interrupt enable for APIX_PHY_NC2 interrupt


[11] APIX_PHY_NC1_HIEN RW 0x0 Host interrupt enable for APIX_PHY_NC1 interrupt


[10] APIX_PHY_RES_HIEN RW 0x0 Host interrupt enable for APIX_PHY_RES interrupt


[9] APIX_PHY_ARS_HIEN RW 0x0 Host interrupt enable for APIX_PHY_ARS interrupt


[8] APIX_PIX_FATAL_HIEN RW 0x0 Host interrupt enable for APIX_PIX_FATAL interrupt


[7] APIX_PIX_ERR_HIEN RW 0x0 Host interrupt enable for APIX_PIX_ERR interrupt


[6] APIX_ASHELL_FATAL_HIEN

RW 0x0 Host interrupt enable for APIX_ASHELL_FATAL interrupt


[5] APIX_ASHELL_ERR_HIEN

RW 0x0 Host interrupt enable for APIX_ASHELL_ERR interrupt

(APIX Ashell error)

[4] APIX_ASHELL_FUNC_HIEN

RW 0x0 Host interrupt enable for APIX_ASHELL_FUNC interrupt


[3] APIX_ASHELL_REQ_HIEN

RW 0x0 Host interrupt enable for APIX_ASHELL_REQ interrupt




[2] APIX_LINK_FATAL_HIEN

RW 0x0 Host interrupt enable for APIX_LINK_FATAL interrupt


[1] APIX_LINK_ERR_HIEN RW 0x0 Host interrupt enable for APIX_LINK_ERR interrupt

(APIX link error)

[0] APIX_LINK_FUNC_HIEN RW 0x0 Host interrupt enable for APIX_LINK_FUNC interrupt


Table 3-186: APIX_HIEN Register




ASHELL_RH_HIEN

Description: Host interrupt enable for ASHELL_RH interrupts



Table 3-187: ASHELL_RH_HIEN Register



[11] ARH_T_TOUT_HIEN RW 0x0 Host interrupt enable for ARH_T_TOUT interrupt


[10] ARH_T_OVL_HIEN RW 0x0 Host interrupt enable for ARH_T_OVL interrupt


[9] ARH_T_THRESH_HIEN RW 0x0 Host interrupt enable for ARH_T_THRESH interrupt


[8] ARH_R_OVL_HIEN RW 0x0 Host interrupt enable for ARH_R_OVL interrupt


[7] ARH_R_THRESH_HIEN RW 0x0 Host interrupt enable for ARH_R_THRESH interrupt


[6] ARH_WRLOCK_HIEN RW 0x0 Host interrupt enable for ARH_WRLOCK interrupt


[5] ARH_WERR_HIEN RW 0x0 Host interrupt enable for ARH_WERR inter-rupt


[4] ARH_RERR_HIEN RW 0x0 Host interrupt enable for ARH_RERR inter-rupt


[3] ARH_PUSH_ACK_HIEN RW 0x0 Host interrupt enable for ARH_PUSH_ACK interrupt


[2] ARH_PUSH_REQ_HIEN RW 0x0 Host interrupt enable for ARH_PUSH_REQ interrupt




[1] ARH_MAIL_ACK_HIEN RW 0x0 Host interrupt enable for ARH_MAIL_ACK interrupt


[0] ARH_MAIL_REQ_HIEN RW 0x0 Host interrupt enable for ARH_MAIL_REQ interrupt


Table 3-187: ASHELL_RH_HIEN Register




E2IP_HIEN

Description: Host interrupt enable for E2IP interrupts



Table 3-188: E2IP_HIEN Register



[16] E2IP_MAC1_UDT_HIEN RW 0x0 Host interrupt enable for E2IP_MAC1_UDT interrupt


[15] E2IP_MAC0_UDT_HIEN RW 0x0 Host interrupt enable for E2IP_MAC0_UDT interrupt


[14] E2IP_RX_OVWR_HIEN RW 0x0 Host interrupt enable for E2IP_RX_OVWR interrupt


[13] E2IP_TX_DROP_HIEN RW 0x0 Host interrupt enable for E2IP_TX_DROP interrupt


[12] E2IP_RX_DROP_HIEN RW 0x0 Host interrupt enable for E2IP_RX_DROP interrupt


[11] ERH_T_TOUT_HIEN RW 0x0 Host interrupt enable for ERH_T_TOUT interrupt


[10] ERH_T_OVL_HIEN RW 0x0 Host interrupt enable for ERH_T_OVL interrupt


[9] ERH_T_THRESH_HIEN RW 0x0 Host interrupt enable for ERH_T_THRESH interrupt


[8] ERH_R_OVL_HIEN RW 0x0 Host interrupt enable for ERH_R_OVL interrupt


[7] ERH_R_THRESH_HIEN RW 0x0 Host interrupt enable for ERH_R_THRESH interrupt




[6] ERH_WRLOCK_HIEN RW 0x0 Host interrupt enable for ERH_WRLOCK interrupt


[5] ERH_WERR_HIEN RW 0x0 Host interrupt enable for ERH_WERR inter-rupt


[4] ERH_RERR_HIEN RW 0x0 Host interrupt enable for ERH_RERR inter-rupt


[3] ERH_PUSH_ACK_HIEN RW 0x0 Host interrupt enable for ERH_PUSH_ACK interrupt


[2] ERH_PUSH_REQ_HIEN RW 0x0 Host interrupt enable for ERH_PUSH_REQ interrupt


[1] ERH_MAIL_ACK_HIEN RW 0x0 Host interrupt enable for ERH_MAIL_ACK interrupt


[0] ERH_MAIL_REQ_HIEN RW 0x0 Host interrupt enable for ERH_MAIL_REQ interrupt


Table 3-188: E2IP_HIEN Register




CFF_CTRL_HIEN

Description: Host interrupt enable for CFF_CTRL interrupts



Table 3-189: CFF_CTRL_HIEN Register



[9] CFF_DW0_HIEN RW 0x0 Host interrupt enable for CFF_DW0 inter-rupt
















[1] CFF_RERR_HIEN RW 0x0 Host interrupt enable for CFF_RERR inter-rupt


[0] CFF_ALL_HIEN RW 0x0 Host interrupt enable for CFF_ALL interrupt




CFF_FIFO_HIEN

Description: Host interrupt enable for CFF_FIFO interrupts



Table 3-190: CFF_FIFO_HIEN Register


[31] CFF_LTHD0_HIEN RW 0x0 Host interrupt enable for CFF_LTHD0 inter-rupt


[30] CFF_UTHD0_HIEN RW 0x0 Host interrupt enable for CFF_UTHD0 interrupt


[29] CFF_OFLW0_HIEN RW 0x0 Host interrupt enable for CFF_OFLW0 interrupt


[28] CFF_UFLW0_HIEN RW 0x0 Host interrupt enable for CFF_UFLW0 interrupt
















RLT_HIEN

Description: Host interrupt enable for RLT interrupts



Table 3-191: RLT_HIEN Register



[15] RLT15_HIEN RW 0x0 Host interrupt enable for RLT15 interrupt


































LIN_HIEN

Description: Host interrupt enable for LIN interrupts



Table 3-192: LIN_HIEN Register



[2] LIN_E_HIEN RW 0x0 Host interrupt enable for LIN_E interrupt


[1] LIN_T_HIEN RW 0x0 Host interrupt enable for LIN_T interrupt


[0] LIN_R_HIEN RW 0x0 Host interrupt enable for LIN_R interrupt




PPG_HIEN

Description: Host interrupt enable for PPG interrupts



Table 3-193: PPG_HIEN Register



[15] PPG33_HIEN RW 0x0 Host interrupt enable for PPG33 interrupt


































I2C0_HIEN

Description: Host interrupt enable for I2C0 interrupts



Table 3-194: I2C0_HIEN Register



[1] I2C0_ERIRQ_HIEN RW 0x0 Host interrupt enable for I2C0_ERIRQ interrupt


[0] I2C0_IRQ_HIEN RW 0x0 Host interrupt enable for I2C0_IRQ inter-rupt




I2C1_HIEN

Description: Host interrupt enable for I2C1 interrupts



Table 3-195: I2C1_HIEN Register



[1] I2C1_ERIRQ_HIEN RW 0x0 Host interrupt enable for I2C1_ERIRQ interrupt


[0] I2C1_IRQ_HIEN RW 0x0 Host interrupt enable for I2C1_IRQ inter-rupt




SGE_HIEN

Description: Host interrupt enable for SGE interrupts



Table 3-196: SGE_HIEN Register



[1] SGE_RLD_HIEN RW 0x0 Host interrupt enable for SGE_RLD inter-rupt


[0] SGE_IRQ_HIEN RW 0x0 Host interrupt enable for SGE_IRQ inter-rupt




ADC_HIEN

Description: Host interrupt enable for ADC interrupts



Table 3-197: ADC_HIEN Register



[3] ADC_ADPIRQ_HIEN RW 0x0 Host interrupt enable for ADC_ADPIRQ interrupt


[2] ADC_RCOIRQ_HIEN RW 0x0 Host interrupt enable for ADC_RCOIRQ interrupt


[1] ADC2_IRQ_HIEN RW 0x0 Host interrupt enable for ADC2_IRQ inter-rupt


[0] ADC_IRQ_HIEN RW 0x0 Host interrupt enable for ADC_IRQ inter-rupt




EIRQ_HIEN

Description: Host interrupt enable for EIRQ interrupts



Table 3-198: EIRQ_HIEN Register



[7] EIRQ_7_HIEN RW 0x0 Host interrupt enable for EIRQ_7 interrupt


















ESPI_HIEN

Description: Host interrupt enable for ESPI interrupts



Table 3-199: ESPI_HIEN Register



[2] ESPI_FAULT_HIEN RW 0x0 Host interrupt enable for ESPI_FAULT interrupt


[1] ESPI_TX_HIEN RW 0x0 Host interrupt enable for ESPI_TX interrupt


[0] ESPI_RX_HIEN RW 0x0 Host interrupt enable for ESPI_RX interrupt




IRIS_HIEN

Description: Host interrupt enable for IRIS interrupts



Table 3-200: IRIS_HIEN Register


[31] IRS_FC_SYNCERR_HIEN

RW 0x0 Host interrupt enable for IRS_FC_SYNCERR interrupt


[30] IRS_FC_SYNC_HIEN RW 0x0 Host interrupt enable for IRS_FC_SYNC interrupt


[29] IRS_FG_SYNCERR_S_HIEN

RW 0x0 Host interrupt enable for IRS_FG_SYNCERR_S interrupt


[28] IRS_FG_SYNC_S_HIEN RW 0x0 Host interrupt enable for IRS_FG_SYNC_S interrupt


[27] IRS_FG_SYNCERR_P_HIEN

RW 0x0 Host interrupt enable for IRS_FG_SYNCERR_P interrupt


[26] IRS_FG_SYNC_P_HIEN RW 0x0 Host interrupt enable for IRS_FG_SYNC_P interrupt


[25] IRS_SIG3_ERR_HIEN RW 0x0 Host interrupt enable for IRS_SIG3_ERR interrupt


[24] IRS_SIG3_RDY_HIEN RW 0x0 Host interrupt enable for IRS_SIG3_RDY interrupt


[23] IRS_SIG3_SL_HIEN RW 0x0 Host interrupt enable for IRS_SIG3_SL interrupt






















[13] IRS_FG_SL_S_HIEN RW 0x0 Host interrupt enable for IRS_FG_SL_S interrupt


[12] IRS_FG_SL_P_HIEN RW 0x0 Host interrupt enable for IRS_FG_SL_P interrupt


[11] IRS_FG_P3_HIEN RW 0x0 Host interrupt enable for IRS_FG_P3 inter-rupt












[7] IRS_DE_SC_HIEN RW 0x0 Host interrupt enable for IRS_DE_SC inter-rupt


[6] IRS_DE_SL_HIEN RW 0x0 Host interrupt enable for IRS_DE_SL inter-rupt


[5] IRS_LB1_SL_HIEN RW 0x0 Host interrupt enable for IRS_LB1_SL interrupt


[4] IRS_LB0_SL_HIEN RW 0x0 Host interrupt enable for IRS_LB0_SL interrupt


[3] IRS_PE_FC1_HIEN RW 0x0 Host interrupt enable for IRS_PE_FC1 interrupt


[2] IRS_PE_FC0_HIEN RW 0x0 Host interrupt enable for IRS_PE_FC0 interrupt


[1] IRS_PE_SC1_HIEN RW 0x0 Host interrupt enable for IRS_PE_SC1 interrupt


[0] IRS_PE_SC0_HIEN RW 0x0 Host interrupt enable for IRS_PE_SC0 interrupt






CMDSEQ_HIEN

Description: Host interrupt enable for CMDSEQ interrupts



Table 3-201: CMDSEQ_HIEN Register



[7] CMDSEQ_FULL_HIEN RW 0x0 Host interrupt enable for CMDSEQ_FULL interrupt


[6] CMDSEQ_EMPTY_HIEN RW 0x0 Host interrupt enable for CMDSEQ_EMPTY interrupt


[5] CMDSEQ_HALT_HIEN RW 0x0 Host interrupt enable for CMDSEQ_HALT interrupt


[4] CMDSEQ_ERROR_HIEN

RW 0x0 Host interrupt enable for CMDSEQ_ERROR interrupt


[3] CMDSEQ_HWM_HIEN RW 0x0 Host interrupt enable for CMDSEQ_HWM interrupt


[2] CMDSEQ_LWM_HIEN RW 0x0 Host interrupt enable for CMDSEQ_LWM interrupt


[1] CMDSEQ_SWINT_HIEN RW 0x0 Host interrupt enable for CMDSEQ_SWINT interrupt


[0] CMDSEQ_WDG_HIEN RW 0x0 Host interrupt enable for CMDSEQ_WDG interrupt




GC_HIEN

Description: Host interrupt enable for GC interrupts


Instance no 0: 0x000004FC

Table 3-202: GC_HIEN Register



[8] FLSH_HIEN RW 0x0 Host interrupt enable for FLSH interrupt


[7] HIFC_HIEN RW 0x0 Host interrupt enable for HIFC interrupt


[6] PANIC_SWITCH_HIEN RW 0x0 Host interrupt enable for PANIC_SWITCH interrupt

(Panic switch was asserted)

[5] LVD_H_F_HIEN RW 0x0 Host interrupt enable for LVD_H_F interrupt


[4] LVD_H_R_HIEN RW 0x0 Host interrupt enable for LVD_H_R inter-rupt


[3] LVD_L_F_HIEN RW 0x0 Host interrupt enable for LVD_L_F interrupt


[2] LVD_L_R_HIEN RW 0x0 Host interrupt enable for LVD_L_R interrupt


[1] GC_WDG_HIEN RW 0x0 Host interrupt enable for GC_WDG inter-rupt


[0] GC_ALV_HIEN RW 0x0 Host interrupt enable for GC_ALV interrupt




DMAC_HIEN

Description: Host interrupt enable for DMAC interrupts



Table 3-203: DMAC_HIEN Register



[5] DMAC_EIRQ1_HIEN RW 0x0 Host interrupt enable for DMAC_EIRQ1 interrupt


[4] DMAC_EIRQ0_HIEN RW 0x0 Host interrupt enable for DMAC_EIRQ0 interrupt


[3] DMAC_EIRQ_HIEN RW 0x0 Host interrupt enable for DMAC_EIRQ interrupt


[2] DMAC_DIRQ1_HIEN RW 0x0 Host interrupt enable for DMAC_DIRQ1 interrupt


[1] DMAC_DIRQ0_HIEN RW 0x0 Host interrupt enable for DMAC_DIRQ0 interrupt


[0] DMAC_DIRQ_HIEN RW 0x0 Host interrupt enable for DMAC_DIRQ interrupt




FSPI_HIEN

Description: Host interrupt enable for FSPI interrupts



Table 3-204: FSPI_HIEN Register



[2] FSPI_FAULT_HIEN RW 0x0 Host interrupt enable for FSPI_FAULT interrupt


[1] FSPI_TX_HIEN RW 0x0 Host interrupt enable for FSPI_TX interrupt


[0] FSPI_RX_HIEN RW 0x0 Host interrupt enable for FSPI_RX interrupt




PRGCRC_HIEN

Description: Host interrupt enable for PRGCRC interrupts



Table 3-205: PRGCRC_HIEN Register



[0] PRGCRC_IRQ_HIEN RW 0x0 Host interrupt enable for PRGCRC_IRQ interrupt




INTERCONNECT_HIEN

Description: Host interrupt enable for INTERCONNECT interrupts



Table 3-206: INTERCONNECT_HIEN Register



[7] IFLASH_TCBUSERR_HIEN

RW 0x0 Host interrupt enable for IFLASH_TCBUSERR interrupt


[6] IFLASH_BUSERR_HIEN RW 0x0 Host interrupt enable for IFLASH_BUSERR interrupt


[5] PRGCRC_BUSERR_HIEN

RW 0x0 Host interrupt enable for PRGCRC_BUSERR interrupt


[4] FSPI_BUSERR_HIEN RW 0x0 Host interrupt enable for FSPI_BUSERR interrupt


[3] ESPI_BUSERR_HIEN RW 0x0 Host interrupt enable for ESPI_BUSERR interrupt


[2] EXTIRQ_BUSERR_HIEN RW 0x0 Host interrupt enable for EXTIRQ_BUSERR interrupt


[1] ERBUS_BUSERR_HIEN RW 0x0 Host interrupt enable for ERBUS_BUSERR interrupt


[0] RBUS_BUSERR_HIEN RW 0x0 Host interrupt enable for RBUS_BUSERR interrupt




PNCSW_CTL

Description: Panic Switch control



Table 3-207: PNCSW_CTL Register



[3] ps_sts R 0x0 Current status of panic switch

[2] ps_test R0W1

0x0 Panic switch test, writing a 1 will trigger the panic switch

[1] ps_reset R0W1

0x0 Writing a 1 will reset the panic switch, all panic irqs have to be cleared before

[0] ps_enable RW 0x0 Panic switch enable

0x0: DISABLE - disabled

0x1: ENABLE - enabled



APIX_PSEN

Description: Panic switch enable for APIX interrupts



Table 3-208: APIX_PSEN Register



[14] APIX_HDCP_ERR_PSEN

RW 0x0 Panic switch enable for APIX_HDCP_ERR interrupt

(APIX HDCP error)

[13] APIX_HDCP_FUNC_PSEN

RW 0x0 Panic switch enable for APIX_HDCP_FUNC interrupt


[12] APIX_PHY_NC2_PSEN RW 0x0 Panic switch enable for APIX_PHY_NC2 interrupt


[11] APIX_PHY_NC1_PSEN RW 0x0 Panic switch enable for APIX_PHY_NC1 interrupt


[10] APIX_PHY_RES_PSEN RW 0x0 Panic switch enable for APIX_PHY_RES interrupt


[9] APIX_PHY_ARS_PSEN RW 0x0 Panic switch enable for APIX_PHY_ARS interrupt


[8] APIX_PIX_FATAL_PSEN RW 0x0 Panic switch enable for APIX_PIX_FATAL interrupt


[7] APIX_PIX_ERR_PSEN RW 0x0 Panic switch enable for APIX_PIX_ERR interrupt


[6] APIX_ASHELL_FATAL_PSEN

RW 0x0 Panic switch enable for APIX_ASHELL_FATAL interrupt


[5] APIX_ASHELL_ERR_PSEN

RW 0x0 Panic switch enable for APIX_ASHELL_ERR interrupt

(APIX Ashell error)

[4] APIX_ASHELL_FUNC_PSEN

RW 0x0 Panic switch enable for APIX_ASHELL_FUNC interrupt


[3] APIX_ASHELL_REQ_PSEN

RW 0x0 Panic switch enable for APIX_ASHELL_REQ interrupt




[2] APIX_LINK_FATAL_PSEN

RW 0x0 Panic switch enable for APIX_LINK_FATAL interrupt


[1] APIX_LINK_ERR_PSEN RW 0x0 Panic switch enable for APIX_LINK_ERR interrupt

(APIX link error)

[0] APIX_LINK_FUNC_PSEN

RW 0x0 Panic switch enable for APIX_LINK_FUNC interrupt


Table 3-208: APIX_PSEN Register




ASHELL_RH_PSEN

Description: Panic switch enable for ASHELL_RH interrupts



Table 3-209: ASHELL_RH_PSEN Register



[11] ARH_T_TOUT_PSEN RW 0x0 Panic switch enable for ARH_T_TOUT interrupt


[10] ARH_T_OVL_PSEN RW 0x0 Panic switch enable for ARH_T_OVL inter-rupt


[9] ARH_T_THRESH_PSEN RW 0x0 Panic switch enable for ARH_T_THRESH interrupt


[8] ARH_R_OVL_PSEN RW 0x0 Panic switch enable for ARH_R_OVL inter-rupt


[7] ARH_R_THRESH_PSEN RW 0x0 Panic switch enable for ARH_R_THRESH interrupt


[6] ARH_WRLOCK_PSEN RW 0x0 Panic switch enable for ARH_WRLOCK interrupt


[5] ARH_WERR_PSEN RW 0x0 Panic switch enable for ARH_WERR inter-rupt


[4] ARH_RERR_PSEN RW 0x0 Panic switch enable for ARH_RERR inter-rupt


[3] ARH_PUSH_ACK_PSEN RW 0x0 Panic switch enable for ARH_PUSH_ACK interrupt


[2] ARH_PUSH_REQ_PSEN RW 0x0 Panic switch enable for ARH_PUSH_REQ interrupt




[1] ARH_MAIL_ACK_PSEN RW 0x0 Panic switch enable for ARH_MAIL_ACK interrupt


[0] ARH_MAIL_REQ_PSEN RW 0x0 Panic switch enable for ARH_MAIL_REQ interrupt


Table 3-209: ASHELL_RH_PSEN Register




E2IP_PSEN

Description: Panic switch enable for E2IP interrupts



Table 3-210: E2IP_PSEN Register



[16] E2IP_MAC1_UDT_PSEN RW 0x0 Panic switch enable for E2IP_MAC1_UDT interrupt


[15] E2IP_MAC0_UDT_PSEN RW 0x0 Panic switch enable for E2IP_MAC0_UDT interrupt


[14] E2IP_RX_OVWR_PSEN RW 0x0 Panic switch enable for E2IP_RX_OVWR interrupt


[13] E2IP_TX_DROP_PSEN RW 0x0 Panic switch enable for E2IP_TX_DROP interrupt


[12] E2IP_RX_DROP_PSEN RW 0x0 Panic switch enable for E2IP_RX_DROP interrupt


[11] ERH_T_TOUT_PSEN RW 0x0 Panic switch enable for ERH_T_TOUT interrupt


[10] ERH_T_OVL_PSEN RW 0x0 Panic switch enable for ERH_T_OVL inter-rupt


[9] ERH_T_THRESH_PSEN RW 0x0 Panic switch enable for ERH_T_THRESH interrupt


[8] ERH_R_OVL_PSEN RW 0x0 Panic switch enable for ERH_R_OVL inter-rupt


[7] ERH_R_THRESH_PSEN RW 0x0 Panic switch enable for ERH_R_THRESH interrupt




[6] ERH_WRLOCK_PSEN RW 0x0 Panic switch enable for ERH_WRLOCK interrupt


[5] ERH_WERR_PSEN RW 0x0 Panic switch enable for ERH_WERR inter-rupt


[4] ERH_RERR_PSEN RW 0x0 Panic switch enable for ERH_RERR inter-rupt


[3] ERH_PUSH_ACK_PSEN RW 0x0 Panic switch enable for ERH_PUSH_ACK interrupt


[2] ERH_PUSH_REQ_PSEN RW 0x0 Panic switch enable for ERH_PUSH_REQ interrupt


[1] ERH_MAIL_ACK_PSEN RW 0x0 Panic switch enable for ERH_MAIL_ACK interrupt


[0] ERH_MAIL_REQ_PSEN RW 0x0 Panic switch enable for ERH_MAIL_REQ interrupt


Table 3-210: E2IP_PSEN Register




CFF_CTRL_PSEN

Description: Panic switch enable for CFF_CTRL interrupts



Table 3-211: CFF_CTRL_PSEN Register



[9] CFF_DW0_PSEN RW 0x0 Panic switch enable for CFF_DW0 interrupt
















[1] CFF_RERR_PSEN RW 0x0 Panic switch enable for CFF_RERR inter-rupt


[0] CFF_ALL_PSEN RW 0x0 Panic switch enable for CFF_ALL interrupt




CFF_FIFO_PSEN

Description: Panic switch enable for CFF_FIFO interrupts



Table 3-212: CFF_FIFO_PSEN Register


[31] CFF_LTHD0_PSEN RW 0x0 Panic switch enable for CFF_LTHD0 inter-rupt


[30] CFF_UTHD0_PSEN RW 0x0 Panic switch enable for CFF_UTHD0 inter-rupt


[29] CFF_OFLW0_PSEN RW 0x0 Panic switch enable for CFF_OFLW0 inter-rupt


[28] CFF_UFLW0_PSEN RW 0x0 Panic switch enable for CFF_UFLW0 inter-rupt
















RLT_PSEN

Description: Panic switch enable for RLT interrupts



Table 3-213: RLT_PSEN Register



[15] RLT15_PSEN RW 0x0 Panic switch enable for RLT15 interrupt


































LIN_PSEN

Description: Panic switch enable for LIN interrupts



Table 3-214: LIN_PSEN Register



[2] LIN_E_PSEN RW 0x0 Panic switch enable for LIN_E interrupt


[1] LIN_T_PSEN RW 0x0 Panic switch enable for LIN_T interrupt


[0] LIN_R_PSEN RW 0x0 Panic switch enable for LIN_R interrupt




PPG_PSEN

Description: Panic switch enable for PPG interrupts



Table 3-215: PPG_PSEN Register



[15] PPG33_PSEN RW 0x0 Panic switch enable for PPG33 interrupt


































I2C0_PSEN

Description: Panic switch enable for I2C0 interrupts



Table 3-216: I2C0_PSEN Register



[1] I2C0_ERIRQ_PSEN RW 0x0 Panic switch enable for I2C0_ERIRQ inter-rupt


[0] I2C0_IRQ_PSEN RW 0x0 Panic switch enable for I2C0_IRQ interrupt




I2C1_PSEN

Description: Panic switch enable for I2C1 interrupts



Table 3-217: I2C1_PSEN Register



[1] I2C1_ERIRQ_PSEN RW 0x0 Panic switch enable for I2C1_ERIRQ inter-rupt


[0] I2C1_IRQ_PSEN RW 0x0 Panic switch enable for I2C1_IRQ interrupt




SGE_PSEN

Description: Panic switch enable for SGE interrupts



Table 3-218: SGE_PSEN Register



[1] SGE_RLD_PSEN RW 0x0 Panic switch enable for SGE_RLD interrupt


[0] SGE_IRQ_PSEN RW 0x0 Panic switch enable for SGE_IRQ interrupt




ADC_PSEN

Description: Panic switch enable for ADC interrupts



Table 3-219: ADC_PSEN Register



[3] ADC_ADPIRQ_PSEN RW 0x0 Panic switch enable for ADC_ADPIRQ interrupt


[2] ADC_RCOIRQ_PSEN RW 0x0 Panic switch enable for ADC_RCOIRQ interrupt


[1] ADC2_IRQ_PSEN RW 0x0 Panic switch enable for ADC2_IRQ inter-rupt


[0] ADC_IRQ_PSEN RW 0x0 Panic switch enable for ADC_IRQ interrupt




EIRQ_PSEN

Description: Panic switch enable for EIRQ interrupts



Table 3-220: EIRQ_PSEN Register



[7] EIRQ_7_PSEN RW 0x0 Panic switch enable for EIRQ_7 interrupt


















ESPI_PSEN

Description: Panic switch enable for ESPI interrupts



Table 3-221: ESPI_PSEN Register



[2] ESPI_FAULT_PSEN RW 0x0 Panic switch enable for ESPI_FAULT inter-rupt


[1] ESPI_TX_PSEN RW 0x0 Panic switch enable for ESPI_TX interrupt


[0] ESPI_RX_PSEN RW 0x0 Panic switch enable for ESPI_RX interrupt




IRIS_PSEN

Description: Panic switch enable for IRIS interrupts



Table 3-222: IRIS_PSEN Register


[31] IRS_FC_SYNCERR_PSEN

RW 0x0 Panic switch enable for IRS_FC_SYNCERR interrupt


[30] IRS_FC_SYNC_PSEN RW 0x0 Panic switch enable for IRS_FC_SYNC interrupt


[29] IRS_FG_SYNCERR_S_PSEN

RW 0x0 Panic switch enable for IRS_FG_SYNCERR_S interrupt


[28] IRS_FG_SYNC_S_PSEN RW 0x0 Panic switch enable for IRS_FG_SYNC_S interrupt


[27] IRS_FG_SYNCERR_P_PSEN

RW 0x0 Panic switch enable for IRS_FG_SYNCERR_P interrupt


[26] IRS_FG_SYNC_P_PSEN RW 0x0 Panic switch enable for IRS_FG_SYNC_P interrupt


[25] IRS_SIG3_ERR_PSEN RW 0x0 Panic switch enable for IRS_SIG3_ERR interrupt


[24] IRS_SIG3_RDY_PSEN RW 0x0 Panic switch enable for IRS_SIG3_RDY interrupt


[23] IRS_SIG3_SL_PSEN RW 0x0 Panic switch enable for IRS_SIG3_SL interrupt






















[13] IRS_FG_SL_S_PSEN RW 0x0 Panic switch enable for IRS_FG_SL_S interrupt


[12] IRS_FG_SL_P_PSEN RW 0x0 Panic switch enable for IRS_FG_SL_P interrupt


[11] IRS_FG_P3_PSEN RW 0x0 Panic switch enable for IRS_FG_P3 inter-rupt












[7] IRS_DE_SC_PSEN RW 0x0 Panic switch enable for IRS_DE_SC inter-rupt


[6] IRS_DE_SL_PSEN RW 0x0 Panic switch enable for IRS_DE_SL inter-rupt


[5] IRS_LB1_SL_PSEN RW 0x0 Panic switch enable for IRS_LB1_SL inter-rupt


[4] IRS_LB0_SL_PSEN RW 0x0 Panic switch enable for IRS_LB0_SL inter-rupt


[3] IRS_PE_FC1_PSEN RW 0x0 Panic switch enable for IRS_PE_FC1 inter-rupt


[2] IRS_PE_FC0_PSEN RW 0x0 Panic switch enable for IRS_PE_FC0 inter-rupt


[1] IRS_PE_SC1_PSEN RW 0x0 Panic switch enable for IRS_PE_SC1 inter-rupt


[0] IRS_PE_SC0_PSEN RW 0x0 Panic switch enable for IRS_PE_SC0 inter-rupt






CMDSEQ_PSEN

Description: Panic switch enable for CMDSEQ interrupts



Table 3-223: CMDSEQ_PSEN Register



[7] CMDSEQ_FULL_PSEN RW 0x0 Panic switch enable for CMDSEQ_FULL interrupt


[6] CMDSEQ_EMPTY_PSEN

RW 0x0 Panic switch enable for CMDSEQ_EMPTY interrupt


[5] CMDSEQ_HALT_PSEN RW 0x0 Panic switch enable for CMDSEQ_HALT interrupt


[4] CMDSEQ_ERROR_PSEN

RW 0x0 Panic switch enable for CMDSEQ_ERROR interrupt


[3] CMDSEQ_HWM_PSEN RW 0x0 Panic switch enable for CMDSEQ_HWM interrupt


[2] CMDSEQ_LWM_PSEN RW 0x0 Panic switch enable for CMDSEQ_LWM interrupt


[1] CMDSEQ_SWINT_PSEN RW 0x0 Panic switch enable for CMDSEQ_SWINT interrupt


[0] CMDSEQ_WDG_PSEN RW 0x0 Panic switch enable for CMDSEQ_WDG interrupt




GC_PSEN

Description: Panic switch enable for GC interrupts



Table 3-224: GC_PSEN Register



[8] FLSH_PSEN RW 0x0 Panic switch enable for FLSH interrupt


[7] HIFC_PSEN RW 0x0 Panic switch enable for HIFC interrupt



[5] LVD_H_F_PSEN RW 0x0 Panic switch enable for LVD_H_F interrupt


[4] LVD_H_R_PSEN RW 0x0 Panic switch enable for LVD_H_R interrupt


[3] LVD_L_F_PSEN RW 0x0 Panic switch enable for LVD_L_F interrupt


[2] LVD_L_R_PSEN RW 0x0 Panic switch enable for LVD_L_R interrupt


[1] GC_WDG_PSEN RW 0x0 Panic switch enable for GC_WDG interrupt


[0] GC_ALV_PSEN RW 0x0 Panic switch enable for GC_ALV interrupt




DMAC_PSEN

Description: Panic switch enable for DMAC interrupts



Table 3-225: DMAC_PSEN Register



[5] DMAC_EIRQ1_PSEN RW 0x0 Panic switch enable for DMAC_EIRQ1 interrupt


[4] DMAC_EIRQ0_PSEN RW 0x0 Panic switch enable for DMAC_EIRQ0 interrupt


[3] DMAC_EIRQ_PSEN RW 0x0 Panic switch enable for DMAC_EIRQ inter-rupt


[2] DMAC_DIRQ1_PSEN RW 0x0 Panic switch enable for DMAC_DIRQ1 interrupt


[1] DMAC_DIRQ0_PSEN RW 0x0 Panic switch enable for DMAC_DIRQ0 interrupt


[0] DMAC_DIRQ_PSEN RW 0x0 Panic switch enable for DMAC_DIRQ inter-rupt




FSPI_PSEN

Description: Panic switch enable for FSPI interrupts



Table 3-226: FSPI_PSEN Register



[2] FSPI_FAULT_PSEN RW 0x0 Panic switch enable for FSPI_FAULT inter-rupt


[1] FSPI_TX_PSEN RW 0x0 Panic switch enable for FSPI_TX interrupt


[0] FSPI_RX_PSEN RW 0x0 Panic switch enable for FSPI_RX interrupt




PRGCRC_PSEN

Description: Panic switch enable for PRGCRC interrupts



Table 3-227: PRGCRC_PSEN Register



[0] PRGCRC_IRQ_PSEN RW 0x0 Panic switch enable for PRGCRC_IRQ interrupt




INTERCONNECT_PSEN

Description: Panic switch enable for INTERCONNECT interrupts



Table 3-228: INTERCONNECT_PSEN Register



[7] IFLASH_TCBUSERR_PSEN

RW 0x0 Panic switch enable for IFLASH_TCBUSERR interrupt


[6] IFLASH_BUSERR_PSEN

RW 0x0 Panic switch enable for IFLASH_BUSERR interrupt


[5] PRGCRC_BUSERR_PSEN

RW 0x0 Panic switch enable for PRGCRC_BUSERR interrupt


[4] FSPI_BUSERR_PSEN RW 0x0 Panic switch enable for FSPI_BUSERR interrupt


[3] ESPI_BUSERR_PSEN RW 0x0 Panic switch enable for ESPI_BUSERR interrupt


[2] EXTIRQ_BUSERR_PSEN

RW 0x0 Panic switch enable for EXTIRQ_BUSERR interrupt


[1] ERBUS_BUSERR_PSEN RW 0x0 Panic switch enable for ERBUS_BUSERR interrupt


[0] RBUS_BUSERR_PSEN RW 0x0 Panic switch enable for RBUS_BUSERR interrupt




DMA_CNTRL

Description: Control for Interrupt base DMA requests



Detailed description of bit field dma0_irqsel values:


















Table 3-229: DMA_CNTRL Register



[26] dma1_ack_sts R 0x0 Current state of DMA0 acknowledge (for debug only)

[25] dma1_req_sts R 0x0 Current state of DMA0 request (for debug only)

[24] dma1_rst R0W1

0x0 Reset for DMA0 request (for debug only)

[23:16] dma1_irqsel RW 0xFF Select interrupt for DMA request 1


[10] dma0_ack_sts R 0x0 Current state of DMA0 acknowledge (for debug only)

[9] dma0_req_sts R 0x0 Current state of DMA0 request (for debug only)

[8] dma0_rst R0W1

0x0 Reset for DMA0 request (for debug only)

[7:0] dma0_irqsel RW 0xFF Select interrupt for DMA request 0



Detailed description of bit field dma1_irqsel values:










































3.2 APIX2 Registers

In this section, the ‘Register Overview’ tables summarize all APIX2 registers, including base address ofthe module and name, description, and the absolute address of each register, which are then describedseparately in the following tables.


3.2.1 APIX2 PHY Register Overview




BASEADDR + 0x0000 PHY_RST_CTRL Control PHY reset and PLL reset

BASEADDR + 0x0004 PHY_RST_STAT PHY Startup Status


BASEADDR + 0x000C PHY_PWR_CTRL PHY Power Control

BASEADDR + 0x0010 PHY_LT_CFG_CTRL Loopthru configuration

BASEADDR + 0x0014 PHY_LT_CFG_CTRL_1 Loopthru Tx FIR Coefficients

BASEADDR + 0x0018 PHY_LT_CFG_CTRL_2 Loopthru Tx FIR structure

BASEADDR + 0x001C PHY_LT_CTRL_1 Loopthru configuration

BASEADDR + 0x0020 PHY_LT_CTRL_2 Loopthru Tx Calibration

BASEADDR + 0x0024 PHY_LT_I_STAT Loopthru Calibration Status

BASEADDR + 0x0028 PHY_LT_P_STAT Loopthru Calibation Status




BASEADDR + 0x0038 PHY_CDR_CFG CDR configuration




BASEADDR + 0x0048 PHY_RX_TST Upstream Swing



BASEADDR + 0x0054 PHY_RX_UP RX Upstream Calibration










BASEADDR + 0x00E0 Reserved Do not modify



BASEADDR + 0x00EC Reserved Do not modify

BASEADDR + 0x00F0 OBS_RX_2 Add observability to DFE regsiter

BASEADDR + 0x00F4 Reserved Do not modify

BASEADDR + 0x0100 BIST_PATTGEN_LINK Bist Link Control

BASEADDR + 0x0104 BistTestDuration test duration

BASEADDR + 0x0108 BistPrbsCfg setup for 16 bit PRBS generator

BASEADDR + 0x010C BistChkPrbsCfg specify a polynomial for 16 bit PRBS checker

BASEADDR + 0x0110 BistCtrl Trigger to start checking test pattern

BASEADDR + 0x0114 BistDownStatus Status of Bist from downstream receiver









BASEADDR + 0x0200 CLKMEAS_CFG Clock Measurement Configuration Register

BASEADDR + 0x0204 CLKMEAS_CNT Clock Measurement Count Register


BASEADDR + 0x0280 MII_CLK_CTRL MII Clock Control


BASEADDR + 0x0288 SYS_CLK_CTRL PHY SYS clock control

BASEADDR + 0x028C PERI_CLK_CTRL PHY SYS clock control

BASEADDR + 0x0290 VID_CLK_CTRL PHY VID clock control

BASEADDR + 0x0294 VIDS_CLK_CTRL PHY VIDS (shifter) clock control






PHY_RST_CTRL

Description: Control PHY reset and PLL reset



Table 3-231: PHY_RST_CTRL Register



[1] sw_pll_reset RW 0x0 reset PLL

1: reset -

0: operational -

[0] sw_reset RW 0x1 reset all except PLL

1: reset -

0: operational -



PHY_RST_STAT

Description: PHY Startup Status



Table 3-232: PHY_RST_STAT Register



[4] pll_good R 0x0 PLL good signal from PHY


[2] apix2_rx_analog_reset_n R 0x0 Inova APIX2 RX requests for reset

[1] ars_reset_request R 0x0 PLL out of VCO tuning range, analog PHY requests for reset




PHY_PWR_CTRL

Description: PHY Power Control



Table 3-233: PHY_PWR_CTRL Register




[10] pd_n RW 0x1 Power down (effective in ES1 only)

0: powerdown -

1: enable -

[9] pd_bandgap_n RW 0x1 Power down bandgap

0: powerdown -

1: enable -

[8] pd_upstream_n RW 0x1 Power down upstream

0: powerdown -

1: enable -

[7] pd_clkgen_n RW 0x1 Power down clock generator

0: powerdown -

1: enable -

[6] pd_sybuf_n RW 0x1 Power down clock buffer to PLL

0: powerdown -

1: enable -

[5] pd_rxbuf_n RW 0x1 Power down clock buffer to RX

0: powerdown -

1: enable -

[4] pd_vco_n RW 0x1 Power down VCO

0: powerdown -

1: enable -

[3] pd_cp_n RW 0x1 Power down charge pump

0: powerdown -

1: enable -

[2] pd_pll_n RW 0x1 Power down PLL

0: powerdown -

1: enable -

[1] en_lt RW 0x0 Enable Loopthru Transmitter

0: disable -

1: enable -



[0] en_rx RW 0x1 Enable receiver

0: disable -

1: enable -

Table 3-233: PHY_PWR_CTRL Register




PHY_LT_CFG_CTRL

Description: Loopthru configuration



Table 3-234: PHY_LT_CFG_CTRL Register






[1:0] lt_tx_rate RW 0x0 Daisy Chain TX rate

3: 3Gbit/s -

2: 1Gbit/s -

1: 500Mbit/s -

0: reset -



PHY_LT_CFG_CTRL_1

Description: Loopthru Tx FIR Coefficients



Table 3-235: PHY_LT_CFG_CTRL_1 Register



[30] lt_fir_sign_3 RW 0x0 Loopthru FIR Sign C3

[29:24] lt_fir_c3 RW 0x20 Loopthru FIR C3












PHY_LT_CFG_CTRL_2

Description: Loopthru Tx FIR structure



Table 3-236: PHY_LT_CFG_CTRL_2 Register



[4:2] lt_fir_d RW 0x7 Loopthru FIR d

[1:0] lt_fir_b RW 0x3 Loopthru FIR b



PHY_LT_CTRL_1

Description: Loopthru configuration



Table 3-237: PHY_LT_CTRL_1 Register



[8] lt_apix2_mode RW 0x1 Loopthru apix mode

0: apix1 - Apix1 Mode

1: apix2 - Apix2 Mode


[1] lt_select_clksource RW 0x1 Loopthru clock select

0: test - from PLL

1: normal - from CDR

[0] lt_select_datasource RW 0x1 select data source for loopthru transmitter (ES1 only - ES2 must set to 0)

0: normal -

1: CDR direct - (ES1 only)



PHY_LT_CTRL_2

Description: Loopthru Tx Calibration



Table 3-238: PHY_LT_CTRL_2 Register



[10] lt_p_tst_ctl_en RW 0x0 Use override value (lt_p_ctl_tst_val) for cable dependent calibration [INTERNAL]

0: normal -

1: override -

[9] lt_p_intcal_en RW 0x0 Use override value (lt_p_cal_tst_val) for comparator calibration [INTERNAL]

0: normal -

1: override -

[8] lt_p_calib_en RW 0x0 Enable cable dependent calibration

0: disable -

1: enable -


[2] lt_i_tst_ctl_en RW 0x0 Use override value (lt_i_ctl_tst_val) for pro-cess calibration [INTERNAL]

0: normal -

1: override -

[1] lt_i_intcal_en RW 0x0 Use override value (lt_i_cal_tst_val) for comparator calibration [INTERNAL]

0: normal -

1: override -

[0] lt_i_calib_en RW 0x0 Enable process compensation calibration

0: disable -

1: enable -



PHY_LT_I_STAT

Description: Loopthru Calibration Status



Table 3-239: PHY_LT_I_STAT Register





[24:16] lt_i_control R 0x0 process compensation value


[10:0] lt_i_calib R 0x0 comparator calibration value



PHY_LT_P_STAT

Description: Loopthru Calibation Status



Table 3-240: PHY_LT_P_STAT Register





[24:16] lt_p_control R 0x0 Cable dependent calibration value


[10:0] lt_p_calib R 0x0 comparator calibration value



PHY_CDR_CFG

Description: CDR configuration



Table 3-241: PHY_CDR_CFG Register



[3:0] cdr_ctrdepth RW 0x1 set counter depth (default 1, except for speed mode 3 (3Gbit) --> 4'b0101; Never set to 0!



PHY_RX_TST

Description: Upstream Swing



Table 3-242: PHY_RX_TST Register




[21:16] rx_upstream_swing RW 0xF rx_upstream output swing

0 : off

15 : default

63 : maximum

For calibrated output level the LT process calibration value lt_i_control[8:1]

should be copied to rx_up_calib[7:0] after LT calibration


[6] rx_test_phase_en RW 0x0 activate rx_test_phase_up/dn test, inhibits normal cdr algo [INTERNAL]

0: normal -

1: test -

[5:1] rx_test_onehot RW 0x0 select a single phase for phase interpolator [INTERNAL]

0 : normal

1..20 : test single phase 0..19

[0] rx_test_onehot_enable RW 0x0 enable test for phase interpolator [INTER-NAL]

0: normal -

1: test -



PHY_RX_UP

Description: RX Upstream Calibration



Table 3-243: PHY_RX_UP Register



[24:17] rx_up_calib RW 0x0 Calibration register for upstream transmit-ter

Set this equal to lt_i_control[8:1] after LT calibration




OBS_RX_2

Description: Add observability to DFE regsiter



Table 3-244: OBS_RX_2 Register



[30] obs_dfe_fir_sign_2 R 0x0 Sign bit of DFE coefficient 2

0: NEG - negative value

1: POS - positive value

[29:24] obs_dfe_fir_c2 R 0x0 DFE coefficient 2














BIST_PATTGEN_LINK

Description: Bist Link Control



Table 3-245: BIST_PATTGEN_LINK Register



[20] bist_up_gen_clksel RW 0x0 Direction of shift (no function?)

0: default - use lt_base_clk

1: shifted - use lt_base_clk shifted 90 deg


[18:16] bist_up_data_bitsel RW 0x0 Select the bit of rx_up_data[5:0] or lt_up_testdata[5:0] to be checked


[9:8] bist_up_pattgen RW 0x0 Upstream Pattern Generation

0: normal - normal (data from Rapix)

1: pattgen - upstream pattern generator active

2: lt_up_data - loopback upstream rx data to upstream tx

3: lt_up_testdata - loopback upstream lt testdata to upstream tx


[5:4] bist_down_rate RW 0x1 Downstream Pattern Generator Rate

0: unused_bw - unused

1: half_bw - 500 Mbit/s (default)

2: full_bw - 1000 Mbit/s

3: high_bw - 3000 Mbit/s


[1:0] bist_down_pattgen RW 0x0 Loopthrough Source (set to 2)

0: reset -

1: pattgen - pattern generator active

2: normal - loopback rx data to tx; (Loop-thru)



BistTestDuration

Description: test duration



Table 3-246: BistTestDuration Register



[4:0] Bist_MaxDuration RW 0x0 0: run forever or stop by stop trigger; >0: run the specified number of clock cycles calculated by 2^Bist_MaxDuration



BistPrbsCfg

Description: setup for 16 bit PRBS generator



Table 3-247: BistPrbsCfg Register


[31:16] bist_start_pattern RW 0x0 For PRBS the 16 LSBs are used as the seed.

[15:0] bist_prbs_poly RW 0x0 polynomial (max. 16bit Polynomial). Default: x6+x5+x3+x2+1 according to ITU-T V.29



BistChkPrbsCfg

Description: specify a polynomial for 16 bit PRBS checker



Table 3-248: BistChkPrbsCfg Register



[15:0] bist_chk_prbs_poly RW 0x110 polynomial (max. 16bit Polynomial). Default: x6+x5+x3+x2+1 according to ITU-T V.29



BistCtrl

Description: Trigger to start checking test pattern



Table 3-249: BistCtrl Register



[2] BIST_Status_Clear R0W1

0x0 write a "1" to reset all status register and all states of BIST

[1] BIST_Trigger_stop R0W1

0x0 write a "1" to stop checking test pattern

[0] BIST_Trigger_start R0W1

0x0 write a "1" to start checking test pattern



BistDownStatus

Description: Status of Bist from downstream receiver



Table 3-250: BistDownStatus Register



[21] Bist_Down_static0 R 0x0 1: received static 0 for at least 32 consecu-tive bits (if using PRBS pattern it indicates that input signals are not connected)

[20] Bist_Down_static1 R 0x0 1: received static 1 for at least 32 consecu-tive bits (if using PRBS pattern it indicates that input signals are not connected)


[17:8] Bist_Down_Err_Cnt R 0x0 b0 : No Data Error b1 : Data Error found (Trigger_start will set Down_Data_Error_Counter to 0)


[2] Bist_Down_NoErr R 0x1 b1 : No error; b0 : error in BIST

[1] Bist_Down_Done R 0x0 b0 : Test in Progress b1 : Test Done (Trigger_start will set Down_Done to b0)

[0] Bist_Down_Busy R 0x0 b0 : PRBS BIST disabled, b1 : PRBS BIST enabled



CLKMEAS_CFG

Description: Clock Measurement Configuration Register



Table 3-251: CLKMEAS_CFG Register


[31] clkmeas_clear RW 0x0 Clear prescaler; 1=clear on, 0=clear off

0: OFF - Clear is off.

1: ON - Clear is on.


[29:8] clkmeas_accu RW 0xEA6 Measurement period = clkmeas_accu * 8 /Xtal_freq

The default value returns a value in kHz in CLKMEAS_CNT register


[6:4] clkmeas_clksel RW 0x0 Select clock source for clock measurement.

0: rx_clk - rx_clk is measured

1: lt_clk - lt_clk is measured

2: sys_clk - sys_clk is measured

3: vid_clk - vid_clk is measured

4: peri_clk - peri_clk is measured

5: mclk_clk - mclk_clk is measured

6: vids_clk - vids_clk is measured

7: mii_clk - mii_clk is measured


[0] clkmeas_en RW 0x0 Enable clock measurement; 1=enabled, 0=disabled

0x0: OFF - Clock measurement unit is off.

0x1: ON - Clock measurement unit is off.



CLKMEAS_CNT

Description: Clock Measurement Count Register



Table 3-252: CLKMEAS_CNT Register


[31:0] clkmeas_count R 0x0 Clock measurement result.

Clk Frequency = clkmeas_count * 30e6 /8 /clkmeas_accu

With default clkmeas_accu, clkmeas_count displays the frequency in kHz



MII_CLK_CTRL

Description: MII Clock ControlReset value only set in shadow register.Clock synthesis module does not use the reset value after device reset.



Table 3-253: MII_CLK_CTRL Register


[31] mii_clk_en RW 0x0 force to enables mii clock

0: disable -

1: enable -




SYS_CLK_CTRL

Description: PHY SYS clock controlReset value only set in shadow register.Clock synthesis module does not use the reset value after device reset.



Table 3-254: SYS_CLK_CTRL Register


[31] sys_clk_en RW 0x0 clock enable

0: disable -

1: enable -

[30] sys_clk_mod_en RW 0x0 triangle clock modulation enable

0: disable -

1: enable -



[27:16] sys_clk_mod_step RW 0x4 modulation amplitude

[15:0] sys_clk_pw RW 0x4C0 pulse width



PERI_CLK_CTRL

Description: PHY SYS clock controlReset value only set in shadow register.Clock synthesis module does not use the reset value after device reset.



Table 3-255: PERI_CLK_CTRL Register


[31] peri_clk_en RW 0x0 clock enable

0: disable -

1: enable -

[30] peri_clk_mod_en RW 0x0 triangle clock modulation enable

0: disable -

1: enable -



[27:16] peri_clk_mod_step RW 0x9 modulation amplitude

[15:0] peri_clk_pw RW 0x960 pulse width



VID_CLK_CTRL

Description: PHY VID clock controlReset value only set in shadow register.Clock synthesis module does not use the reset value after device reset.



Table 3-256: VID_CLK_CTRL Register


[31] vid_clk_en RW 0x0 clock enable

0: disable -

1: enable -

[30] vid_clk_mod_en RW 0x0 triangle clock modulation enable

0: disable -

1: enable -



[27:16] vid_clk_mod_step RW 0x4 modulation amplitude

[15:0] vid_clk_pw RW 0x469 pulse width



VIDS_CLK_CTRL

Description: PHY VIDS (shifter) clock controlReset value only set in shadow register.Clock synthesis module does not use the reset value after device reset.



Table 3-257: VIDS_CLK_CTRL Register


[31] vids_clk_en RW 0x0 enables automatic update of vids_clk_delay

0: disable -

1: enable -



[25:16] vids_clk_delay RW 0x0 Samples vid_clk, vids_clk, vids2_clk using vid3_clk




3.2.2 APIX2RX Link Register Overview

The APIX2 RX Link Layer is configured by applying the configuration data together with an config_validat the configuration interface.

The configuration data register APIX_CFG_* may only be changed if APIX_CFG_VALID.config_valid isinactive.

The APIX2 RX Link Layer is disabled and a soft reset is issued to the block immediately after deassertingAPIX_CFG_VALID.config_valid.




BASEADDR + 0x0000 APIX_CFG_0 Inova Config Byte



BASEADDR + 0x000C APIX_CFG_3 Inova Config Byte






BASEADDR + 0x0024 APIX_PARAM_3 Config Parameter


BASEADDR + 0x0100 APIX_CFG_VALID Inova Config Signals, resets APIX IP core

BASEADDR + 0x0104 APIX_CFG_MODE Inova Config Signals, general configuration register

BASEADDR + 0x0108 APIX_STAT_CTRL_0 Inova Status Control Signals

BASEADDR + 0x010C APIX_STAT_CTRL_1 Inova Counter Clear Signals

BASEADDR + 0x0110 APIX_STAT_TIMEOUT Inova frame alignment status

BASEADDR + 0x0114 APIX_STAT_0 Inova Status Bytes


BASEADDR + 0x011C APIX_STAT_2 Inova Status Bytes


BASEADDR + 0x0124 TST_CFG_0 Inova Test Config Bytes

BASEADDR + 0x0128 TST_STAT Inova Test Status Bytes





BASEADDR + 0x013C DBG_STAT_4 Inova Debug Data from IP

BASEADDR + 0x0140 DBG_STAT_5 Inova Debug Data from IP,

BASEADDR + 0x0144 APIX_REM_CMD_EN APIX Remote Command Inbound Enable

BASEADDR + 0x0148 APIX_REM_CMD_REQ APIX Remote Command Request

BASEADDR + 0x014C APIX_REM_CMD_STAT APIX Remote Command Status


BASEADDR + 0x0154 INT_STAT_LINK Interrupt Status Link

BASEADDR + 0x0158 INT_STAT_ASHELL Interrupt Status Ashell

BASEADDR + 0x015C INT_STAT_PIX Interrupt Status Ashell

BASEADDR + 0x0160 INT_EN_LINK Interrupt Enable Link

BASEADDR + 0x0164 INT_EN_ASHELL Interrupt Enable Ashell

BASEADDR + 0x0168 INT_EN_PIX Interrupt Enable Ashell

BASEADDR + 0x016C INT_SET_LINK Interrupt Set Link

BASEADDR + 0x0170 INT_SET_ASHELL Interrupt Set Ashell



BASEADDR + 0x0174 INT_SET_PIX Interrupt Set Pixel







APIX_CFG_0

Description: Inova Config Byte0x01 DFE control0x02 APIX analog configurationfor APIX1 and APIX2



Table 3-259: APIX_CFG_0 Register



[15] agc_auto_calc_off RW 0x1 AGC coefficient auto calculation

See APIX Configuration Data

agc_coeff

Important

set to 0 if DownBw is set to 0b11 (3000 Mbit/s),

set to 1 otherwise

0: enable - AGC coefficient is calculated automatically

1: disable - AGC coefficient must be defined manually

[14] fir_auto_calc_off RW 0x1 FIR coefficients auto calculation

See APIX Configuration Data

fir_coeff_0, fir_signum_0,

fir_coeff_1, fir_signum_1,

fir_coeff_2, fir_signum_2

Important

set to 0 if DownBw is set to 0b11 (3000 Mbit/s),

set to 1 otherwise

0: enable - FIR coefficients are calculated automatically

1: disable - FIR coefficients must be defined manually

[13] ignore_pll_good RW 0x0 ignore PLL good

if disabled, lost of PLL good results in reset of APIX1/2 core after finished configuration

1: enable -

0: disable -





[10] low_pass RW 0x0 set to 1 if down_bw is set to 0b11 (3000 Mbit/s), set to 0 otherwise

0: disable -

1: enable -

[9:8] down_bw RW 0x1 downstream bandwidth (CDR mode[1:0])

Important:

if set to 01 or 10 (500 Mbit/s or 1000 Mbit/s):

set all FIR coefficients to 0

set the AGC coefficient to 32

set signums of all FIR coefficients to 0

if set to 11 (3000 Mbit/s) see also cdr_counter_depth

0: unused_bw - unused

1: half_bw - 500 Mbit/s (default)

2: full_bw - 1000 Mbit/s

3: high_bw - 3000 Mbit/s

[7] err_detection_en RW 0x0 enable error detection

AGC and FIR coefficients are re-initialized and the DFE algorithm is restarted when an error condition is detected.

With error detection disabled, this error condition follows watchdog for restart of DFE algorithm.

With error detection enabled, this error condition follows watchdog for restart of DFE algorithm only when a certain DFE internal condition is active at the same time (only for 3 GBit/s mode)

0: disable - Default value

1: enable -

[6] filter_enable RW 0x0 if active enables a pattern filter influencing the DFE algorithm

0: disable -

1: enable - Default value for 3 Gbit/s mode

[5:4] update_value RW 0x0 define the step size used to update FIR and AGC coefficients (DFE)

0: step_1_16 - 1/16 of LSB

1: step_1_32 - 1/32 of LSB

2: step_1_64 - 1/64 of LSB, Default value for 3 Gbit/s mode

3: step_1_16_2 - 1/16 of LSB






[2:1] active_cx RW 0x0 select coefficients which are calculated by the DFE algorithm

0: agc_c - agc_c

1: agc_c_fir_c0 - agc_c, fir_c0

2: agc_c_fir_c0_fir_c1 - agc_c, fir_c0, fir_c1

3: agc_c_fir_c0_fir_c1_fir_c2 - agc_c, fir_c0, fir_c1, fir_c2, Default value for 3 GBit/s mode

[0] use_preset4init RW 0x0 enables FIR and AGC preset for DFE algo-rithm

if enabled and AGC/FIR coefficient auto calculation enabled, FIR coefficient{0,1,2} (together with their sign presets) and AGC coefficient are used when the DFE algo-rithm is initialized (otherwise internally defined defaults are used)

0: disable - Default value

1: enable -





APIX_CFG_1

Description: Inova Config Byte0x05 definition of FIR coefficient 0 for DFE0x06 definition of FIR coefficient 1 for DFE0x07 definition of FIR coefficient 2 for DFEfor APIX1 and APIX2







[22] fir_signum_2 RW 0x0 defines the signum of FIR coefficient 2

Important

if DownBW is set to 01 or 10 (downstream bandwidth 500Mbit/s or 1000Mbit/s)

set the signum to 0

set the FIR coefficient to 0

0: neg - negative signum

1: pos - positive signum

[21:16] fir_coeff_2 RW 0x0 defines the FIR coefficient 2

Important


set the signum to 0


Note:

these definitions are not applied if the auto calculation of the coefficients is enabled



Important


set the signum to 0







Important


set the signum to 0


Note:




Important


set the signum to 0





Important


set the signum to 0


Note:






APIX_CFG_2

Description: Inova Config Byte 0x0a definition of AGC coefficient 0x0b configure watchdog for DFE upstream0x0c Upstream bit alignment for APIX1 and APIX2





[31] up_wait_dwn_fa_en RW 0x1 sense downstream frame aligned for upstream

if enabled no transitions on upstream until the downstream is frame aligned to avoid a bad bit alignment at upstream receiver

0: disable -

1: enable -

[30] up_ba_sel_fa RW 0x1 upstream self start of bit realignment

if the limit of upstream link qualifier exceeded, upstream bit alignment start a new bit alignment.

if the internal monitoring of upstream bit alignment detects too many consecutive misalignments (defined by upBAErrThresh) realignment is started.

0: disable - disable

1: enable - enable

[29:27] up_ba_thresh RW 0x3 upstream link qualifier threshold

threshold of consecutive upstream bit align-ment


1: thresh_1 - qualifier threshold 1







[26] up_ba_hi_pass_en RW 0x0 upstream bit alignment high pass allowed only a bit alignment at fast transitions


1: enable - enable



[25:24] up_sp_offset_750 RW 0x0 upstream sample point multiple of 750 MHz clocks

only a fine-tune to optimize the sample point of upstream data recovery

[23] watchdog_dfe RW 0x0 watchdog for restart of DFE algorithm

If the watchdog is enabled a 24 bit down counter is started after lost of downstream frame alignment.

When the countdown expires and the APIX2 device is not frame aligned the DFE algorithm restarts.

0: disable -

1: enable -


[21] up_ba RW 0x0 upstream bit alignment check for plausibil-ity, otherwise request restart of bit align-ment


1: enable - enable

[20:19] up_sp_offset RW 0x1 upstream sample point multiple of core clock after detect transitions

0: upstrem_187_5 - 187.5MBit/s upstrem

1: upstream_all other - all other upstream

2: upstream_reserved_0 - reserved_0 upstream

3: upstream_reserved_1 - reserved_1 upstream

[18] up_ba_edge RW 0x0 upstream bit alignment at falling or rising edge

0: rising - rising edge

1: falling - falling edge

[17:16] up_serial_bw RW 0x2 upstream serial bandwidth

0: apix2_187_5 - APIX2 mode 187.5 Mbit/s









[14:8] agc_coeff RW 0x20 defines the AGC coefficient

Note

this definition is not applied if the auto cal-culation of the coefficients is enabled

Important

if DownBW is set to 0b01 or 0b10 (down-stream bandwidth 500Mbit/s or 1000Mbit/s)

set the AGC coefficient to 32






APIX_CFG_3

Description: Inova Config Byte 0x10 MII clock settings,AShell2 configuration 0x0f configure audio interface, MII interface and AShell, 0x0e audio: clock synthesis controller, 0x0d pixel channel configuration, for APIX1 and APIX2





[31:30] ashell_min_bw_prio1

RW 0x0 Guaranteed minimum AShell2 bandwidth for priority group 1 data (remote access, support data)

Set to 0 for APIX1 mode.

0: res0 - residual AShell2 bandwidth, that is not used for MII/Nibble data and AShell2 generic data

1: res1_128 - 1/128 of AShell2 bandwidth

2: res1_32 - 1/32 of AShell2 bandwidth

3: res_1_8 - 1/8 of AShell2 bandwidth

[29] mii_clk_sel RW 0x0 selects one of two MII clocks


0: sel_core - select core_clk and define the mii clock fre-quencey via 'mii_clk_freq'

1: sel_mii - select mii_clk (25MHz clock from Analog Macro)

[28:24] mii_clk_freq RW 0x0 define MII clock frequency (mii_clk_sel is 0)


for the mii_fn the following formula needs to be applied F(mii) = 187.5 / (2(N+1))

[23] up_falign_opt RW 0x1 option of upstream frame alignment procedure (daisy chain mode only)

1: set_1 - set to 1

[22] down_falign_opt

RW 0x1 option of downstream frame alignment procedure

1: set_1 - set to 1

[21] audio_bw RW 0x0 audio bandwidth

0: ordinary - ordinary bandwidth

1: high - high bandwidth

[20] audio_en RW 0x0 audio interface enable

0: disable -

1: enable -

[19] audio_selfadjusten

RW 0x0 audio clock self-adjusting enable

0: disable - always adjust audio clock pulse width with config-ured initial step size

1: enable - automatic decrease/increase of step size, to strive for configured minimum step size



[18] ashell_backpressure_en

RW 0x1 ashell back pressure enable

APIX2 mode : AShell2 automatic freeze enable

APIX1 mode : APIX1 AShell automatic backpressure enable

0: disable - Caution: a disabled back pressure can cause data loss

1: enable -

[17] mii_interface_en

RW 0x0 MII/nibble interface enable

0: disable - MII/nibble interface disabled

1: enable - MII/nibble interface enabled

[16] mii_ethernet_mode

RW 0x0 MII ethernet mode

0: off - MII ethernet mode off, use MII/nibble interface to trans-fer nibble data

1: on - MII ethernet mode on, use MII/nibble interface to trans-fer ethernet packets

[15] audio_lastpulsewidth

RW 0x0 remember last pulse width, after audio buffer overrun or under-run

0: restart - restart audio clock adjustment

1: refill - refill audio buffer and remember last audio clock pulse width

[14:13] audio_minstepsize

RW 0x0 minimum step size for audio clock cycle change

0: step_5 - step size 5ps




[12:10] audio_stepsize

RW 0x0 step size for cycle time change

0: ass_250ps - AudioStepSize 250ps








[9:8] audio_selfadjust

RW 0x0 audio clock self-adjustment setting influences the step size decrease rate recommended setting : '01'

[7] ashell0_ack_en

RW 0x0 AShell0 acknowledgement of receipt

0: disable - acknowledgement disabled

1: enable - acknowledgement enabled (only if AShell2_0 ARQ is disabled)






[5] ch0_pixstartmode

RW 0x0 pixel channel 0 : start output after reset

0: asap - as soon as possible

1: first - with first pixel of a picture after rising edge of DE

[4] ch1_pixstartmode

RW 0x0 pixel channel 1 : start output after reset

0: asap - as soon as possible

1: first - with first pixel of a picture after rising edge of DE


[1] ch1_pixen RW 0x0 enable pixel channel 1 in APIX2 core


1: enable - enable

[0] ch0_pixen RW 0x1 enable pixel channel 0 in APIX2 core


1: enable - enable





Detailed description of bit field mii_clk_freq values:

0: mii_off - off

1: mii_f1 - 187.5MHz / (2(1 +1))

2: mii_f2 - 187.5MHz / (2(2 +1))

3: mii_f3 - 187.5MHz / (2(3 +1))

4: mii_f4 - 187.5MHz / (2(4 +1))

5: mii_f5 - 187.5MHz / (2(5 +1))

6: mii_f6 - 187.5MHz / (2(6 +1))

7: mii_f7 - 187.5MHz / (2(7 +1))

8: mii_f8 - 187.5MHz / (2(8 +1))

9: mii_f9 - 187.5MHz / (2(9 +1))

10: mii_f10 - 187.5MHz / (2(10+1))

11: mii_f11 - 187.5MHz / (2(11+1))

12: mii_f12 - 187.5MHz / (2(12+1))

13: mii_f13 - 187.5MHz / (2(13+1))

14: mii_f14 - 187.5MHz / (2(14+1))

15: mii_f15 - 187.5MHz / (2(15+1))

16: mii_f16 - 187.5MHz / (2(16+1))

17: mii_f17 - 187.5MHz / (2(17+1))

18: mii_f18 - 187.5MHz / (2(18+1))

19: mii_f19 - 187.5MHz / (2(19+1))

20: mii_f20 - 187.5MHz / (2(20+1))

21: mii_f21 - 187.5MHz / (2(21+1))

22: mii_f22 - 187.5MHz / (2(22+1))

23: mii_f23 - 187.5MHz / (2(23+1))

24: mii_f24 - 187.5MHz / (2(24+1))

25: mii_f25 - 187.5MHz / (2(25+1))

26: mii_f26 - 187.5MHz / (2(26+1))

27: mii_f27 - 187.5MHz / (2(27+1))

28: mii_f28 - 187.5MHz / (2(28+1))

29: mii_f29 - 187.5MHz / (2(29+1))

30: mii_2_5 - 187.5MHz / 75 = 2,5MHz

31: mii_d3 - 187.5MHz / 3



APIX_CFG_4

Description: Inova Config Byte 0x14 misc., 0x13 pixel channel config, 0x12 configuration for AShell2_0, 0x11 data channel bandwidth configuration AShell2 configuration for APIX2 MII clock settings





[31] dwn_wdfaen RW 0x0 watchdog downstream frame alignment


0: disable -

1: enable -

[30] up_wdbaen RW 0x0 watchdog upstream bit alignment


Note: If the watchdog is enabled a 24 bit down counter is started after lost of upstream frame alignment. When the countdown expires and the APIX2 device is not frame aligned the upstream bit align-ment restarts.

0: disable -

1: enable -


[28] rx_daisy_chain RW 0x0 RX daisy chain


0: disable - no daisy_chain, one Apix2 RX device connected

1: enable - daisy_chain , two Apix2 RX device connected

[27] up_lenient_dis RW 0x0 upstream lenient mode disable

tolerates a single synchronization error within a defined timing window without automatic re-synchronization


0: enable - lenient mode enabled

1: disable - lenient mode disabled



[26] dwn_lenient_dis RW 0x0 downstream lenient mode disable

tolerates a single synchronization error within a defined timing window without automatic re-synchronization




[25] pix_majcheck RW 0x1 majority check of parameters in pixel path


Note:

inoperable if bulk data mode is enabled

0: mode_2 - two equal parameters must be received consecutively to be valid

1: mode_3 - three equal parameters must be received consecutively to be valid

[24] reserved_0x14_0 RW 0x1 Set to 1 for APIX2 mode.


[23] ch1_use21 RW 0x0 use 21 of 24 Bit at pixel channel 1


Note:

To use 21 Bit out of 24, pixel data width must be set to 24 Bit. The LSBs red[0], green[0] and blue[0] are each connected to the next higher bit.

red[0] = red[1]

green[0] = green[1]

blue[0] = blue[1]

0: b24 - transmit 24 Bit pixel data


[22:21] ch1_pixwidth RW 0x0 pixel data width at pixel channel 1


Note:

To use 21 Bit out of 24, pixel data width must be set to 24 Bit.

The LSBs red[0], green[0] and blue[0] are not transmitted.

0: bpp10 - 10 Bit per Pixel








[20] ch0_use21 RW 0x0 use 21 of 24 Bit at pixel channel 0


Note:

To use 21 Bit out of 24, pixel data width must be set to 24 Bit. The LSBs red[0], green[0] and blue[0] are each connected to the next higher bit.

red[0] = red[1]

green[0] = green[1]

blue[0] = blue[1]



[19:18] ch0_pixwidth RW 0x0 pixel data width at pixel channel 0


Note:

To use 21 Bit out of 24, pixel data width must be set to 24 Bit.

The LSBs red[0], green[0] and blue[0] are not transmitted.





[17] swap_path RW 0x0 swap pixel paths


0: forward - TX0 -> RX0, TX1 -> RX1

1: swap - TX0 -> RX1, TX1 -> RX0

[16] clone_path RW 0x0 clone pixel path


0: forward - TX0 -> RX0, TX1 -> RX1

1: clone - TX0 -> RX0, TX0 -> RX1 (swap_path = forward), TX1 -> RX0, TX1 -> RX1 (swap_path = swap),

[15] ashell2_broadcasten RW 0x0 broadcast mode of AShell2_0


0: disable - broadcast mode disabled, AShell2_0 receive path extracts payload with target_id 0

1: enable - broadcast mode enabled, AShell2_0 receive path extracts payload with every target_id





[14] ashell2_linkerrortol RW 0x1 AShell link error tolerance


0: starts_realignment - AShell starts realignment after Apix2 link error, all buffers will be cleared, loss of payload data may occur

1: repeats_retransmission - AShell repeats retransmission until frame alignment, AShell transaction alignment and retrans-mission was successful, only available with ARQ enabled

[13:10] ashell2_crctocnt RW 0x9 CRC timeout counter


Reaching this threshold results in an auto-matic AShell2 transaction realignment and communication is kept alive. This is no fatal error. If the APIX link is frame aligned, the transaction alignment will be restored.

Note

Timeout only occurs, if CRC errors are consecutive. Timeout forces transaction realignment.

0: tout_0 - 0b0000 timeout disabled

1: tout_4 - 0b0001 4

2: tout_6 - 0b0010 6

3: tout_10 - 0b0011 10

4: tout_8 - 0b0100 8

5: tout_16 - 0b0101 16

6: tout_24 - 0b0110 24

7: tout_40 - 0b0111 40

8: tout_32 - 0b1000 32

9: tout_64 - 0b1001 64

10: tout_96 - 0b1010 96

11: tout_160 - 0b1011 160

12: tout_256 - 0b1100 256

13: tout_512 - 0b1101 512

14: tout_768 - 0b1110 768

15: tout_1280 - 0b1111 1280

[9] ashell2_arq_disable RW 0x0 ARQ of AShell2_0


0: enable - ARQ enable

1: disable - ARQ disable





[8] ashell2_en RW 0x1 AShell2_0 enable


0: disable - AShell2_0 disable

1: enable - AShell2_0 enable

[7] ashell2_uni RW 0x0 AShell2_0 unidirectional mode


if ARQ enabled, the AShell2 bandwidth dif-ference between upstream and down-stream (and vice versa) must not exceed the factor 4, otherwise use the divider to fall below factor 4

0: bidir - AShell2_0 operates bidirectional, APIX2 upstream is required

1: unidir - AShell2_0 operates only in downstream direction, without upstream (no error control available)

[6:5] ashell2_updiv RW 0x0 AShell2 upstream bandwidth divider


if ARQ enabled, the AShell2 bandwidth dif-ference between upstream and down-stream (and vice versa) must not exceed the factor 4, otherwise use the divider to fall below factor 4

0: div1 - divided by 1




[4:0] down_data_bw RW 0x1 totally available downstream bandwidth for AShell data, audio and GPIO.


Important

mandatory to use the same configuration for TX and RX

16: bw_1_5_mbit - 0b10000 500:1000:3000 => 1.5 MBit/s : 3 MBit/s : 9 MBit/s

8: bw_18_mbit - 0b01000 500:1000:3000 => 18 MBit/s : 37 MBit/s : 113 MBit/s








APIX_CFG_5

Description: Inova Config Byte 0x18 APIX1 config, 0x17 APIX1 sideband config, 0x16 APIX1 sideband config, 0x15 GPIO config,





[31] sbdown_validation RW 0x0 validate serial inbound AShell data with transmitted clock or with internal qualifier


0: automatic - valid with internal qualifier

1: transmitted - transmitted valid, valid with sbdown_data[1]

[30] unused_0x18_6 RW 0x1 reserved

[29] eshell RW 0x0 connect internal APIX1 PHY sideband con-nection (external ashell)


Note: if enabled the APIX1 AShell interface is not operable

0: ashell - connect internal APIX1 PHY to APIX1 AShell

1: gpio - connect internal APIX1 PHY to external sideband data through APIX1 GPIO interface

[28] spi_over_sb RW 0x0 If serial AShell data is validated with trans-mitted clock, this configuration selects between two different validation modes


downstream : sbdown_validation = 0x1

upstream : sbup_daclk = 0x2

0: full_data_mode -

1: spi_mode - Bandwidth configured by sbdown_data_cycletime



[27:24] crc_time_out_value RW 0x0 CRC timeout value, same as Ashell2_CRCToCnt


0: tout_dis - timeout disabled

1: tout_4 - CRC timeout value = 4















[23:20] sbup_data_cycletime3to0 RW 0x0 configures cycle time of sbup clock (multi-ples of 8ns) when sbup_data are asynchro-nous (sbup_data[1] is used as sbup clock). lower bits of sbup_data_cycletime.


[19] sbup_dwidth RW 0x0 AShell: enable sbup data ports


0: sbup_1_bit - 1 bit data and valid (sbup_data[0])

1: sbup_2_bit - 2 bit data (sbup_data[1:0])

[18:17] sbup_daclk RW 0x0 AShell: generate sbup clock and transmit as sbup_data[1]


0: disable_0 - disabled

1: reserved - reserved

2: enable - enabled: use clock defined at sbup_data_cycletime

3: disable_1 - disabled





[16] sbdown_dwidth RW 0x0 AShell: enable sbdown data ports


0: sbdown_1_bit - 1 bit data and valid (sbdown_data[0])

1: sbdown_2_bit - 2 bit data (sbdown_data[1:0])


[14:8] sbup_data_cycletime10to4

RW 0x0 Set to 0 for APIX2 mode.

upper bits of sbup_data_cycletime

AShell: configures cycle time of sbup clock (multiples of 8ns) when sbup_data are asynchronous (sbup_data[1] is used as sbup clock) (see also here)

14: min at 62.50 MBit/s upstream band-width

26: min at 31.25 MBit/s upstream band-width

sbup_data_cycletime10to4 sbup_data_cycletime3to0 sbup data cycle-time (multiples of 8ns)

000_0000 1110 14

... ...

111_1111 1111 2047

[7] gpio_despiking RW 0x0 GPIO despiking


0: disable -

1: enable -

[6] gpio_upbw RW 0x1 GPIO upstream bandwidth mode


0: low - low speed

1: high - high speed

[5] gpio0_upen RW 0x1 GPIO0 upstream channel enable


0: disable -

1: enable -

[4] gpio1_upen RW 0x0 GPIO1 upstream channel enable


0: disable -

1: enable -





[3] gpio0_dwnen RW 0x1 GPIO0 downstream channel enable


0: disable -

1: enable -

[2] gpio1_dwnen RW 0x0 GPIO1 downstream channel enable


0: disable -

1: enable -

[1] gpio_dwnbwmode RW 0x1 GPIO downstream bandwidth mode


Note:

Low speed GPIO downstream bandwidth unsupported if GPIO downstream band-width divider set to 1


0: low - low speed

1: high - high speed

[0] gpio_dwnbwdiv RW 0x0 GPIO downstream bandwidth divider


0: full - disabled

1: half - divide the GPIO downstream band-width by half





APIX_CFG_6

Description: Inova Config Byte 0x1C APIX1 configuration, 0x1B APIX1 configuration, 0x1A APIX1 configuration, 0x19 APIX1 AShell config,






[29:24] reserved_0x1c RW 0x6 reserved

[23:22] pixel_data_width RW 0x0 Set to 0 for APIX2 mode.





[21:20] pixel_trans_ctrl RW 0x0 APIX PHY (Soft IP): transmission of pixel controls


0: never - never

1: unused - unused

2: even - with even pixels only needed to save bandwidth

3: every - with every pixel

[19:17] reserved_0x1b_1 RW 0x7 reserved


[15] ashell1_en RW 0x0 APIX1 Ashell1 enable


0: disable -

1: enable -

[14] sbdown_clk_en RW 0x0 APIX1 sideband downstream clock enable


0: disable -

1: enable -





[11] downlenientDis RW 0x0 downstream lenient mode disable, toler-ates a single synchronization error within a defined timing window without automatic re-synchronization,





[9] ddown_enable RW 0x0 configure downstream pixel data path


0: video_mode - downstream pixel data path is used for video transmission, AShell data or GPIO transmission optional via sideband interface

1: data_mode - downstream pixel data path is used for AShell data transmission, no sideband interface available

[8] ext_sb_data_dis RW 0x0 use two internal register stages


0: ext - for external sideband data / APIX1 GPIO

1: no_ext - no external sideband data

[7:4] ashell1_window_size RW 0x0 AShell window size Window size of the retransmission protocol (number of trans-actions) supported size: 1...12


0: reset -

1: min -

12: max -

[3] ashell1_arq_disable RW 0x0 retransmission disable


0: enable -

1: disable -

[2] ashell1_suppress_idle RW 0x0 suppress idle transmission to reduce data traffic (or interrupt load if receiving Ashell is SW implementation)


0: disable -

1: enable -






APIX_CFG_8

Description: Inova Config Byte 0x24 APIX2 flow control for AShell2 generic data0x23 APIX2 core config for video0x22 APIX2 core config for audio and HDCP control (HDCP control only valid for Indigo2 withHDCP keys)






[26] hdcp_off RW 0x1 APIX2 HDCP function off

Reset value for Indigo2 ES1 is 0

0: enabled - all HDCP functions are enabled

1: off - HDCP data communication over APIX2 and video decryption are disabled

[25] stall_release RW 0x0 stall release signaling mode for AShell2_0 generic data interface


0: disable - signaling as soon as AShell2 bandwidth is available

1: enable - signaling as soon as possible

[24] flow_control RW 0x0 flow control for AShell2_0 generic data interface

Important: Flow control is only functional if acknowledgement of receipt is disabled!


0: disable -

1: enable -



[19] ch0_big_picture RW 0x0 enable big picture for channel 0 enable this option for more as 2047 active pixel per active line


0: disable -

1: enable -

[18] ch1_big_picture RW 0x0 enable big picture for channel 1 enable this option for more as 2047 active pixel per active line


0: disable -

1: enable -





[13:12] hdcp_serial_format RW 0x0 audio serial data format


0: left - left-justified mode

1: i2s - I2S mode

2: reserved - reserved

3: right - right-justified mode

[11] hdcp_tdm_order RW 0x0 TDM audio left/right channel order


0: order_0 - left0/right0/left1/right1/left2/right2/left3/right3

1: order_1 - left0/left1/left2/left3/right0/right1/right2/right3

[10] audio_frclk_pol RW 0x0 audio frclk polarity (I2S_WS signal)


0: falling - change data at falling edge

1: rising - change data at rising edge

[9] audio_bclk_pol RW 0x0 audio bclk polarity (I2S_SCLK signal)


0: left_low - 2ch: left low, right high, TDM: frame start at falling edge

1: left_high - 2ch: left high, right low, TDM: frame start at rising edge

[8] hdcp_middle RW 0x0 send hdcp support as i2c job (config only for Emerald in the middle use case)


0: disable -

1: enable -






APIX_PARAM_3

Description: Config Parameter



Table 3-267: APIX_PARAM_3 Register








APIX_CFG_VALID

Description: Inova Config Signals, resets APIX IP core



Table 3-268: APIX_CFG_VALID Register



[0] config_valid RW 0x0 enable APIX core with applied configura-tion / soft reset

0: reset - APIX core keeps in reset, only in this state reconfiguration of APIX_CFG_X is allowed, all counters are cleared

1: enabled - APIX core is enabled with applied configuration



APIX_CFG_MODE

Description: Inova Config Signals, general configuration register



Table 3-269: APIX_CFG_MODE Register



[1] apix_rx0_rx1 RW 0x0 select the device number of daisy-chained APIX2 RX devices

0: rx0 - APIX module is RX0 (directly con-nected to APIX2 TX device)

1: rx1 - APIX module is RX1 (connected to APIX2 TX device through RX0)

[0] apix_mode RW 0x1 select APIX1/APIX2 mode

Note:

only change this bit during APIX_CFG_RESET.config_valid = 0

0: apix1 - APIX module is running in APIX1 mode

1: apix2 - APIX module is running in APIX2 mode



APIX_STAT_CTRL_0

Description: Inova Status Control Signalssignals to control parts of the modules below, each of the signals needs to be active for asingle core clock cycle, all signals are high active



Table 3-270: APIX_STAT_CTRL_0 Register



[7] Reserved R0W1

0x0 -

[6:5] Reserved R0W1

0x0 -

[4] audio_clk_restart R0W1

0x0 audio clock synthesis controller restart by writing a 1

[3] Reserved R0W1

0x0 -

[2] ashell2_ta_diff_cnt_clear R0W1

0x0 clear Ticket counter difference of AShell2_0, field APIX_STAT_1.ashell2_ta_diff_cnt by writ-ing a 1,

[1] apix1_ashell_restart R0W1

0x0 Apix1 AShell restart by writing a 1, forces local transaction realignment and protocol realignment on local and remote AShell

[0] ashell2_realign R0W1

0x0 AShell2 realign by writing a 1, forces local transaction realignment and protocol realignment on local and remote AShell



APIX_STAT_CTRL_1

Description: Inova Counter Clear Signals



Table 3-271: APIX_STAT_CTRL_1 Register



[7] bist_err_cnt_clr R0W1

0x0 clear TST_STAT.prbs_err_cnt pseudo ran-dom test - error counter

[6] up_maxqual_cnt_clr R0W1

0x0 clear APIX_STAT_0.up_maxqual_cnt max-imum occurrence of upstream link qualifier

[5] ashell2_crc_err_cnt_clr R0W1

0x0 clear APIX_STAT_1.ashell2_crc_err_cnt CRC error counter of AShell2_0

[4] ashell1_crc_err_cnt_clr R0W1

0x0 clear APIX_STAT_2.apix1_ashell_crc_err_cnt Apix1 AShell CRC error counter

[3] apix1_down_err_cnt_clr R0W1

0x0 clear APIX_STAT_2.apix1_down_falign_err_cnt Apix1 downstream synchronization loss counter

[2] pll_err_cnt_clr R0W1

0x0 clear APIX_STAT_0.pll_err_cnt PLL error counter

[1] down_falign_err_cnt_clr R0W1

0x0 clear APIX_STAT_0.down_falign_err_cnt downstream frame aligned error counter

[0] up_falign_err_cnt_clr R0W1

0x0 clear APIX_STAT_0.up_falign_err_cnt upstream frame aligned error counter



APIX_STAT_TIMEOUT

Description: Inova frame alignment status



Table 3-272: APIX_STAT_TIMEOUT Register



[0] frame_alignment_timeout_detect

R 0x0 signalizes that the device wasn't frame aligned when the watchdog of frame align-ment was expired



APIX_STAT_0

Description: Inova Status Bytes 0x04 APIX2 downstream frame aligned status,0x03 APIX2 upstream frame aligned status, 0x02 upstream bit aligned status, 0x01 PLL status



Table 3-273: APIX_STAT_0 Register



[30] down_falign R 0x0 Apix2 downstream frame aligned

[29:24] down_falign_err_cnt R 0x0 downstream frame aligned error counter, stops at maximum value 63

use APIX_STAT_CTRL_1.down_falign_err_cnt_clr to clear this counter


[22] up_falign R 0x0 Apix2 upstream frame aligned (daisy chain)

[21:16] up_falign_err_cnt R 0x0 upstream frame aligned error counter (daisy chain)

stops at maximum value 63, use APIX_STAT_CTRL_1.up_falign_err_cnt_clr to clear this counter

[15] fir_ctrl_restart RW1C

0x0 fir controller restart, activated by watchdog for restart of DFE algorithm

[14] up_ba_restart RW1C

0x0 upstream bit alignment restart, activated by watchdog


[11] up_bit_aligned R 0x0 upstream bit aligned (daisy chain) deter-mined sample point for upstream data

[10:8] up_maxqual_cnt R 0x0 maximum occurrence of consecutive upstream Bit alignment faults

maximum occurrence of upstream link qualifier,use APIX_STAT_CTRL_1.up_maxqual_cnt_clr to clear


[6] pll_good R 0x0 PHY0 PLL good

[5:0] pll_err_cnt R 0x0 PHY0 PLL error counter can be reset by activating APIX_STAT_CTRL_1.pll_err_cnt_clr



APIX_STAT_1

Description: Inova Status Bytes 0x08 general status information of Apix1 AShell,0x07 CRC error counter of AShell2_0, 0x06 Ticket counter difference of AShell2_0, 0x05 general status information of AShell2_0





[31] apix1_ashell_rem_restarted

RW1C

0x0 Apix1 AShell remote ashell restarted

Remote AShell has requested transaction alignment.

[30] apix1_ashell_prot_err RW1C

0x0 Apix1 AShell protocol error

Indicates that the AShell protocol controller encountered a protocol error.

[29] apix1_ashell_crc_timeout RW1C

0x0 Apix1 AShell CRC timeout

The number of consecutively corrupted inbound transactions exceeds a configured threshold.

[28] apix1_ashell_inbound_handshake

R 0x0 Apix1 AShell inbound handshake

Local AShell performs handshake proce-dure on request of remote AShell

[27] apix1_ashell_outbound_handshake

R 0x0 Apix1 AShell outbound handshake

Local AShell performs handshake proce-dure on request of remote AShell

[26] apix1_ashell_ready R 0x0 Apix1 AShell ready for data

Indicates that the AShell is not performing any handshake procedure with remote AShell

[25] apix1_ashell_operational R 0x0 Apix1 AShell operational

When asserted, transaction alignment between local and remote AShell is estab-lished and local AShell is ready to accept transactions from application and to deliver received transactions.


[23:16] ashell2_crc_err_cnt R 0x0 CRC error counter of AShell2_0

Number of received CRC errors. The coun-ter stops at maximum value of 255. It can be reset to 0 by activating APIX_STAT_CTRL_1.ashell2_crc_err_cnt_clr



[15:8] ashell2_ta_diff_cnt R 0x0 Ticket counter difference of AShell2_0

The ticket counter presents the current dif-ference between transmitted and received transactions with application data at the transmit path. If fatal error occures, the application can ascertain a loss of payload transactions.

It can be reset to 0 by activating APIX_STAT_CTRL_0.ashell2_ta_diff_cnt_clear.

[7] ashell2_crc_err RW1C

0x0 CRC error

Incoming transaction is defective.

The distance between CRC errors depends on the AShell2 gross bandwidth and corre-sponds to the distance between AShell2 transactions. Two CRC errors cannot occur within two core clocks, there are minimum 30 core clocks between.

The mean distance in [core_clocks/trans-action] is:

(187.5*10^6[core_clocks/s] * 80[bit/trans-action] / AShell2_gross_bandwidth[bit/s])

[6] ashell2_fatal RW1C

0x0 fatal error

AShell is in illegal condition, lost transac-tions cannot be retransmitted. AShell is no longer operational and starts automatic realignment.

reasons for fatal errors can be:

* transaction loss

* APIX2 link error, if link error tolerance is configured to 0

* reception of a forbidden AShell2 intern control transaction (protocol error)

* remote AShell2 realignment

Only one fatal error can occur within an AShell2 operational state. After that, AShell2 has to become operational again, before the next fatal error may occur.





[5] ashell2_ta_loss RW1C

0x0 transaction loss

AShell2 has detected by its protocol, that more payload transactions have to be retransmitted after CRC error than avail-able in payload buffer. This event happens, if the quotient between the AShell2 upstream bandwidth and the AShell2 downstream bandwidth exceeds 4. The rule to avoid this malfunction is described here This event causes a fatal error.

Only one transaction loss error can occur within an AShell2 operational state. After that, AShell2 has to become operational again, before the next transaction loss error may occur.

[4] ashell2_prot_tx_handshake

R 0x0 protocol transmit path handshake

AShell transmit path handshakes with remote AShell transmit path.

[3] ashell2_prot_rx_handshake

R 0x0 protocol receive path handshake

AShell receive path handshakes with remote AShell transmit path.

[2] ashell2_ta_aligned R 0x0 transaction inbound aligned

Correct extraction of AShell transactions out of Apix2 frame.

[1] ashell2_operational R 0x0 AShell operational

When asserted, transaction alignment between local and remote AShell is estab-lished and local AShell is ready to accept transactions from application and to deliver received transactions.

[0] ashell2_ta_diff_cnt_valid R 0x0 ticket counter difference valid

When high, the local and remote AShell2 ticket counters are aligned.

If an AShell2 fatal error occurred because the remote APIX2 device was reset, the local and remote ticket counters are not aligned, and the ticket counter difference is not valid. The ticket counter difference must be cleared to realign the counters.





APIX_STAT_2

Description: Inova Status Bytes 0x0c pixel channel status, 0x0b pixel fifo status, helps to detect malfunctions in clock synthesis controller,0x0a APIX1 downstream frame aligned, 0x09 error status information of Apix1 AShell






[29] ch1_pix_sync_check R 0x0 pixel channel 1 synchronization marks check

if high, consecutive received synchroniza-tion marks confirmed that the pixel controls are aligned to pixel data and passed the majority check

[28] ch1_pix_param_check R 0x0 pixel channel 1 timing parameter check

if high, pixel controls are periodic and con-secutive received video timing parameter are constant and passed the majority check

[27] ch0_pix_sync_check R 0x0 pixel channel 0 synchronization marks check

if high, consecutive received synchroniza-tion marks confirmed that the pixel controls are aligned to pixel data and passed the majority check

[26] ch0_pix_param_check R 0x0 pixel channel 0 timing parameter check

if high, pixel controls are periodic and con-secutive received video timing parameter are constant and passed the majority check

[25] ch1_pix_fatal_inova RW1C

0x0 pixel channel 1, fatal error on pixel control transmission

[24] ch0_pix_fatal_inova RW1C

0x0 pixel channel 0, fatal error on pixel control transmission

[23] ch1_pix_fifoempty R 0x0 pixel channel 1 FIFO empty

[22] ch1_pix_fifofull R 0x0 pixel channel 1 FIFO full

[21] ch0_pix_fifoempty R 0x0 pixel channel 0 FIFO empty

[20] ch0_pix_fifofull R 0x0 pixel channel 0 FIFO full


[17] audio_clksyn_trouble RW1C

0x0 audio clock synthesis trouble

[16] audio_clksyn_ready R 0x0 audio clock synthesis controller ready


[14] apix1_down_frame_aligned

R 0x0 Apix1 downstream frame aligned



[13:8] apix1_down_falign_err_cnt

R 0x0 Apix1 downstream frame aligned error counter

stops at maximum value 63, it can be reset by APIX_STAT_CTRL_1.apix1_down_err_cnt_clr

[7:2] apix1_ashell_crc_err_cnt R 0x0 Apix1 AShell CRC error counter

Number of detected CRC errors (inbound transactions). The counter stops at maxi-mum value of 63. It can be reset to 0 by APIX_STAT_CTRL_1.ashell1_crc_err_cnt_clr

[1] apix1_ashell_crc_err RW1C

0x0 Apix1 AShell CRC error

Indicates CRC error of inbound transac-tions.

[0] apix1_ashell_fatal_err RW1C

0x0 Apix1 AShell fatal error

fatal error indicates that AShell encounters a condition where AShell can not deliver and receive transactions.

reasons for fatal errors are:

* CRC timeout, the number of consecutive CRC errors, defined at APIX_CFG_5.crc_time_out_value occurred

* loss of APIX frame alignment

* reception of a forbidden AShell intern control transaction (protocol error)

* remote AShell restart





APIX_STAT_4

Description: Inova Status Bytes 0x11 APIX link status,0x12 APIX link status,0x14 APIX2 generic data flow control status






[25] ashell2_0_backpressure R 0x0 This flag indicates that the flow control for AShell2_0 generic data forces a backpres-sure to the remote site. This function is only available with enabled flow control.




[11] support_inbound_full R 0x0 support inbound data

[10] ashell2_0_inbound_full R 0x0 AShell2_0 inbound data

[9] mii_full R 0x0 MII / nibble data

[8] apix1_ashell_dout_full R 0x0 APIX1 AShell data out


[1] tx_rev2_det R 0x0 status apix2 tx rev2 detected

[0] uplink_qual RW1C

0x0 upstream link qualifier threshold, config-ured at up_ba_thresh, exceeded



TST_CFG_0

Description: Inova Test Config Bytes 0x02 test modes, 0x03 audio master clock : pulse width, 0x04 audio master clock : pulse width,



Table 3-277: TST_CFG_0 Register


[31:24] audio_master_clk_width_low

RW 0x0 audio master clock : pulse width

[23:16] audio_master_clk_width_high

RW 0x0 audio master clock : pulse width


[13] audio_master_clk_mode RW 0x0 manual setting of audio master clock pulse width

0: auto - pulse width is detected and adjusted by the clock synthesis controller

1: none - setting audio master clock by configuring 16 bit pulse width at audio_master_clk_width, no pulse width detection by the clock synthesis controller, automatic adjustment can be enabled by configuration rx_dbg_data_0x02[5]

[12:11] prbs_test_8b10b RW 0x0 PRBS test 8B10B

the run length defines the number of bits until the sequence will be repeated

0: length_16_2_8 - run length 16 * 2^8 (PRBS8)




[10] prbs_test_mode RW 0x0 PRBS test mode

0: disabled - disable

1: enable - receive a pseudorandom binary sequence in downstream, the APIX2 RX synchronizes itself on this sequence and checks for errors, TX PRBS test mode must be enabled too, with the same run length





TST_STAT

Description: Inova Test Status Bytes 0x01 pseudo random test - error counter, 0x02 pseudo random test - error counter, 0x03 pseudo random test - error,



Table 3-278: TST_STAT Register




[17] prbs_sync R 0x0 pseudo random test - sync

[16] prbs_err RW1C

0x0 pseudo random test - error

[15:8] prbs_err_cnt_hi R 0x0 pseudo random test - error counter

[7:0] prbs_err_cnt_lo R 0x0 pseudo random test - error counter



DBG_STAT_4

Description: Inova Debug Data from IP



Table 3-279: DBG_STAT_4 Register



[30] dbg_rx_fir_sign_0 R 0x0

[29:24] dbg_rx_fir_coeff_0 R 0x0


[22:16] dbg_rx_agc_coeff R 0x0




DBG_STAT_5

Description: Inova Debug Data from IP,



Table 3-280: DBG_STAT_5 Register











APIX_REM_CMD_EN

Description: APIX Remote Command Inbound Enable



Table 3-281: APIX_REM_CMD_EN Register



[2] inb_ashell2_clear_ticket_counter_hwen

RW 0x0 Enable remote command request from TX: Ashell2 clear ticket counter

[1] inb_ashell2_realign_hwen

RW 0x0 Enable remote command request from TX: Ashell2 re-alignment

[0] inb_soft_reset_hwen RW 0x0 Enable remote command request from TX: Software reset



APIX_REM_CMD_REQ

Description: APIX Remote Command Request



Table 3-282: APIX_REM_CMD_REQ Register



[2] outb_ashell2_clear_ticket_counter_req

W 0x0 Request remote command to TX: Ashell2 clear ticket counter

[1] outb_ashell2_realign_req W 0x0 Request remote command to TX: Ashell2 re-alignment

[0] outb_soft_reset_req W 0x0 Request remote command to TX: Software reset



APIX_REM_CMD_STAT

Description: APIX Remote Command Status



Table 3-283: APIX_REM_CMD_STAT Register



[3] outb_req_done RW1C

0x0 Sample acknowledgement of remote com-mand request to TX




INT_STAT_LINK

Description: Interrupt Status Link 0 = Interrupt is inactive, 1 = Interrupt is active (see interrupt mapping table).



Table 3-284: INT_STAT_LINK Register



[16] int_fatal_frame_alignment_timeout_detect

RW1C

0x0 signalizes that the device wasn't frame aligned when the watchdog of frame align-ment was expired


[11] int_err_prbs RW1C

0x0 Inova Bist prbs error

[10] int_err_apix1_downreadyloss

RW1C

0x0 Loss of APIX1 downstream PHY frame alignment

[9] int_err_apix2downframealignedloss

RW1C


[8] int_err_apix1_pixalignedloss

RW1C

0x0 APIX1 Pixel stream looses alignment


[2] int_func_apix1_pixaligned

RW1C

0x0 APIX1: Pixel stream becomes aligned

[1] int_func_gpi1 RW1C

0x0 Edge detected at APIX GPI[1] port

[0] int_func_gpi0 RW1C




INT_STAT_ASHELL

Description: Interrupt Status Ashell 0 = Interrupt is inactive, 1 = Interrupt is active (see interrupt mapping table).



Table 3-285: INT_STAT_ASHELL Register



[26] int_fatal_ashell1_fatal RW1C

0x0 APIX1 Ashell Fatal Error, fatal error indi-cates that AShell encounters a condition transactions. reasons for fatal errors are: "CRC timeout, the number of consecutive CRC errors, "loss of APIX frame alignment "reception of a forbidden AShell intern con-trol transaction "remote AShell restart

[25] int_fatal_ashell1_proterr RW1C

0x0 APIX1 Ashell, Protocol Error

[24] int_fatal_ashell2_fatal RW1C

0x0 Ashell2 Fatal Error, AShell is in illegal con-dition, lost transactions cannot be retrans-mitted. AShell is no longer operational and starts automatic realignment. reasons for fatal errors are: "transaction loss "APIX2 link error, if link error tolerance is config-ured to 0 "reception of a forbidden AShell2 intern control transaction (protocol error) "remote AShell2 realignment Only one fatal error can occur within an AShell2 opera-tional state. After that, AShell2 has to become operational again, before the next fatal error may occur.


[22] int_err_ashell1_crcerror RW1C

0x0 APIX1 Ashell CRC Error, incoming trans-action is defective

[21] int_err_ashell1_crctimeout

RW1C

0x0 APIX1 Ashell, CRC Timeout, The number of consecutively corrupted inbound trans-actions exceeds a configured threshold.

[20] int_err_ashell1_remrestarted

RW1C

0x0 APIX1 Ashell, remote ashell was restarted, remote ashell has requested transaction alignment

[19] int_err_ashell2_taloss RW1C

0x0 Ashell2 Transaction loss, AShell2 has detected by its protocol, that more payload transactions have to be retransmitted after CRC error than available in payload buffer. This event happens, if the quotient between the AShell2 upstream bandwidth and the AShell2 downstream bandwidth exceeds 4. The rule to avoid this malfunc-tion is described at register field . This event causes a fatal error.



[18] int_err_ashell2_crcerror RW1C

0x0 Ashell2 CRC Error, incoming transaction is defective

[17] int_err_ashell2_unconnected

RW1C

0x0 Ashell2 looses operational state

[16] int_err_ashell1_unconnected

RW1C

0x0 APIX1 Ashell looses operational state


[9] int_func_ashell2_connected

RW1C

0x0 Ashell2 enters operational state

[8] int_func_ashell1_connected

RW1C

0x0 APIX1 Ashell enters operational state


[2] int_req_remote_inbound_ashell2_clear_ticket_counter

RW1C

0x0 Remote command clear Ashell2 ticket counter received

[1] int_req_remote_inbound_ashell2_realign

RW1C

0x0 Remote command realign Ashell2 received

[0] int_req_remote_inbound_soft_reset

RW1C

0x0 Remote command soft reset received

Table 3-285: INT_STAT_ASHELL Register




INT_STAT_PIX

Description: Interrupt Status Ashell 0 = Interrupt is inactive, 1 = Interrupt is active (see interrupt mapping table).



Table 3-286: INT_STAT_PIX Register



[9] int_fatal_ch0pixfatal RW1C

0x0 Pixel channel 0 fatal error on pixel control transmission

[8] int_fatal_ch1pixfatal RW1C



[3] int_err_ch0pixfifofull RW1C

0x0 Channel 0 Pixel FIFO is full

[2] int_err_ch0pixfifoempty RW1C

0x0 Channel 0 Pixel FIFO is empty

[1] int_err_ch1pixfifofull RW1C


[0] int_err_ch1pixfifoempty RW1C




INT_EN_LINK

Description: Interrupt Enable Link



Table 3-287: INT_EN_LINK Register



[16] int_fatal_frame_alignment_timeout_detect_en

RW 0x0 signalizes that the device wasn't frame aligned when the watchdog of frame align-ment was expired


[11] int_err_prbs_en RW 0x0 Inova Bist prbs error

[10] int_err_apix1_downreadyloss_en

RW 0x0 Loss of APIX1 downstream PHY frame alignment

[9] int_err_apix2downframealignedloss_en

RW 0x0 Loss of APIX2 downstream PHY frame alignment

[8] int_err_apix1_pixalignedloss_en

RW 0x0 APIX1 Pixel stream looses alignment


[2] int_func_apix1_pixaligned_en

RW 0x0 APIX1: Pixel stream becomes aligned

[1] int_func_gpi1_en RW 0x0 Edge detected at APIX GPI[1] port

[0] int_func_gpi0_en RW 0x0 Edge detected at APIX GPI[0] port



INT_EN_ASHELL

Description: Interrupt Enable Ashell



Table 3-288: INT_EN_ASHELL Register



[26] int_fatal_ashell1_fatal_en RW 0x0 APIX1 Ashell Fatal Error, fatal error indi-cates that AShell encounters a condition transactions. reasons for fatal errors are: "CRC timeout, the number of consecutive CRC errors, "loss of APIX frame alignment "reception of a forbidden AShell intern con-trol transaction "remote AShell restart

[25] int_fatal_ashell1_proterr_en

RW 0x0 APIX1 Ashell, Protocol Error

[24] int_fatal_ashell2_fatal_en RW 0x0 Ashell2 Fatal Error, AShell is in illegal con-dition, lost transactions cannot be retrans-mitted. AShell is no longer operational and starts automatic realignment. reasons for fatal errors are: "transaction loss "APIX2 link error, if link error tolerance is config-ured to 0 "reception of a forbidden AShell2 intern control transaction (protocol error) "remote AShell2 realignment Only one fatal error can occur within an AShell2 opera-tional state. After that, AShell2 has to become operational again, before the next fatal error may occur.


[22] int_err_ashell1_crcerror_en

RW 0x0 APIX1 Ashell CRC Error, incoming trans-action is defective

[21] int_err_ashell1_crctimeout_en

RW 0x0 APIX1 Ashell, CRC Timeout, The number of consecutively corrupted inbound trans-actions exceeds a configured threshold.

[20] int_err_ashell1_remrestarted_en

RW 0x0 APIX1 Ashell, remote ashell was restarted, remote ashell has requested transaction alignment

[19] int_err_ashell2_taloss_en RW 0x0 Ashell2 Transaction loss, AShell2 has detected by its protocol, that more payload transactions have to be retransmitted after CRC error than available in payload buffer. This event happens, if the quotient between the AShell2 upstream bandwidth and the AShell2 downstream bandwidth exceeds 4. The rule to avoid this malfunc-tion is described at register field . This event causes a fatal error.

[18] int_err_ashell2_crcerror_en

RW 0x0 Ashell2 CRC Error, incoming transaction is defective



[17] int_err_ashell2_unconnected_en

RW 0x0 Ashell2 looses operational state

[16] int_err_ashell1_unconnected_en

RW 0x0 APIX1 Ashell looses operational state


[9] int_func_ashell2_connected_en

RW 0x0 Ashell2 enters operational state

[8] int_func_ashell1_connected_en

RW 0x0 APIX1 Ashell enters operational state


[2] int_req_remote_inbound_ashell2_clear_ticket_counter_en

RW 0x0 Remote command clear Ashell2 ticket counter received

[1] int_req_remote_inbound_ashell2_realign_en

RW 0x0 Remote command realign Ashell2 received

[0] int_req_remote_inbound_soft_reset_en

RW 0x0 Remote command soft reset received

Table 3-288: INT_EN_ASHELL Register




INT_EN_PIX

Description: Interrupt Enable Ashell



Table 3-289: INT_EN_PIX Register



[9] int_fatal_ch0pixfatal_en RW 0x0 Pixel channel 0 fatal error on pixel control transmission

[8] int_fatal_ch1pixfatal_en RW 0x0 Pixel channel 1 fatal error on pixel control transmission


[3] int_err_ch0pixfifofull_en RW 0x0 Channel 0 Pixel FIFO is full

[2] int_err_ch0pixfifoempty_en

RW 0x0 Channel 0 Pixel FIFO is empty

[1] int_err_ch1pixfifofull_en RW 0x0 Channel 1 Pixel FIFO is full

[0] int_err_ch1pixfifoempty_en

RW 0x0 Channel 1 Pixel FIFO is empty



INT_SET_LINK

Description: Interrupt Set Link



Table 3-290: INT_SET_LINK Register



[16] int_fatal_frame_alignment_timeout_detect_set

R0W1

0x0 signalizes that the device wasn't frame aligned when the watchdog of frame align-ment was expired


[11] int_err_prbs_set R0W1

0x0 Inova Bist prbs error

[10] int_err_apix1_downreadyloss_set

R0W1


[9] int_err_apix2downframealignedloss_set

R0W1


[8] int_err_apix1_pixalignedloss_set

R0W1

0x0 APIX1 Pixel stream looses alignment


[2] int_func_apix1_pixaligned_set

R0W1

0x0 APIX1: Pixel stream becomes aligned

[1] int_func_gpi1_set R0W1


[0] int_func_gpi0_set R0W1




INT_SET_ASHELL

Description: Interrupt Set Ashell



Table 3-291: INT_SET_ASHELL Register



[26] int_fatal_ashell1_fatal_set

R0W1

0x0 APIX1 Ashell Fatal Error, fatal error indi-cates that AShell encounters a condition transactions. reasons for fatal errors are: "CRC timeout, the number of consecutive CRC errors, "loss of APIX frame alignment "reception of a forbidden AShell intern con-trol transaction "remote AShell restart

[25] int_fatal_ashell1_proterr_set

R0W1

0x0 APIX1 Ashell, Protocol Error

[24] int_fatal_ashell2_fatal_set

R0W1

0x0 Ashell2 Fatal Error, AShell is in illegal con-dition, lost transactions cannot be retrans-mitted. AShell is no longer operational and starts automatic realignment. reasons for fatal errors are: "transaction loss "APIX2 link error, if link error tolerance is config-ured to 0 "reception of a forbidden AShell2 intern control transaction (protocol error) "remote AShell2 realignment Only one fatal error can occur within an AShell2 opera-tional state. After that, AShell2 has to become operational again, before the next fatal error may occur.


[22] int_err_ashell1_crcerror_set

R0W1

0x0 APIX1 Ashell CRC Error, incoming trans-action is defective

[21] int_err_ashell1_crctimeout_set

R0W1

0x0 APIX1 Ashell, CRC Timeout, The number of consecutively corrupted inbound trans-actions exceeds a configured threshold.

[20] int_err_ashell1_remrestarted_set

R0W1

0x0 APIX1 Ashell, remote ashell was restarted, remote ashell has requested transaction alignment

[19] int_err_ashell2_taloss_set

R0W1

0x0 Ashell2 Transaction loss, AShell2 has detected by its protocol, that more payload transactions have to be retransmitted after CRC error than available in payload buffer. This event happens, if the quotient between the AShell2 upstream bandwidth and the AShell2 downstream bandwidth exceeds 4. The rule to avoid this malfunc-tion is described at register field . This event causes a fatal error.

[18] int_err_ashell2_crcerror_set

R0W1

0x0 Ashell2 CRC Error, incoming transaction is defective



[17] int_err_ashell2_unconnected_set

R0W1

0x0 Ashell2 looses operational state

[16] int_err_ashell1_unconnected_set

R0W1

0x0 APIX1 Ashell looses operational state


[9] int_func_ashell2_connected_set

R0W1

0x0 Ashell2 enters operational state

[8] int_func_ashell1_connected_set

R0W1

0x0 APIX1 Ashell enters operational state


[2] int_req_remote_inbound_ashell2_clear_ticket_counter_set

R0W1

0x0 Remote command clear Ashell2 ticket counter received

[1] int_req_remote_inbound_ashell2_realign_set

R0W1

0x0 Remote command realign Ashell2 received

[0] int_req_remote_inbound_soft_reset_set

R0W1

0x0 Remote command soft reset received

Table 3-291: INT_SET_ASHELL Register




INT_SET_PIX

Description: Interrupt Set Pixel



Table 3-292: INT_SET_PIX Register



[9] int_fatal_ch0pixfatal_set R0W1


[8] int_fatal_ch1pixfatal_set R0W1



[3] int_err_ch0pixfifofull_set R0W1


[2] int_err_ch0pixfifoempty_set

R0W1


[1] int_err_ch1pixfifofull_set R0W1


[0] int_err_ch1pixfifoempty_set

R0W1





3.2.3 AShell Remote Handler Register Overview


Base Address(es)Instance no 0: BASEADDR0="00022000"Instance no 1: BASEADDR1="00024000"


BASEADDRx + 0x0000 RH_CTRL Remote Handler Control Register

BASEADDRx + 0x0004 RH_STAT Remote Handler Status Register

BASEADDRx + 0x0008 RESET_CTRL Reset Control Register

BASEADDRx + 0x000C AHBM_LOCK AHB Master Lock Register

BASEADDRx + 0x0010 BASE_ADDR_WRITE Base Address Register for Write Message

BASEADDRx + 0x0014 BASE_ADDR_READ Base Address Register for Read Message

BASEADDRx + 0x0018 BASE_ADDR_EVENT Base Address Register for Event and Push Message

BASEADDRx + 0x001C FIFO_THRESH_VAL FIFO Threshold Register

BASEADDRx + 0x0020 FIFO_STAT FIFO Status Register

BASEADDRx + 0x0024 RH_IRQ_EN Remote Handler Interrupt Enable

BASEADDRx + 0x0028 Reserved Do not modify

BASEADDRx + 0x002C MAILBOX Send an event message to the host

BASEADDRx + 0x0030 PUSH_MODE Push Mode Register

BASEADDRx + 0x0034 PUSH_MSG Push Message Data

BASEADDRx + 0x0038 PUSH_INDEX Setup the index identifier of push message

BASEADDRx + 0x003C PUSH_TYPE Setup the type of the push message

BASEADDRx + 0x0040 PUSH_TID PUSH message target ID setup

BASEADDRx + 0x0044 ASHELL_FLUSH AShell Message Flush

BASEADDRx + 0x0048 EVENT_STAT0 Event Status Register 0

BASEADDRx + 0x004C EVENT_STAT1 Event Status Register 1




BASEADDRx + 0x005C EVENT_STAT5 Event Status Register 5



BASEADDRx + 0x0068 EVENT_EN0 Event Enable Register 0

BASEADDRx + 0x006C EVENT_EN1 Event Enable Register 1




BASEADDRx + 0x007C EVENT_EN5 Event Enable Register 5



BASEADDRx + 0x0088 AHB_WRERR_ADDR AHB Write-Error Address Register

BASEADDRx + 0x008C AHB_RDERR_ADDR AHB Read-Error Address Register

BASEADDRx + 0x0400 EVENT_MSG_TABLE Event Lookup Table


RH_CTRL

Description: Remote Handler Control Register


Instance no 0: 0x00022000Instance no 1: 0x00024000

Table 3-294: RH_CTRL Register


[31] init_start R0W1

0x0 Remote Handler (Event Lookup Table) ini-tialization trigger

0: triggered - sequence already started, check RH_STAT.init_done flag

1: trigger - start sequence to initialize the event lookup table


[21:16] outb_deliv_cnt RW 0x3F Remote Handler delivery resent value before dropping the message.


[13] outb_deliv_en RW 0x0 Remote Handler takes care of delivery han-dling. ARQ of AShell is disabled.

0: arq - AShell using automatic retransmis-sion

1: deliv - Retransmission is controlled by remote handler

[12] outb_tout_en RW 0x0 Outbound timeout enable

0: ntout - Outbound interface waits until acknowledge from AShell

1: tout - Outbound interface waits until acknowledge from AShell or timeout

[11:10] push_tid_en RW 0x0 Set outbound target ID of push messages (AShell2)

0: push_apix - use target ID configuration from APIX

1: push_tid0 - push message forwarded to target ID 0

2: push_tid1 - push message forwarded to target ID 1

3: push_tid01 - push message forwarded as specified per push-message group 'PUSH_TID'



[9:8] event_tid_en RW 0x0 Set outbound target ID of event messages (AShell2)

0: event_apix - use target ID configuration from APIX

1: event_tid0 - event message forwarded to target ID 0

2: event_tid1 - event message forwarded to target ID 1

3: event_tid01 - event message forwarded as specified in event table 'irq_msg_table'

[7:6] tx_tid_en RW 0x0 Set outbound target ID of read responses (AShell2)

0: tx_apix - use target ID configuration from APIX

1: tx_tid0 - transmit with target ID =0

2: tx_tid1 - transmit with target ID =1

3: tx_tid01 - transmit with target ID as it was requested from

[5:4] rx_tid_en RW 0x0 Filter inbound data, based on target ID (AShell2)

0: rx_apix - use target ID configuration from APIX

1: rx_tid0 - receive data with target ID =0 only

2: rx_tid1 - receive data with target ID =1 only

3: rx_tid01 - receive data with target ID =0 and =1

[3] push_en RW 0x0 Enable push message

Note: set also 'event_en' to enable push message

0: disable - push message are disabled

1: enable - push message are enabled

[2] event_en RW 0x0 Enable event message

0: disable - event message are disabled

1: enable - event message are enabled

[1] auto_clear_en RW 0x0 Enable auto-clear of event status

0: self - event status will be cleared by SW

1: auto - event status will be auto-cleared be remote handler after message sent

[0] rh_en RW 0x0 Enable Remote Handler

0: disable - no remote handler functionality

1: enable - remote handler enabled=

Table 3-294: RH_CTRL Register




RH_STAT

Description: Remote Handler Status Register



Table 3-295: RH_STAT Register


[31] init_done R 0x0 Remote Handler initialization done, access to event lookup table is allowed if this flag is done

0: ongoing - initialization ongoing

1: done - initialization done (remote handler ready to configure)


[0] push_block_end RW1C

0x0 End of push message block transfer detected



RESET_CTRL

Description: Reset Control Register



Table 3-296: RESET_CTRL Register



[0] sw_reset R0W1

0x0 Remote handler software reset



AHBM_LOCK

Description: AHB Master Lock Register


Instance no 0: 0x0002200CInstance no 1: 0x0002400C

Table 3-297: AHBM_LOCK Register


[31] lock RW 0x1 Lock AHB write requests

Note: Already received AHB transaction are processed. Incoming write requests are dropped (except write-unlock).

0: unlocked - AHB write operations are enabled

1: locked - AHB write operations are dis-abled


[19:0] unlock_pattern RW 0xFFFFF This unlock_pattern is checked against field AShell_DownstreamUnlock.AddrKey of an incoming AShell message



BASE_ADDR_WRITE

Description: Base Address Register for Write Message



Table 3-298: BASE_ADDR_WRITE Register



[11:0] base_addr_write RW 0x0 base address, MSBs (upper 12 bit) of a 32bit AHB write Address

if AShell message flag 'oa' is set, then AHBWriteAddr = BaseAddr + MessageOff-setAddr



BASE_ADDR_READ

Description: Base Address Register for Read Message



Table 3-299: BASE_ADDR_READ Register



[11:0] base_addr_read RW 0x0 base address, MSBs (upper 12 bit) of a 32bit AHB read Address

if AShell message flag 'oa' is set, then AHBReadAddr = BaseAddr + MessageOff-setAddr



BASE_ADDR_EVENT

Description: Base Address Register for Event and Push Message



Table 3-300: BASE_ADDR_EVENT Register



[11:0] base_addr_event RW 0x0 base address, MSBs (upper 12 bit) of a 32bit AHB read Address

if AShell message flag 'oa' is set, then AHBEventReadAddr = BaseAddr + Messa-geOffsetAddr



FIFO_THRESH_VAL

Description: FIFO Threshold Register



Table 3-301: FIFO_THRESH_VAL Register



[12:8] tx_thresh_val RW 0x10 Specifies the threshold of the transmit mes-sage FIFO


[4:0] rx_thresh_val RW 0x10 Specifies the threshold of the receive mes-sage FIFO



FIFO_STAT

Description: FIFO Status Register



Table 3-302: FIFO_STAT Register



[14:9] push_level R 0x0 FIFO level (number of messages)

[8] push_empty R 0x0 Push block message FIFO empty status

0: nempty - transmit FIFO not empty

1: empty - transmit FIFO empty


[3] tx_thresh R 0x0 Transmit FIFO threshold status

0: below - FIFO level is below threshold

1: above - FIFO level is above threshold

[2] rx_thresh R 0x0 Receive FIFO threshold status

0: below - FIFO level is below threshold

1: above - FIFO level is above threshold

[1] tx_empty R 0x1 Transmit FIFO is empty

0: nempty - transmit FIFO not empty

1: empty - transmit FIFO empty

[0] rx_empty R 0x1 Receive FIFO is empty status

0: nempty - receive FIFO not empty

1: empty - receive FIFO empty



RH_IRQ_EN

Description: Remote Handler Interrupt Enable



Table 3-303: RH_IRQ_EN Register



[11] irq_t_tout_en RW 0x0 TX interrupt enable TCTRL timeout (loss of message)

[10] irq_t_ovl_en RW 0x0 TX interrupt enable TX-fifo overflow (loss of message)

[9] irq_t_thresh_en RW 0x0 TX interrupt enable TX-fifo threshold reached

[8] irq_r_ovl_en RW 0x0 RX interrupt enable RX-fifo overflow (loss of message)

[7] irq_r_thresh_en RW 0x0 RX interrupt enable RX-fifo threshold reached

[6] irq_r_wrlock_en RW 0x0 RX interrupt enable receive write message while locked

[5] irq_b_werr_en RW 0x0 AHB write error interrupt enable

[4] irq_b_rerr_en RW 0x0 AHB read error interrupt enable

[3] irq_c_push_ack_en RW 0x0 Push message acknowledge interrupt enable

[2] irq_c_push_req_en RW 0x0 Push message request interrupt enable

[1] irq_c_mail_ack_en RW 0x0 Mailbox message acknowledge interrupt enable

[0] irq_c_mail_req_en RW 0x0 Mailbox message request interrupt enable



MAILBOX

Description: Send an event message to the host



Table 3-304: MAILBOX Register


[31:0] mail_data RW 0x0 An upstream event message with this pay-load will be sent to the host.



PUSH_MODE

Description: Push Mode Register



Table 3-305: PUSH_MODE Register


[31] push_block_start R0W1

0x0 Initiate transfer of of Push Message within Block transfer mode


[7:2] push_block_length RW 0x8 Length of push message within block trans-fer mode

Note: max. block length is 32


[0] push_block_mode RW 0x0 Push Message Mode

0: single - Single transfer mode

1: block - Block transfer mode



PUSH_MSG

Description: Push Message Data



Table 3-306: PUSH_MSG Register


[31:0] push_data RW 0x0 Push message data

If push_block_mode equals 'single' reads and writes a register

If push_block_mode equals 'block' reads and writes a FIFO.

A read during block transfer mode will remove a message from the FIFO.



PUSH_INDEX

Description: Setup the index identifier of push message



Table 3-307: PUSH_INDEX Register



[7:0] push_idx RW 0x0 Push message index



PUSH_TYPE

Description: Setup the type of the push message



Table 3-308: PUSH_TYPE Register



[2:0] push_type RW 0x0 push_type[2] ... SOF

push_type[1] ... EOF

push_type[0] ... DATA

Send a SOF push message to the host, PushType=0b101

Send a DATA push message to the host, PushType=0b001

Send an EOF push message to the host, PushType=0b011

PushType=0b000 is reserved for the event message



PUSH_TID

Description: PUSH message target ID setup



Table 3-309: PUSH_TID Register


[31:0] push_tid RW 0x0 Define Target ID for push messages

push_tid[ i] ... target ID for messages (i*8+0) up to (i*8+7)



ASHELL_FLUSH

Description: AShell Message Flush



Table 3-310: ASHELL_FLUSH Register



[2] flush_pusheof RW 0x0 Generate flush for every end of frame push message.

For all other push messages, no flush will be generated.

[1] flush_event RW 0x0 Generate flush for every event message.

[0] flush_request_last RW 0x0 Generate flush for the last AShell message requested.



EVENT_STAT0

Description: Event Status Register 0



Table 3-311: EVENT_STAT0 Register


[31:0] event_stat_0 RW1C

0x0 Status of event 31..0



EVENT_STAT1










EVENT_STAT2










EVENT_STAT3










EVENT_STAT4










EVENT_STAT5










EVENT_STAT6










EVENT_STAT7










EVENT_EN0

Description: Event Enable Register 0



Table 3-319: EVENT_EN0 Register


[31:0] event_en_0 RW 0x0 Enable of event 31..0



EVENT_EN1









EVENT_EN2









EVENT_EN3









EVENT_EN4









EVENT_EN5









EVENT_EN6









EVENT_EN7









AHB_WRERR_ADDR

Description: AHB Write-Error Address Register



Table 3-327: AHB_WRERR_ADDR Register


[31:0] ahb_wr_err_addr R 0x0 Address of the last internal active AHB write transaction.

This register is update in case of a wrong AHB bus write transaction initialized by remote handler.

Note: This register is not updated in case of a missaligned ASHELL write transaction.



AHB_RDERR_ADDR

Description: AHB Read-Error Address Register



Table 3-328: AHB_RDERR_ADDR Register


[31:0] ahb_rd_err_addr R 0x0 Address of the last internal active AHB read transaction.

This register is update in case of a wrong AHB bus read transaction initialized by remote handler



EVENT_MSG_TABLE

Description: Event Lookup Table



Table 3-329: EVENT_MSG_TABLE Register



[24] event_msg_flush RW 0x0 Flush

0: disable - Flush disabled

1: enable - Flush enabled

[23] event_msg_target RW 0x0 Taget ID

0: ashell2_0 - Forward this event to target ID 0

1: ashell2_1 - Forward this event to target ID 1

[22] event_msg_oa RW 0x0 Offset Address Enable

0: disable - Use 'envent_msg_addr' as an absolute address

1: enable - Use 'event_msg_addr' as an offset address to the base address 'ba_read'

[21:20] event_msg_size RW 0x3 access type for event message

0: byte - read byte 8-bit

1: halfword - read half word 16-bit

2: word - read word 32-bit

3: noacc - no read access for this event message

[19:0] event_msg_addr RW 0x0 read address for event message




3.2.4 APIX2 HDCP Register Overview

NOTE Please be aware, that this section is only valid for MB88F334 ’Indigo2’ and not functional for MB88F33x ’Indigo2-N’and MB88F33x ’Indigo2-S’.




BASEADDR + 0x0000 CFG_HDCP HDCP configuration signals


BASEADDR + 0x0008 CTRL_HDCP_0 HDCP control signals

BASEADDR + 0x000C STATUS_HDCP_0 HDCP status signals

BASEADDR + 0x0010 STATUS_HDCP_1 HDCP status signals
















BASEADDR + 0x0050 INT_STAT_HDCP Interrupt Status HDCP

BASEADDR + 0x0054 INT_EN_HDCP Interrupt Enable HDCP

BASEADDR + 0x0058 INT_SET_HDCP Interrupt Set HDCP


CFG_HDCP

Description: HDCP configuration signals



Table 3-331: CFG_HDCP Register



[1] repeater_mode RW 0x0 Enables repeater mode when the device is part of an HDCP repeater

0: disable -

1: enable -

[0] aud_support RW 0x0 Enables response to the transmitter that audio is supported as part of the HDCP processing

0: disable -

1: enable -



CTRL_HDCP_0

Description: HDCP control signals



Table 3-332: CTRL_HDCP_0 Register



[12] req_reauth RW 0x0 Triggers the function of replying with a default Ri and Pj such that the TX will detect the error and re-start authentication. The function is active until the TX sends an AKSV update, even though this bit self-clears instantaneously

[11] repeater_topo_max_cascade_exceeded

RW 0x0 Only applicable in repeater mode, other-wise it should remain zero. Defines the MAX_CASCADE_EXCEEDED field of the repeater topology for Bstatus

[10:8] repeater_topo_depth RW 0x0 Only applicable in repeater mode, other-wise it should remain zero. Defines the DEPTH field of the repeater topology for Bstatus

[7] repeater_topo_max_devs_exceeded

RW 0x0 Only applicable in repeater mode, other-wise it should remain zero. Defines the MAX_DEVS_EXCEEDED field of the repeater topology for Bstatus

[6:0] repeater_topo_device_count

RW 0x0 Only applicable in repeater mode, other-wise it should remain zero. Defines the DEVICE_COUNT field of the repeater topology for Bstatus



STATUS_HDCP_0

Description: HDCP status signals



Table 3-333: STATUS_HDCP_0 Register


[31:24] pj_vid R 0x0 HDCP protocol value

[23:16] ri_vid_hi R 0x0 HDCP protocol value

[15:8] ri_vid_lo R 0x0 HDCP protocol value


[3] lv_expired_err R 0x0 Flag which indicates that when generating a new Ri and Pj, the previous Ri or Pj val-ues have not been read by the TX. This is an indication that something is probably wrong with the current encryption and quite possibly the content is unrecoverable and should be muted to prevent unconfortable picture and sound. However, it is the TX task to detect errors and re-start authenti-cation if needed.

[2] key_storage_err R 0x0 Flags an error related to the HDCP key storage: Bksv not ready before it was requested by the remote transmitter?s authentication process, or the complete HDCP Key set was not swept in time before the TX checked Ro (100ms from Aksv update)

[1] encrypted_aud R 0x0 Flags high when detecting encrypted audio frames

[0] encrypted_vid R 0x0 Flags high when detecting encrypted video frames



STATUS_HDCP_1






[31:24] ainfo R 0x0 HDCP protocol value

[23:16] pj_aud R 0x0 HDCP protocol value

[15:8] ri_aud_hi R 0x0 HDCP protocol value

[7:0] ri_aud_lo R 0x0 HDCP protocol value



STATUS_HDCP_2






[31:24] an_vid_3 R 0x0 HDCP protocol value






STATUS_HDCP_3












STATUS_HDCP_4






[31:24] an_aud_3 R 0x0 HDCP protocol value






STATUS_HDCP_5












STATUS_HDCP_6







[23:16] bstatus_hi R 0x0 HDCP protocol value

[15:8] bstatus_lo R 0x0 HDCP protocol value

[7:0] bcaps R 0x0 HDCP protocol value



STATUS_HDCP_7






[31:24] bksv_3 R 0x0 HDCP protocol value






STATUS_HDCP_8










STATUS_HDCP_9






[31:24] aksv_3 R 0x0 HDCP protocol value






STATUS_HDCP_10










STATUS_HDCP_11






[31:24] sha_hash_3 R 0x0 HDCP protocol value






STATUS_HDCP_12












STATUS_HDCP_13






[31:24] sha_hash_b R 0x0 HDCP protocol value

[23:16] sha_hash_a R 0x0 HDCP protocol value





STATUS_HDCP_14






[31:24] sha_hash_f R 0x0 HDCP protocol value

[23:16] sha_hash_e R 0x0 HDCP protocol value

[15:8] sha_hash_d R 0x0 HDCP protocol value

[7:0] sha_hash_c R 0x0 HDCP protocol value



STATUS_HDCP_15












INT_STAT_HDCP

Description: Interrupt Status HDCP 0 = Interrupt is inactive, 1 = Interrupt is active (see interrupt mapping table).



Table 3-349: INT_STAT_HDCP Register



[9] int_err_lv_expired RW1C

0x0 Flag which indicates that when generating a new Ri and Pj, the previous Ri or Pj val-ues have not been read by the TX. This is an indication that something is probably wrong with the current encryption and quite possibly the content is unrecoverable and should be muted to prevent unconfortable picture and sound. However, it is the TX task to detect errors and re-start authenti-cation if needed.

[8] int_err_key_storage RW1C

0x0 Flags an error related to the HDCP key storage: Bksv not ready before it was requested by the remote transmitter?s authentication process, or the complete HDCP Key set was not swept in time before the TX checked Ro (100ms from Aksv update)


[2] int_func_aksv_update RW1C

0x0 Flag which indicates an AKSV update

[1] int_func_enrypt_aud RW1C

0x0 Flags high when detecting encrypted audio frames

[0] int_func_enrypt_vid RW1C

0x0 Flags high when detecting encrypted video frames



INT_EN_HDCP

Description: Interrupt Enable HDCP



Table 3-350: INT_EN_HDCP Register



[9] int_err_lv_expired_en RW 0x0 Enable int_err_lv_expired

[8] int_err_key_storage_en RW 0x0 Enable int_err_key_storage


[2] int_func_aksv_update_en RW 0x0 Enable int_func_aksv_update

[1] int_func_enrypt_aud_en RW 0x0 Enable int_func_enrypt_aud

[0] int_func_enrypt_vid_en RW 0x0 Enable int_func_enrypt_vid



INT_SET_HDCP

Description: Interrupt Set HDCPFor debugging



Table 3-351: INT_SET_HDCP Register



[9] int_err_lv_expired_set W 0x0 Set int_err_lv_expired

[8] int_err_key_storage_set W 0x0 Set int_err_key_storage


[2] int_func_aksv_update_set

W 0x0 Set int_func_aksv_update

[1] int_func_enrypt_aud_set W 0x0 Set int_func_enrypt_aud

[0] int_func_enrypt_vid_set W 0x0 Set int_func_enrypt_vid




3.2.5 Embedded Ethernet Register Overview




BASEADDR + 0x0000 LOCK Key Register for Lock and Unlock

BASEADDR + 0x0004 LOCK_STAT Lock Status Register

BASEADDR + 0x0008 ENABLE Enable Register

BASEADDR + 0x000C RESET_CTRL Reset Control Register

BASEADDR + 0x0010 CLEAR_CNT Clear Error Counter Register

BASEADDR + 0x0014 RX_CNT_0 RX Error Counter 0 (total of dropped frames)

BASEADDR + 0x0018 RX_CNT_1 RX Error Counter 1

BASEADDR + 0x001C RX_CNT_2 RX Error Counter 2



BASEADDR + 0x0028 TX_CNT_0 Transmit Counter Register 0

BASEADDR + 0x002C TX_CNT_1 Transmit Counter Register 1

BASEADDR + 0x0030 SW_FLUSH Software Transmit Trigger Register

BASEADDR + 0x0034 HOST0_TRIG_CTRL Transmit Trigger for Host 0 Register

BASEADDR + 0x0038 HOST0_TRIG_VAL Trigger Values for Host 0 Register

BASEADDR + 0x003C HOST1_TRIG_CTRL Transmit Trigger for Host 0 Register

BASEADDR + 0x0040 HOST1_TRIG_VAL Trigger Values for Host 0 Register

BASEADDR + 0x0044 IRQ_EN E2IP Interrupt Enable


BASEADDR + 0x004C COMMON_CTRL Common Control/Mode Register

BASEADDR + 0x0050 TX_RX_TARGETID APIX Channel Destination Register

BASEADDR + 0x0054 TX_CFG Transmitter Config Register

BASEADDR + 0x0058 CLIENT_MAC_LO E2IP Client MAC Address Register

BASEADDR + 0x005C CLIENT_MAC_HI E2IP Client MAC Address Register

BASEADDR + 0x0060 CLIENT_MAC_VLAN E2IP Client MAC VLAN Register

BASEADDR + 0x0064 CLIENT_IP E2IP Client IP Address Register

BASEADDR + 0x0068 CLIENT_UDP_PORT E2IP Client UDP Port Register

BASEADDR + 0x006C CLIENT_RPC_MSGID E2IP Client RPC Message-ID Register

BASEADDR + 0x0070 CLIENT_RPC_ID E2IP Client RPC ID Register

BASEADDR + 0x0074 CLIENT_RPC_MISC E2IP Client RPC Header Register

BASEADDR + 0x0078 HOST_MAC_VLD Host MAC Address Validation Register

BASEADDR + 0x007C HOST0_MAC_LO E2IP Host 0 MAC Address Register

BASEADDR + 0x0080 HOST0_MAC_HI E2IP Host 0 MAC Address Register

BASEADDR + 0x0084 HOST0_IP E2IP Host 0 IP Address Register

BASEADDR + 0x0088 HOST0_IP_TTL E2IP Host 0 IP Time-to-live Register

BASEADDR + 0x008C HOST0_UDP E2IP Host 0 UDP Port Register

BASEADDR + 0x0090 HOST0_RPC_MSGID E2IP Host 0 RPC Message-ID Register

BASEADDR + 0x0094 HOST0_RPC_ID E2IP Host 0 RPC ID Register

BASEADDR + 0x0098 HOST0_RPC_MISC E2IP Host 0 RPC Header Register

BASEADDR + 0x009C HOST1_MAC_LO E2IP Host 1 Mac Address Register

BASEADDR + 0x00A0 HOST1_MAC_HI E2IP Host 1 Mac Address Register

BASEADDR + 0x00A4 HOST1_IP E2IP Host 1 IP Address Register

BASEADDR + 0x00A8 HOST1_IP_TTL E2IP Host 1 IP Time-to-life Register

BASEADDR + 0x00AC HOST1_UDP E2IP Host 1 UDP Port Register

BASEADDR + 0x00B0 HOST1_RPC_MSGID E2IP Host 1 RPC Message-ID Register

BASEADDR + 0x00B4 HOST1_RPC_ID E2IP Host 1 RPC ID Register

BASEADDR + 0x00B8 HOST1_RPC_MISC E2IP Host 1 RPC Header Register


LOCK

Description: Key Register for Lock and Unlock



Table 3-353: LOCK Register


[31:0] key W 0x0 Write the lock or unlock key to this register field

0x00000000: default - Value after reset

0xc0cac01a: unlock - Unlock pattern

0x1fedbeef: lock - Lock pattern



LOCK_STAT

Description: Lock Status Register



Table 3-354: LOCK_STAT Register



[0] lock_stat R 0x1 The lock status can be read back from this field

0: unlocked - Host and Client registers are unlocked

1: locked - Host and Client registers are locked



ENABLE

Description: Enable Register



Table 3-355: ENABLE Register



[0] e2ip_en RW 0x0 Enable E2IP core functionality

0: disable - Disable E2IP functionality

1: enable - Enable E2IP functionality



RESET_CTRL

Description: Reset Control Register



Table 3-356: RESET_CTRL Register



[0] sw_reset R0W1

0x0 E2IP software reset



CLEAR_CNT

Description: Clear Error Counter Register



Table 3-357: CLEAR_CNT Register



[6] clr_tx_cnt_1 R0W1

0x0 Clear TX_CNT_1

[5] clr_tx_cnt_0 R0W1

0x0 Clear TX_CNT_0

[4] clr_rx_cnt_4 R0W1

0x0 Clear RX_CNT_4


0x0 Clear RX_CNT_3


0x0 Clear RX_CNT_2


0x0 Clear RX_CNT_1


0x0 Clear RX_CNT_0



RX_CNT_0

Description: RX Error Counter 0 (total of dropped frames)



Table 3-358: RX_CNT_0 Register



[15:0] rx_total_dropped R 0x0 Total number of dropped frames.



RX_CNT_1

Description: RX Error Counter 1





[31:16] rx_rpc_dropped R 0x0 Number of frames which could not be han-dled at the AUTOSAR (RPC) layer

The frame shall be a UDP frame, with valid IP addresses of host 0 or host 1, checksum for IP and Ethernet correct

[15:0] rx_invalid_udp R 0x0 Number of frames received with valid IP addressing, but invalid UDP destination port




RX_CNT_2







[15:0] rx_fielderr_dropped R 0x0 Number of frames which could not be han-dled due to field errors within IP header.


IP header fields checked: IP.TOS, IP.ID, IP.FLAGS, IP.OFFSET



RX_CNT_3






[31:16] rx_arp_icmp_dropped R 0x0 Number of dropped frames which could not be stored due to ARP/ICMP-RAM full sta-tus.

[15:0] rx_ashell_dropped R 0x0 Number of dropped frames which could not be stored due to RXFIFO full status.



RX_CNT_4






[31:16] rx_mac1_updates R 0x0 Number of changes to Host 1 MAC address

[15:0] rx_mac0_updates R 0x0 Number of changes to Host 0 MAC address



TX_CNT_0

Description: Transmit Counter Register 0



Table 3-363: TX_CNT_0 Register


[31:16] tx_mac1_dropped R 0x0 Number of dropped frames which could not be sent because the E2IP Host1 MAC address was unknown

[15:0] tx_mac0_dropped R 0x0 Number of dropped frames which could not be sent because the E2IP Host0 MAC address was unknown



TX_CNT_1

Description: Transmit Counter Register 1



Table 3-364: TX_CNT_1 Register



[15:0] tx_resent_dropped R 0x0 Number of dropped frames which could not be sent because the re-sent limit has been reached



SW_FLUSH

Description: Software Transmit Trigger Register



Table 3-365: SW_FLUSH Register



[1] host1_sw_flush R0W1

0x0 Trigger to transmit remaining messages within transmit path

0: keep - Keep content of transmit path FIFOs

1: flush - Flush content of transmit path FIFOs

[0] host0_sw_flush R0W1

0x0 Trigger to transmit remaining messages within transmit path

0: keep - Keep content of transmit path FIFOs

1: flush - Flush content of transmit path FIFOs



HOST0_TRIG_CTRL

Description: Transmit Trigger for Host 0 Register



Table 3-366: HOST0_TRIG_CTRL Register



[2] host0_ext_en RW 0x0 Flush TX FIFO on external trigger

0: disable - Disable flush on external trigger

1: enable - Enable flush on external trigger

[1] host0_thresh_en RW 0x0 Flush TX FIFO at defined threshold

Note: Flush always if max. frame size is reached

0: disable - E2IP transmits only max. frame size

1: enable - E2IP transmits using threshold mode

[0] host0_interval_en RW 0x0 Flush TX FIFO at regular intervals



1: enable - E2IP transmits using interval mode



HOST0_TRIG_VAL

Description: Trigger Values for Host 0 Register



Table 3-367: HOST0_TRIG_VAL Register


[31:24] host0_thresh RW 0x80 Threshold value in number of bytes. If equal or above the threshold a packet shall be framed and transmitted


[21:0] host0_interval RW 0x0 Interval Max Counter value [HCLK]

Note: The lower 5-bits are ignored inter-nally.



HOST1_TRIG_CTRL

Description: Transmit Trigger for Host 0 Register



Table 3-368: HOST1_TRIG_CTRL Register



[2] host1_ext_en RW 0x0 Flush TX FIFO on external trigger

0: disable - Disable flush on external trigger

1: enable - Enable flush on external trigger

[1] host1_thresh_en RW 0x0 Flush TX FIFO at defined threshold



1: enable - E2IP transmits using threshold mode

[0] host1_interval_en RW 0x0 Flush TX FIFO at regular intervals



1: enable - E2IP transmits using interval mode



HOST1_TRIG_VAL

Description: Trigger Values for Host 0 Register



Table 3-369: HOST1_TRIG_VAL Register


[31:24] host1_thresh RW 0x80 Threshold value in number of bytes. If equal or above the threshold a packet shall be framed and transmitted


[21:0] host1_interval RW 0x0 Interval Max Counter value [HCLK]

Note: The lower 5-bits are ignored inter-nally.



IRQ_EN

Description: E2IP Interrupt Enable



Table 3-370: IRQ_EN Register



[4] irq_mac1_update_en RW 0x0 Host 1 MAC address update interrupt enable

[3] irq_mac0_update_en RW 0x0 Host 0 MAC address update interrupt enable

[2] irq_rx_overwrite_en RW 0x0 RX overwrite interrupt enable

RX has detected an overwrite of a previous ethernet frame which was not processed completely

[1] irq_tx_drop_en RW 0x0 TX frame dropped interrupt enable

Transmitter side has dropped an ethernet frame or part of the payload.

Refer to TX_CNT_0 to TX_CNT1

[0] irq_rx_drop_en RW 0x0 RX frame dropped interrupt enable

Receiver side has dropped an ethernet frame or part of the payload.

Refer to RX_CNT_0 to RX_CNT3



COMMON_CTRL

Description: Common Control/Mode Register



Table 3-371: COMMON_CTRL Register



[30] mac_learn RW 0x0 Mode of MAC address learning

0: ip - learn host MAC if, matching E2IP src-IP, ARP-request, ARP-response

1: ip_udp - learn host MAC if, matching E2IP src-IP, dest-IP, dest-UDP.port, ARP-response

[29] eth_tagged RW 0x0 Ethernet frame format

0: untagged - Untagged ethernet frames

1: tagged - Tagged ethernet frames

[28:27] tx_duplex_mode RW 0x1 Transmitter duplex mode

0: full - Full duplex transmission

1: shared - Shared medium (e.g. APIX with daisy chain)

2: half - Half duplex transmission

3: resv - Reserved

[26] arp_en RW 0x1 Enable ARP Protocol

0: disable - ARP protocol disabled

1: enable - ARP protocol enabled

[25] icmp_en RW 0x1 Enable ICMP Protocol

0: disable - ICMP protocol disabled

1: enable - ICMP protocol enabled


[23:0] arp_tout RW 0x1F ARP timeout value [time reference = mii_clk]

E2IP client initiates ARP, if timeout and (active) E2IP Host's MAC address are unknown.



TX_RX_TARGETID

Description: APIX Channel Destination RegisterSet register to is 0xD for MII communications.



Table 3-372: TX_RX_TARGETID Register



[3:2] rx_target_sel RW 0x3 Define the target ID (selector) of all receive transactions

Set to 0x3 for MII communications.

Reset value for Indigo2 ES1 is 0.

0: rx_apix - Use target ID configuration from APIX

1: rx_tid0 - Receive with target ID =0

2: rx_tid1 - Receive with target ID =1

3: rx_tid01 - Receive with target ID =0 or ID=1

[1:0] tx_target_sel RW 0x1 Define the target ID (selector) of all transmit transactions

Set to 0x1 for MII communications.

Reset value for Indigo2 ES1 is 0.

0: tx_apix - Use target ID configuration from APIX

1: tx_tid0 - Transmit with target ID =0

2: tx_tid1 - Transmit with target ID =1

3: tx_tidr - Reserved



TX_CFG

Description: Transmitter Config Register



Table 3-373: TX_CFG Register



[9:8] tx_host_sel RW 0x0 Select to which host RPC frames are trans-mitted.

0: to_requestor - Transmit frames as requested

1: to_host_0 - Transmit all frames to host 0

2: to_host_1 - Transmit all frames to host 1

3: reserved - Reserved

[7:0] tx_resent RW 0x4 Number of resends to be attempted before dropping the message

Maximum allowed number is 126.



CLIENT_MAC_LO

Description: E2IP Client MAC Address Register



Table 3-374: CLIENT_MAC_LO Register


[31:0] client_mac_lo RW 0x0 E2IP MAC Address (lower bits)

Note: client_mac_lo is updated with a write to client_mac_hi



CLIENT_MAC_HI

Description: E2IP Client MAC Address Register



Table 3-375: CLIENT_MAC_HI Register



[15:0] client_mac_hi RW 0x0 E2IP MAC Address (higher bits)



CLIENT_MAC_VLAN

Description: E2IP Client MAC VLAN Register



Table 3-376: CLIENT_MAC_VLAN Register


[31:29] client_vlanprio RW 0x0 MAC VLAN priority

[28] client_vlancfi RW 0x0 MAC VLAN canonical format indicator

[27:16] client_vlanid RW 0x49 MAC VLAN identifier

[15:0] client_tpid RW 0x8100 MAC VLAN tag protocol identifier



CLIENT_IP

Description: E2IP Client IP Address Register



Table 3-377: CLIENT_IP Register


[31:0] client_ip RW 0x0 E2IP Client IP Address



CLIENT_UDP_PORT

Description: E2IP Client UDP Port Register



Table 3-378: CLIENT_UDP_PORT Register



[15:0] client_udp_port RW 0x0 E2IP UDP Port



CLIENT_RPC_MSGID

Description: E2IP Client RPC Message-ID Register



Table 3-379: CLIENT_RPC_MSGID Register


[31:0] client_rpc_msgid RW 0x0 Message-ID



CLIENT_RPC_ID

Description: E2IP Client RPC ID Register



Table 3-380: CLIENT_RPC_ID Register


[31:16] client_rpc_sid RW 0x0 Session-ID

[15:0] client_rpc_id RW 0x0 Client-ID



CLIENT_RPC_MISC

Description: E2IP Client RPC Header Register



Table 3-381: CLIENT_RPC_MISC Register


[31:24] client_rpc_code RW 0x0 Return code

[23:16] client_rpc_msgtyp RW 0x0 Message type

[15:8] client_rpc_ifvers RW 0x0 Interface version

[7:0] client_rpc_protvers RW 0x0 Protocol version



HOST_MAC_VLD

Description: Host MAC Address Validation Register



Table 3-382: HOST_MAC_VLD Register



[1] host1_mac_vld R 0x0 Validates the MAC address of Host 1

0: drop - The MAC address of Host 1 is unknown, the E2IP client will drop trans-mission requests

1: vld - The MAC address of Host 1 has been learned.

[0] host0_mac_vld R 0x0 Validates the MAC address of Host 0

0: drop - The MAC address of Host 0 is unknown, the E2IP client will drop trans-mission requests

1: vld - The MAC address of Host 0 has been learned.



HOST0_MAC_LO

Description: E2IP Host 0 MAC Address Register



Table 3-383: HOST0_MAC_LO Register


[31:0] host0_mac_lo RW 0x0 E2IP MAC Address (lower bits)

Note: host0_mac_lo is updated with a write to host0_mac_hi

Note: While writing the host MAC address, it becomes validated



HOST0_MAC_HI

Description: E2IP Host 0 MAC Address Register



Table 3-384: HOST0_MAC_HI Register



[15:0] host0_mac_hi RW 0x0 E2IP MAC Address (higher bits)



HOST0_IP

Description: E2IP Host 0 IP Address Register



Table 3-385: HOST0_IP Register


[31:0] host0_ip RW 0x0 E2IP Host IP Address



HOST0_IP_TTL

Description: E2IP Host 0 IP Time-to-live Register



Table 3-386: HOST0_IP_TTL Register



[7:0] host0_ttl RW 0x1 Time-to-live



HOST0_UDP

Description: E2IP Host 0 UDP Port Register



Table 3-387: HOST0_UDP Register



[15:0] host0_udp_port RW 0x0 Host 0 UDP Port



HOST0_RPC_MSGID

Description: E2IP Host 0 RPC Message-ID Register



Table 3-388: HOST0_RPC_MSGID Register


[31:0] host0_rpc_msgid RW 0x0 Message-ID



HOST0_RPC_ID

Description: E2IP Host 0 RPC ID Register



Table 3-389: HOST0_RPC_ID Register


[31:16] host0_rpc_sid RW 0x0 Session-ID

[15:0] host0_rpc_id RW 0x0 Host-ID



HOST0_RPC_MISC

Description: E2IP Host 0 RPC Header Register



Table 3-390: HOST0_RPC_MISC Register


[31:24] host0_rpc_code RW 0x0 Return-Code

[23:16] host0_rpc_msgtyp RW 0x0 Message Type

[15:8] host0_rpc_ifvers RW 0x0 Interface-Version

[7:0] host0_rpc_protvers RW 0x0 Protocol-Version



HOST1_MAC_LO

Description: E2IP Host 1 Mac Address Register



Table 3-391: HOST1_MAC_LO Register


[31:0] host1_mac_lo RW 0x0 E2IP Mac Address (lower bits)

Note: host1_mac_lo gets updated with a write to host1_mac_hi

Note: While writing the host MAC address, it becomes validated



HOST1_MAC_HI

Description: E2IP Host 1 Mac Address Register



Table 3-392: HOST1_MAC_HI Register



[15:0] host1_mac_hi RW 0x0 E2IP Mac Address (higher bits)



HOST1_IP

Description: E2IP Host 1 IP Address Register



Table 3-393: HOST1_IP Register


[31:0] host1_ip RW 0x0 E2IP Host IP Address



HOST1_IP_TTL

Description: E2IP Host 1 IP Time-to-life Register



Table 3-394: HOST1_IP_TTL Register



[7:0] host1_ttl RW 0x1 Time-to-life



HOST1_UDP

Description: E2IP Host 1 UDP Port Register



Table 3-395: HOST1_UDP Register



[15:0] host1_udp_port RW 0x0 Host 1 UDP Port



HOST1_RPC_MSGID

Description: E2IP Host 1 RPC Message-ID Register



Table 3-396: HOST1_RPC_MSGID Register


[31:0] host1_rpc_msgid RW 0x0 Message-ID



HOST1_RPC_ID

Description: E2IP Host 1 RPC ID Register



Table 3-397: HOST1_RPC_ID Register


[31:16] host1_rpc_sid RW 0x0 Session-ID

[15:0] host1_rpc_id RW 0x0 Host-ID



HOST1_RPC_MISC

Description: E2IP Host 1 RPC Header Register



Table 3-398: HOST1_RPC_MISC Register


[31:24] host1_rpc_code RW 0x0 Return-Code

[23:16] host1_rpc_msgtyp RW 0x0 Message Type

[15:8] host1_rpc_ifvers RW 0x0 Interface-Version

[7:0] host1_rpc_protvers RW 0x0 Protocol-Version




3.3 HS_SPI Interface Registers

In this section, the ‘Register Overview’ table summarizes all HS-SPI registers, including base addressof the module and name, description, and the absolute address of each register, which are thendescribed separately in the following tables.


3.3.1 High-speed SPI Interface Register Overview


Base Address(es)Instance no 0: BASEADDR0="00026000"Instance no 1: BASEADDR1="000B1000"


BASEADDRx + 0x0000 MCTRL HS_SPI Module Control Register

BASEADDRx + 0x0004 PCC0HS_SPI Peripheral Communication Configuration Register 0


BASEADDRx + 0x000C PCC2HS_SPI Peripheral Communication Configuration Register 2


BASEADDRx + 0x0014 TXF HS_SPI TX Interrupt Flag Register

BASEADDRx + 0x0018 TXE HS_SPI TX Interrupt Enable Register

BASEADDRx + 0x001C TXC HS_SPI TX Interrupt Clear Register

BASEADDRx + 0x0020 RXF HS_SPI RX Interrupt Flag Register

BASEADDRx + 0x0024 RXE HS_SPI RX Interrupt Enable Register

BASEADDRx + 0x0028 RXC HS_SPI RX Interrupt Clear Register

BASEADDRx + 0x002C FAULTF HS_SPI Fault Interrupt Flag Register

BASEADDRx + 0x0030 FAULTC HS_SPI Fault Interrupt Clear Register

BASEADDRx + 0x0034 DMCFG HS_SPI Direct Mode Configuration Register

BASEADDRx + 0x0035 DMDMAEN HS_SPI Direct Mode DMA Enable Register

BASEADDRx + 0x0036 SVCFG0 Supervision Config Register 0

BASEADDRx + 0x0037 SVCFG1 Supervision Config Register 1

BASEADDRx + 0x0038 DMSTART HS_SPI Direct Mode Start Register

BASEADDRx + 0x0039 DMSTOP HS_SPI Direct Mode Stop Register

BASEADDRx + 0x003A DMPSEL HS_SPI Direct Mode Peripheral Select Register

BASEADDRx + 0x003B DMTRP HS_SPI Direct Mode Transfer Protocol Register

BASEADDRx + 0x003C DMBCC HS_SPI Direct Mode Byte Count Control Register

BASEADDRx + 0x003E DMBCS HS_SPI Direct Mode Byte Count Status Register

BASEADDRx + 0x0040 DMSTATUS HS_SPI Direct Mode Status Register

BASEADDRx + 0x0044 TXBITCNT HS_SPI Transmit Bit Count Register

BASEADDRx + 0x0045 RXBITCNT HS_SPI Receive Bit Count Register

BASEADDRx + 0x0046 RXSHIFT HS_SPI RX Shift Register

BASEADDRx + 0x004A FIFOCFG HS_SPI FIFO Configuration Register

BASEADDRx + 0x004E TXFIFO0 HS_SPI TX-FIFO Registers 0

BASEADDRx + 0x0052 TXFIFO1 HS_SPI TX-FIFO Registers 1


BASEADDRx + 0x005A TXFIFO3 HS_SPI TX-FIFO Registers 3















BASEADDRx + 0x008E RXFIFO0 HS_SPI RX-FIFO Registers 0

BASEADDRx + 0x0092 RXFIFO1 HS_SPI RX-FIFO Registers 1

BASEADDRx + 0x0096 RXFIFO2 HS_SPI RX-FIFO Registers 2

BASEADDRx + 0x009A RXFIFO3 HS_SPI RX-FIFO Registers 3

BASEADDRx + 0x009E RXFIFO4 HS_SPI RX-FIFO Registers 4

BASEADDRx + 0x00A2 RXFIFO5 HS_SPI RX-FIFO Registers 5

BASEADDRx + 0x00A6 RXFIFO6 HS_SPI RX-FIFO Registers 6

BASEADDRx + 0x00AA RXFIFO7 HS_SPI RX-FIFO Registers 7

BASEADDRx + 0x00AE RXFIFO8 HS_SPI RX-FIFO Registers 8

BASEADDRx + 0x00B2 RXFIFO9 HS_SPI RX-FIFO Registers 9

BASEADDRx + 0x00B6 RXFIFO10 HS_SPI RX-FIFO Registers 10

BASEADDRx + 0x00BA RXFIFO11 HS_SPI RX-FIFO Registers 11

BASEADDRx + 0x00BE RXFIFO12 HS_SPI RX-FIFO Registers 12

BASEADDRx + 0x00C2 RXFIFO13 HS_SPI RX-FIFO Registers 13

BASEADDRx + 0x00C6 RXFIFO14 HS_SPI RX-FIFO Registers 14

BASEADDRx + 0x00CA

RXFIFO15 HS_SPI RX-FIFO Registers 15

BASEADDRx + 0x00CE

CSCFG HS_SPI Command Sequencer Configuration Register

BASEADDRx + 0x00D2 CSITIME HS_SPI Command Sequencer Idle Time Register

BASEADDRx + 0x00D6 CSAEXT HS_SPI Command Sequencer Address Extension Register

BASEADDRx + 0x00DA

RDCSDC0HS_SPI Read Command Sequence Data/Control Register 0

BASEADDRx + 0x00DC


BASEADDRx + 0x00DE


BASEADDRx + 0x00E0 RDCSDC3HS_SPI Read Command Sequence Data/Control Register 3





BASEADDRx + 0x00EA WRCSDC0HS_SPI Write Command Sequence Data/Control Register 0

BASEADDRx + 0x00EC

WRCSDC1HS_SPI Write Command Sequence Data/Control Register 1

BASEADDRx + 0x00EE WRCSDC2HS_SPI Write Command Sequence Data/Control Register 2

BASEADDRx + 0x00F0 WRCSDC3HS_SPI Write Command Sequence Data/Control Register 3










BASEADDRx + 0x00FA MID HS_SPI Module ID Register






MCTRL

Description: HS_SPI Module Control Register


Instance no 0: 0x00026000Instance no 1: 0x000B1000

Table 3-400: MCTRL Register



[4] MES R 0x0 Module Enable Status

'0': Module is completely disabled and it has entered the power saving mode

'1': Module is enabled

[3] CDSS RW 0x0 Clock Division Source Select

When HSSPI is in master mode, the inter-nal clock divider can divide either the AHB clock (i.e. iHCLK) or the peripheral clock (i.e. iPCLK). The CDSS bit decides which clock is divided by the clock divider. This field is not used in slave mode.

'0': Clock divider divides the iHCLK

'1': Clock divider divides the iPCLK


[1] CSEN RW 0x0 Command Sequencer Enable

'0': Direct mode is enabled. Command sequencer is disabled

'1': Command sequencer is enabled. Direct mode is disabled

Note: To check whether the command sequencer mode is available in a particular device, refer to the device specific data-sheet. If command sequencer is not avail-able in the device, the CSEN bit is read-only and its value is '0'.



[0] MEN RW 0x0 Module Enable

'0': Module is disabled. The HSSPI module enters power saving mode. All serial I/O signals are tri-stated by the HSSPI

'1': Module is enabled

After configuring the HSSPI, the software must set this bit to '1' to enable the HSSPI in operating mode.

When the software resets this bit:

a) In direct mode - As a master the HSSPI stops further SPI transfers after the slave select is released (if it is already asserted). As a slave, HSSPI does not respond to any SPI transfers after the slave select is released (if it is already asserted). After the slave select is released, it internally enters a power saving mode, by gating the iHCLK and the iPCLK clocks to some of its internal logic blocks.

b) In command sequencer mode - The HSSPI generates an unmapped memory access fault interrupt if any further AHB access to memory mapped devices are received. It does not initiate any commands on the serial interface. After the slave select has been released, it internally enters power saving mode by gating the iHCLK and the iPCLK clocks to some of its internal logic blocks.

Table 3-400: MCTRL Register




PCC0

Description: HS_SPI Peripheral Communication Configuration Register 0



Table 3-401: PCC0 Register



[16] SAFESYNC RW 0x1 Safe Synchronisation for Peripheral 0

This bit is valid only when the HSSPI is configured as an SPI master in direct mode or command sequencer mode.

'0': The module operates normally. Pre-determined delay for safe synchronisation of data is not added by HSSPI during the serial transfers

'1': The module implements the safe syn-chronisation of data while serial communi-cation with peripheral '0' is taking place

[15:9] CDRS RW 0x0 Clock Division Ratio Select of Peripheral 0

When the HSSPI is configured as an SPI master in direct mode or in command sequencer mode, this field decides the clock division ratio of the internal clock divider. This field is not used when the HSSPI is configured in SPI slave mode.

0: Reserved

1: Divide by 2

2: Divide by 4

3: Divide by 6

...

127: Divide by 254

In general, for a non-zero value of CDRS, the source clock frequency (i.e. Fi) is divided by twice the CDRS value, to get the derived clock frequency (i.e. Fo).

Fo = Fi/(2 x CDRS)

The value of the CDRS bit should be cho-sen such that the resultant serial clock fre-quency is not more than the frequency of the AHB clock.




[7] SDIR RW 0x0 Shift Direction of Peripheral 0

The SDIR bit decides the bit transmission order within a field. It bit does not affect the position of the most significant bit and least significant bit in the data registers. Read or write access to data registers always has the least significant bit in bit'0'.

'0': Most significant bit is transmitted first

'1': Least significant bit is transmitted first

[6:5] SS2CD RW 0x0 Slave-Select to Clock Delay of Peripheral 0

This bit is used only when the HSSPI is configured as an SPI master in direct mode or in command sequencer mode.

It defines a setup time for the slave device. By delaying the toggling of SCLK, the HSSPI delays the data transmission (of the slave) from the chip select active edge by a multiple of SCLK cycles.

If HSSPIn_PCC0~3:CPHA = '0', the delay between assertion of slave select and the first edge on the SCLK is given by:

(SS2CD + 3 + 0.5) number of clock periods of SCLK.


(SS2CD + 3) number of clock periods of SCLK.

When the slave select becomes active, the slave has to prepare the data transfer within the delay time defined by the SS2CD bits.

[4] SSPOL RW 0x0 Slave Select Polarity of Peripheral 0

This bit is used to decide the polarity of the slave select (i.e. SSEL0) signal.

'0': SSEL0 is held high during the default state. The signal is active low

'1': SSEL0 is held low during the default state. The signal is active high

This bit must not be changed while the module is enabled (i.e. HSSPIn_MCTRL:MES='1').





[3] RTM RW 0x0 Use Retimed Clock for Capturing the Data from Peripheral 0

This bit must be set to '1' if the serial device interfaced with the HSSPI provides tight setup or hold margins to the HSSPI. This bit takes effect only when the HSSPI is configured as an SPI master in direct mode or command sequencer mode.

'0': Do not use the retimed clock to capture the serial data

'1': Use the retimed clock to capture the serial data

The HSSPIn_PCC0:CPHA, HSSPIn_PCC0:CPOL, HSSPIn_PCC0:ACES and RTM bits together decide the clocking mode of the HSSPI serial interface.

[2] ACES RW 0x0 Active Clock Edges are Same on Periph-eral 0

This bit decides whether the active edges of the clock used for launching and captur-ing data are same or opposite. This bit takes effect only when the HSSPI is config-ured as an SPI master in direct mode or in command sequencer mode.

'0': Launching and capturing of data are done on alternate (i.e. opposite) clock edges

'1': Launching and capturing of data are done on the same clock edges

The HSSPIn_PCC0:CPHA, HSSPIn_PCC0:CPOL, ACES, and HSSPIn_PCC0:RTM bits together decide the clocking mode of HSSPI serial inter-face.

Do not set ACES to '1' if HSSPIn_DMTRP:TRP is '0000'.

[1] CPOL RW 0x0 Clock Polarity of Peripheral 0

'0': SCLK is held low during its default state

'1': SCLK is held high during its default state

The HSSPIn_PCC0:CPHA, CPOL, HSSPIn_PCC0:ACES, and HSSPIn_PCC0:RTM bits together decide the clocking mode of the HSSPI serial inter-face.





[0] CPHA RW 0x0 Clock Phase of Peripheral 0

'0': Input data are sampled on odd num-bered edges of the serial clock

'1': Input data are sampled on even num-bered edges of the serial clock

The CPHA, HSSPIn_PCC0:CPOL, HSSPIn_PCC0:ACES and HSSPIn_PCC0:RTM bits together decide the clocking mode of the HSSPI serial inter-face.





PCC1













0: Reserved

1: Divide by 2

2: Divide by 4

3: Divide by 6

...

127: Divide by 254


Fo = Fi/(2 x CDRS)





















This bit must not be changed while the HSSPI module is enabled (i.e. HSSPIn_MCTRL:MES='1').











This bit decides whether the active edges of the clock used for launching and captur-ing data are same or opposite.




Do not set ACES to '1' if HSSPIn_DMTRP:TRP is '0000'.









PCC2



Instance no 0: 0x0002600CInstance no 1: 0x000B100C










0: Reserved

1: Divide by 2

2: Divide by 4

3: Divide by 6

...

127: Divide by 254


Fo = Fi/(2 x CDRS)












If HSSPIn_PCC0~3:CPHA = '0', the delay between assertion of slave select and first edge on the SCLK is given by:


If HSSPIn_PCC0~3:CPHA = '1', the delay between assertion of slave select and first edge on the SCLK is given by:












'0': Output data is driven one half serial clock cycle before the first edge of the serial clock and on subsequent even num-bered edges of the serial clock

'1': Output data is driven on odd numbered edges of the serial clock






PCC3













0: Reserved

1: Divide by 2

2: Divide by 4

3: Divide by 6

...

127: Divide by 254


Fo = Fi/(2 x CDRS)





TXF

Description: HS_SPI TX Interrupt Flag Register



Table 3-405: TXF Register



[11] SVSPI3 R 0x0 Supervision of SPI3 TX output showed an error.

This interrupt flag triggers the TX interrupt signal, if it is enabled in HSSPIn_TXE:SVSPI3.








[6] TSSRS R 0x0 Slave Select Released

This interrupt flag indicates that the slave select line has been released by the SPI master.

This interrupt flag triggers the TX interrupt signal, if it is enabled in HSSPIn_TXE:TSSRE.

[5] TFMTS R 0x0 TX-FIFO Fill Level is More Than Threshold

This interrupt flag is set with every AHB clock if the TX-FIFO fill level is more than the configured TX-FIFO threshold value.

i.e. HSSPIn_DMSTATUS:TXFLEVEL is greater than HSSPIn_FIFOCFG:TXFTH.

This interrupt flag triggers the TX interrupt signal if it is enabled in HSSPIn_TXE:TFMTE.



[4] TFLETS R 0x0 TX-FIFO Fill Level is Less Than or Equal to Threshold

This interrupt flag is set with every AHB clock if the TX-FIFO fill level is less than or equal to the configured TX-FIFO threshold value.

i.e. HSSPIn_DMSTATUS:TXFLEVEL is less than or equal to HSSPIn_FIFOCFG:TXFTH.

This interrupt flag triggers the TX interrupt signal if it is enabled in HSSPIn_TXE:TFLETE.

[3] TFUS R 0x0 TX-FIFO Underrun

This interrupt flag indicates that the TX-FIFO is underrun.

The TX-FIFO underrun condition happens when TX-FIFO is read by the SPI core while empty. This condition may happen during the slave mode of operation.

This interrupt flag triggers the TX interrupt signal if it is enabled in HSSPIn_TXE:TFUE.

[2] TFOS R 0x0 TX-FIFO Overrun

This interrupt flag indicates that the TX-FIFO is overrun.

The TX-FIFO overrun condition happens when HSSPIn_TXFIFO0~15 register is written to by the software while the TX-FIFO is full.

This interrupt flag triggers the TX interrupt signal if it is enabled in HSSPIn_TXE:TFOE.

[1] TFES R 0x0 TX-FIFO and Shift Register is Empty

This interrupt flag is set with every AHB clock, if the TX-FIFO and the TX shift regis-ter (in the SPI core) are empty.

This interrupt flag triggers the TX interrupt signal if it is enabled in HSSPIn_TXE:TFEE.

[0] TFFS R 0x0 TX-FIFO Full

This interrupt flag is set with every AHB clock if the TX-FIFO is full.

This interrupt flag triggers the TX interrupt signal if it is enabled in HSSPIn_TXE:TFFE.

Table 3-405: TXF Register




TXE

Description: HS_SPI TX Interrupt Enable Register



Table 3-406: TXE Register



[11] SVSPI3 RW 0x0 SPI3 TX supervision Interrupt Enable.

This bit decides whether the HSSPIn_TXF:SVSPI3 interrupt flag is routed on TX interrupt signal or not.

'0': The HSSPIn_TXF:SVSPI3 interrupt flag does not trigger the TX interrupt signal '1': The HSSPIn_TXF:SVSPI3 interrupt flag triggers the TX interrupt signal

'1': The HSSPIn_TXF:SVSPI3 interrupt flag triggers the TX interrupt signal











'0': The HSSPIn_TXF:SVSPI0 interrupt flag does not trigger the TX interrupt signal





[6] TSSRE RW 0x0 Slave Select Released Interrupt Enable

This bit decides whether or not the HSSPIn_TXF:TSSRS interrupt flag is routed on the TX interrupt signal.

'0': The HSSPIn_TXF:TSSRS interrupt flag does not trigger the TX interrupt signal

'1': The HSSPIn_TXF:TSSRS interrupt flag triggers the TX interrupt signal

[5] TFMTE RW 0x0 TX-FIFO Fill Level is More Than Threshold Interrupt Enable

This bit decides whether or not the HSSPIn_TXF:TFMTS interrupt flag is routed on the TX interrupt signal.

'0': The HSSPIn_TXF:TFMTS interrupt flag does not trigger the TX interrupt signal

'1': The HSSPIn_TXF:TFMTS interrupt flag triggers the TX interrupt signal

[4] TFLETE RW 0x0 TX-FIFO Fill Level is Less Than or Equal To Threshold Interrupt Enable

This bit decides whether or not the HSSPIn_TXF:TFLETS interrupt flag is routed on the TX interrupt signal.

'0': The HSSPIn_TXF:TFLETS interrupt flag does not trigger the TX interrupt signal

'1': The HSSPIn_TXF:TFLETS interrupt flag triggers the TX interrupt signal

[3] TFUE RW 0x0 TX-FIFO Underrun Interrupt Enable

This bit decides whether or not the HSSPIn_TXF:TFUS interrupt flag is routed on the TX interrupt signal.

'0': The HSSPIn_TXF:TFUS interrupt flag does not trigger the TX interrupt signal

'1': The HSSPIn_TXF:TFUS interrupt flag triggers the TX interrupt signal

[2] TFOE RW 0x0 TX-FIFO Overrun Interrupt Enable

This bit decides whether or not the HSSPIn_TXF:TFOS interrupt flag is routed on the TX interrupt signal.

'0': The HSSPIn_TXF:TFOS interrupt flag does not trigger the TX interrupt signal

'1': The HSSPIn_TXF:TFOS interrupt flag triggers the TX interrupt signal





[1] TFEE RW 0x0 TX-FIFO Empty Interrupt Enable

This bit decides whether or not the HSSPIn_TXF:TFES interrupt flag is routed on the TX interrupt signal.

'0': The HSSPIn_TXF:TFES interrupt flag does not trigger the TX interrupt signal

'1': The HSSPIn_TXF:TFES interrupt flag triggers the TX interrupt signal

[0] TFFE RW 0x0 TX-FIFO Full Interrupt Enable

This bit decides whether or not the HSSPIn_TXF:TFFS interrupt flag is routed on the TX interrupt signal.

'0': The HSSPIn_TXF:TFFS interrupt flag does not trigger the TX interrupt signal

'1': The HSSPIn_TXF:TFFS interrupt flag triggers the TX interrupt signal





TXC

Description: HS_SPI TX Interrupt Clear Register



Table 3-407: TXC Register



[11] SVSPI3 R0W1

0x0 SPI3 TX supervision Interrupt Clear.

This bit is used to clear the HSSPIn_TXF:SVSPI3 interrupt flag.

'0': No effect

'1': Clears the HSSPIn_TXF:SVSPI3 inter-rupt flag

Read returns '0'.

[10] SVSPI2 R0W1



'0': No effect


Read returns '0'.

[9] SVSPI1 R0W1



'0': No effect


Read returns '0'.

[8] SVSPI0 R0W1



'0': No effect


Read returns '0'.


[6] TSSRC R0W1

0x0 Slave Select Released Interrupt Clear

This bit is used to clear the HSSPIn_TXF:TSSRS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_TXF:TSSRS inter-rupt flag

Read returns '0'.



[5] TFMTC R0W1

0x0 TX-FIFO Fill Level More Than Threshold Interrupt Clear

This bit is used to clear the HSSPIn_TXF:TFMTS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_TXF:TFMTS inter-rupt flag

Read returns '0'.

[4] TFLETC R0W1

0x0 TX-FIFO Fill Level Less Than or Equal to Threshold Interrupt Clear

This bit is used to clear the HSSPIn_TXF:TFLETS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_TXF:TFLETS inter-rupt flag

Read returns '0'.

[3] TFUC R0W1

0x0 TX-FIFO Underrun Interrupt Clear

This bit is used to clear the HSSPIn_TXF:TFUS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_TXF:TFUS interrupt flag

Read returns '0'.

[2] TFOC R0W1

0x0 TX-FIFO Overrun Interrupt Clear

This bit is used to clear the HSSPIn_TXF:TFOS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_TXF:TFOS interrupt flag

Read returns '0'.

[1] TFEC R0W1

0x0 TX-FIFO Empty Interrupt Clear

This bit is used to clear the HSSPIn_TXF:TFES interrupt flag.

'0': No effect

'1': Clears the HSSPIn_TXF:TFES interrupt flag

Read returns '0'.

[0] TFFC R0W1

0x0 TX-FIFO Full Interrupt Clear

This bit is used to clear the HSSPIn_TXF:TFFS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_TXF:TFFS interrupt flag

Read returns '0'.

Table 3-407: TXC Register




RXF

Description: HS_SPI RX Interrupt Flag Register



Table 3-408: RXF Register



[6] RSSRS R 0x0 Slave Select Released

This interrupt flag indicates that the slave select line is released by the SPI master.

This interrupt flag triggers the RX interrupt signal if it is enabled in HSSPIn_RXE:RSSRE.

[5] RFMTS R 0x0 RX-FIFO Fill Level is More Than Threshold

This interrupt flag is set with every AHB clock if the RX-FIFO fill level is more than the configured RX-FIFO threshold value.

i.e. HSSPIn_DMSTATUS:RXFLEVEL is greater than HSSPIn_FIFOCFG:RXFT.

This interrupt flag triggers the RX interrupt signal if it is enabled in HSSPIn_RXE:RFMTE.

[4] RFLETS R 0x0 RX-FIFO Fill Level is Less Than or Equal to Threshold

This interrupt flag is set with every AHB clock if the RX-FIFO fill level is less than or equal to the configured RX-FIFO threshold value.

i.e. HSSPIn_DMSTATUS:RXFLEVEL is less than or equal to HSSPIn_FIFOCFG:RXFTH.

This interrupt flag triggers the RX interrupt signal if it is enabled in HSSPIn_RXE:RFLETE.

[3] RFUS R 0x0 RX-FIFO Underrun

This interrupt flag indicates that the RX-FIFO is underrun.

The RX-FIFO underrun condition happens when HSSPIn_RXFIFO0~15 register is read (by an AHB master) while the RX-FIFO is empty.

This interrupt flag triggers the RX interrupt signal if it is enabled in HSSPIn_RXE:RFUE.



[2] RFOS R 0x0 RX-FIFO Overrun

This interrupt flag indicates that the RX-FIFO is overrun.

The RX-FIFO overrun condition happens when RX-FIFO is written to by the SPI core while full. This condition may happen dur-ing the slave mode of operation.

This interrupt flag triggers the RX interrupt signal if it is enabled in HSSPIn_RXE:RFOE.

[1] RFES R 0x0 RX-FIFO Empty

This interrupt flag is set with every AHB clock if the RX-FIFO is empty.

This interrupt flag triggers the RX interrupt signal if it is enabled in HSSPIn_RXE:RFEE.

[0] RFFS R 0x0 RX-FIFO Full

This interrupt flag is set with every AHB clock if the RX-FIFO is full.

This interrupt flag triggers the RX interrupt signal if it is enabled in HSSPIn_RXE:RFFE.

Table 3-408: RXF Register




RXE

Description: HS_SPI RX Interrupt Enable Register



Table 3-409: RXE Register



[6] RSSRE RW 0x0 Slave Select Released Interrupt Enable

This bit decides whether or not the HSSPIn_RXF:RSSRS interrupt flag is routed on the RX interrupt signal.

'0': The HSSPIn_RXF:RSSRS interrupt flag does not trigger the RX interrupt signal

'1': The HSSPIn_RXF:RSSRS interrupt flag triggers the RX interrupt signal

[5] RFMTE RW 0x0 RX-FIFO Fill Level is More Than Threshold Interrupt Enable

This bit decides whether or not the HSSPIn_RXF:RFMTS interrupt flag is routed on the RX interrupt signal.

'0': The HSSPIn_RXF:RFMTS interrupt flag does not trigger the RX interrupt signal

'1': The HSSPIn_RXF:RFMTS interrupt flag triggers the RX interrupt signal

[4] RFLETE RW 0x0 RX-FIFO Fill Level is Less Than or Equal To Threshold Interrupt Enable

This bit decides whether or not the HSSPIn_RXF:RFLETS interrupt flag is routed on the RX interrupt signal.

'0': The HSSPIn_RXF:RFLETS interrupt flag does not trigger the RX interrupt signal

'1': The HSSPIn_RXF:RFLETS interrupt flag triggers the RX interrupt signal

[3] RFUE RW 0x0 RX-FIFO Underrun Interrupt Enable

This bit decides whether or not the HSSPIn_RXF:RFUS interrupt flag is routed on the RX interrupt signal.

'0': The HSSPIn_RXF:RFUS interrupt flag does not trigger the RX interrupt signal

'1': The HSSPIn_RXF:RFUS interrupt flag triggers the RX interrupt signal



[2] RFOE RW 0x0 RX-FIFO Overrun Interrupt Enable

This bit decides whether or not the HSSPIn_RXF:RFOS interrupt flag is routed on the RX interrupt signal

'0': The HSSPIn_RXF:RFOS interrupt flag does not trigger the RX interrupt signal

'1': The HSSPIn_RXF:RFOS interrupt flag triggers the RX interrupt signal

[1] RFEE RW 0x0 RX-FIFO Empty Interrupt Enable

This bit decides whether or not the HSSPIn_RXF:RFES interrupt flag is routed on the RX interrupt signal.

'0': The HSSPIn_RXF:RFES interrupt flag does not trigger the RX interrupt signal

'1': The HSSPIn_RXF:RFES interrupt flag triggers the RX interrupt signal

[0] RFFE RW 0x0 RX-FIFO Full Interrupt Enable

This bit decides whether or not the HSSPIn_RXF:RFFS interrupt flag is routed on the RX interrupt signal.

'0': The HSSPIn_RXF:RFFS interrupt flag does not trigger the RX interrupt signal

'1': The HSSPIn_RXF:RFFS interrupt flag triggers the RX interrupt signal

Table 3-409: RXE Register




RXC

Description: HS_SPI RX Interrupt Clear Register



Table 3-410: RXC Register



[6] RSSRC R0W1

0x0 Slave Select Released Interrupt Clear

This bit is used to clear the HSSPIn_RXF:RSSRS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_RXF:RSSRS inter-rupt flag

Read returns '0'.

[5] RFMTC R0W1

0x0 RX-FIFO Fill Level More Than Threshold Interrupt Clear

This bit is used to clear the HSSPIn_RXF:RFMTS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_RXF:RFMTS inter-rupt flag

Read returns '0'.

[4] RFLETC R0W1

0x0 RX-FIFO Fill Level Less Than or Equal to Threshold Interrupt Clear

This bit is used to clear the HSSPIn_RXF:RFLETS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_RXF:RFLETS inter-rupt flag

Read returns '0'.

[3] RFUC R0W1

0x0 RX-FIFO Underrun Interrupt Clear

This bit is used to clear the HSSPIn_RXF:RFUS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_RXF:RFUS inter-rupt flag

Read returns '0'.

[2] RFOC R0W1

0x0 RX-FIFO Overrun Interrupt Clear

This bit is used to clear the HSSPIn_RXF:RFOS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_RXF:RFOS inter-rupt flag

Read returns '0'.



[1] RFEC R0W1

0x0 RX-FIFO Empty Interrupt Clear

This bit is used to clear the HSSPIn_RXF:RFES interrupt flag.

'0': No effect

'1': Clears the HSSPIn_RXF:RFES inter-rupt flag

Read returns '0'.

[0] RFFC R0W1

0x0 RX-FIFO Full Interrupt Clear

This bit is used to clear the HSSPIn_RXF:RFFS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_RXF:RFFS inter-rupt flag

Read returns '0'.

Table 3-410: RXC Register




FAULTF

Description: HS_SPI Fault Interrupt Flag Register



Table 3-411: FAULTF Register



[4] DRCBSFS R 0x0 DMA Read Channel Block Size Fault

This interrupt flag indicates that the block size fault has occurred on a DMA read channel.

The DMA read channel block size fault occurs if the HSSPI RX block counter is '0' and there is a valid read access to the RX FIFO .

This interrupt flag is non-maskable in the HSSPI module.

[3] DWCBSFS R 0x0 DMA Write Channel Block Size Fault

This interrupt flag indicates that the block size fault has occurred on a DMA write channel.

The DMA write channel block size fault occurs if the HSSPI TX block counter is '0' and there is a valid write access to the TX FIFO.

This interrupt flag is non-maskable in the HSSPI module.


[1] WAFS R 0x0 Write Access Fault

This interrupt flag indicates that a write access fault has occurred. This interrupt flag is non-maskable in the HSSPI module.

This bit is set in command sequencer mode if HSSPIn_CSCFG:SRAM = '0' and an AHB master performs a write access to a mem-ory location mapped onto the HSSPI mem-ory area.



[0] UMAFS R 0x0 Unmapped Memory Access Fault

This interrupt flag indicates that an unmapped memory access fault has occurred. This interrupt flag is non mask-able in the HSSPI module.

This bit is set by the HSSPI when any of the following conditions occur:

a) In direct mode (i.e. HSSPIn_MCTRL:CSEN = '0'), an AHB access within the 256 MB address range starting from the HSSPI base address is detected.

b) In command sequencer mode (i.e. HSSPIn_MCTRL:CSEN = '1'), an AHB access to a memory device which is not enabled (in HSSPIn_CSCFG:SSEL0EN~SSEL3EN bits) is detected.

c) In command sequencer mode (i.e. HSSPIn_MCTRL:CSEN = '1'), an AHB access to a memory location which is out-side the memory range being mapped onto the four slave selects (configured through the HSSPIn_CSCFG:MSEL field) is detected.

d) While the module is disabled (i.e. HSSPIn_MCTRL:MEN = '0'), an AHB access to a mapped memory is detected.

Table 3-411: FAULTF Register




FAULTC

Description: HS_SPI Fault Interrupt Clear Register



Table 3-412: FAULTC Register



[4] DRCBSFC R0W1

0x0 DMA Read Channel Block Size Fault Inter-rupt Clear

This bit is used to clear the HSSPIn_FAULTF:DRCBSFS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_FAULTF:DRCBSFS interrupt flag

Read returns '0'.

[3] DWCBSFC R0W1

0x0 DMA Write Channel Block Size Fault Inter-rupt Clear

This bit is used to clear the HSSPIn_FAULTF:DWCBSFS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_FAULTF:DWCBSFS interrupt flag

Read returns '0'.

[2] Reserved R0W1

0x0 -

[1] WAFC R0W1

0x0 Write Access Fault Interrupt Clear

This bit is used to clear the HSSPIn_FAULTF:WAFS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_FAULTF:WAFS interrupt flag

Read returns '0'.

[0] UMAFC R0W1

0x0 Unmapped Memory Access Fault Interrupt Clear

This bit is used to clear the HSSPIn_FAULTF:UMAFS interrupt flag.

'0': No effect

'1': Clears the HSSPIn_FAULTF:UMAFS interrupt flag

Read returns '0'.



DMCFG

Description: HS_SPI Direct Mode Configuration Register



Table 3-413: DMCFG Register



[2] MSTARTEN RW 0x0 iMSTART Enable

This bit is used only in direct mode (i.e. HSSPIn_MCTRL:CSEN = '0').

'0': The HSSPI can initiate a transfer only when the software writes a '1' to the HSSPIn_DMSTART:START bit

'1': The HSSPI can initiate a transfer either when the software writes a '1' to the HSSPIn_DMSTART:START bit or when a positive edge is detected on the iMSTART input signal of the HSSPI

[1] SSDC RW 0x0 Slave Select Deassertion Control

This bit decides how the slave select is deasserted.

'0': Software flow control. HSSPIn_DMSTOP:STOP is used to decide when to deassert the slave select

'1': Byte counter mode. HSSPIn_DMBCC:BCC is used to decide when to deassert the slave select

[0] MST RW 0x1 Set to '1'.



DMDMAEN

Description: HS_SPI Direct Mode DMA Enable Register



Table 3-414: DMDMAEN Register



[1] TXDMAEN RW 0x0 TX DMA Enable

'0': TX DMA channel is disabled

'1': TX DMA channel is enabled

[0] RXDMAEN RW 0x0 RX DMA Enable

'0': RX DMA channel is disabled

'1': RX DMA channel is enabled



SVCFG0

Description: Supervision Config Register 0



Table 3-415: SVCFG0 Register


[7:4] SPI1SVOFF RW 0x0 Byte offset for supervision of the transmit-ted data of SPI1




SVCFG1

Description: Supervision Config Register 1



Table 3-416: SVCFG1 Register






DMSTART

Description: HS_SPI Direct Mode Start Register



Table 3-417: DMSTART Register



[0] START RpWp1

0x0 Start Transfer

'0': No effect

'1': Sets this bit

The HSSPI resets this bit to '0' when it starts the serial transfer. Writing a '1' to this bit when the bit is already set to '1' has no effect on the current serial transfer.

The HSSPI sets this bit to '1' if in direct mode (i.e. HSSPIn_MCTRL:CSEN = '0') and a positive edge is detected on iMSTART input signal (while HSSPIn_DMCFG:MSTARTEN is set).



DMSTOP

Description: HS_SPI Direct Mode Stop Register



Table 3-418: DMSTOP Register



[0] STOP RW 0x0 Stop bit

This bit is used only when HSSPIn_DMCFG:SSDC = '0'.

This bit is used in software flow control mode for deassertion of the slave select output.

'0': The HSSPI does not deassert the slave select output

'1': Deassertion of the slave select output by the HSSPI depends on the mode used:

In TX only mode - Stop is set and all con-tent in TX-FIFO is transferred.

In RX only mode - Stop is set and current filling of shift register is complete.

In TX and RX mode - Stop is set and all content in TX-FIFO is transferred.



DMPSEL

Description: HS_SPI Direct Mode Peripheral Select Register


Instance no 0: 0x0002603AInstance no 1: 0x000B103A

Table 3-419: DMPSEL Register



[5] SPI3_NOCS RW 0x0 Select the input for the SPI3 when in (use only for master, legacy mode) '0': use com-mon SPI_SDIO1 '1': use dedicated SPI3_SDI




[1:0] PSEL RW 0x0 Peripheral Select

The PSEL bits decide which of the 4 slave select output lines in SSEL3~0 is active for the current serial transfer.

'00': Slave select 0






DMTRP

Description: HS_SPI Direct Mode Transfer Protocol Register


Instance no 0: 0x0002603BInstance no 1: 0x000B103B

Table 3-420: DMTRP Register



[3:0] TRP RW 0x0 Transfer Protocol

Bits TRP[3:2] indicate duplex configuration - RX-only, TX-only or both: TX and RX.

Bits TRP[1:0] indicate whether the protocol used is legacy, dual or quad.

'0000': TX and RX in legacy mode

'0100': RX only in legacy mode

'0101': RX only in dual mode

'0110': RX only in quad mode

'1000': TX only in legacy mode

'1001': TX only in dual mode

'1010': TX only in quad mode

All other combinations are reserved.



DMBCC

Description: HS_SPI Direct Mode Byte Count Control Register



Table 3-421: DMBCC Register


[15:0] BCC RW 0x0 Byte Count Control

This field is used by the HSSPI only in direct mode and when HSSPIn_DMCFG:SSDC = '1'.

The BCC field must be programmed by the software with the number of bytes to be transmitted or received or both.

The value in this field is loaded in a down counter at the start of a transfer and the counter is decremented when a byte is seri-ally transferred. The HSSPI completes the transaction and deasserts the slave select when this down counter reaches '0'.



DMBCS

Description: HS_SPI Direct Mode Byte Count Status Register


Instance no 0: 0x0002603EInstance no 1: 0x000B103E

Table 3-422: DMBCS Register


[15:0] BCS R 0x0 Byte Count Status

This read-only field is valid only when the HSSPI acts in direct mode and when HSSPIn_DMCFG:SSDC = '1'.

The BCS field indicates the number of bytes in the current serial transfer that have not yet been serially transmitted, received or both.



DMSTATUS

Description: HS_SPI Direct Mode Status Register



Table 3-423: DMSTATUS Register



[20:16] TXFLEVEL R 0x0 Current Fill Level of TX-FIFO

This field indicates the current fill level of the TX-FIFO.


[12:8] RXFLEVEL R 0x0 Current Fill Level of RX-FIFO

This field indicates the current fill level of the RX-FIFO.


[1] TXACTIVE R 0x0 TX Active

It indicates whether transmission is in prog-ress.

'0': Serial transmission is not active

'1': Serial transmission is active

[0] RXACTIVE R 0x0 RX Active

It indicates whether reception is in prog-ress.

'0': Serial reception is not active

'1': Serial reception is active



TXBITCNT

Description: HS_SPI Transmit Bit Count Register



Table 3-424: TXBITCNT Register



[5:0] TXBITCNT R 0x0 TX Bit Count

It indicates the number of bits pending transmission from the TX shift register.

0: No bits will be transmitted

1: One (1) bit will be transmitted

...

31: 31 bits will be transmitted

32: 32 bits will be transmitted

The HSSPIn_TXBITCNT register is updated by the HSSPI when a transfer stops (while the HSSPI is in master mode) or when a transfer ends (i.e. slave select deassertion interrupt flag is asserted).



RXBITCNT

Description: HS_SPI Receive Bit Count Register



Table 3-425: RXBITCNT Register



[5:0] RXBITCNT R 0x0 RX Bit Count

It indicates the number of valid bits in the RX shift register.

0: No bits are valid

1: One (1) bit is valid

...

31: 31 bits are valid

32: 32 bits are valid

'This register is used in slave mode only'.

When a transfer ends in slave mode (i.e. slave select deassertion interrupt flag is asserted), the HSSPIn_RXSHIFT register is updated with the assembled data and the HSSPIn_RXBITCNT register is updated with the number of valid bits in the HSSPIn_RXSHIFT register. The software can read the HSSPIn_RXSHIFT and HSSPIn_RXBITCNT registers to get the RX data which has not yet been pushed into the RX-FIFO.



RXSHIFT

Description: HS_SPI RX Shift Register



Table 3-426: RXSHIFT Register


[31:0] RXSHIFT R 0x0 RX Shift Register

'This register is used in slave mode only'.

When a transfer ends in slave mode (i.e. slave select line is deasserted), the HSSPIn_RXSHIFT register is updated with the assembled data and the HSSPIn_RXBITCNT register is updated with the number of valid bits in the HSSPIn_RXSHIFT register. The software can read the HSSPIn_RXSHIFT and HSSPIn_RXBITCNT registers to get the RX data which has not yet been pushed into the RX-FIFO.



FIFOCFG

Description: HS_SPI FIFO Configuration Register



Table 3-427: FIFOCFG Register



[12] TXFLSH R0W1

0x0 TX-FIFO Flush

This register can be used by the software to flush the TX-FIFO.

'0': No effect

'1': Flushes the TX-FIFO

Read returns a '0'.

[11] RXFLSH R0W1

0x0 RX-FIFO Flush

This register can be used by the software to flush the RX-FIFO.

'0': No effect

'1': Flushes the RX-FIFO

Read returns a '0'.

[10] TXCTRL RW 0x0 TXCTRL bit to be Written to TX-FIFO

When a write to the HSSPIn_TXFIFO0~15 register occurs, bit 33 in the TX-FIFO word is written with the value in the HSSPIn_FIFOCFG:TXCTRL field.

The HSSPIn_FIFOCFG:TXCTRL should be set by the software only when the HSSPIn_DMTRP:TRP field is pro-grammed in any one of the following modes:

a) TX only in dual mode

b) TX only in quad mode

If the HSSPIn_DMTRP:TRP field is pro-grammed in any mode other than the two modes mentioned above, then the TXCTRL bit shall be programmed to '0' by the soft-ware.

Before writing to the HSSPIn_TXFIFO0~15 register, the software must update this bit, depending on whether it wants the TXC-TRL bit in the next location in TX-FIFO to be set or reset.



[9:8] FWIDTH RW 0x0 FIFO Width

This register field indicates the FIFO width. Depending on the configured width of the FIFO, the usable size of the shift register in the SPI core also changes.

'00': TX-FIFO, RX-FIFO and shift register are 8-bit wide




[7:4] TXFTH RW 0x7 TX-FIFO Threshold Level

Software must program this field with the threshold level of the TX-FIFO.

[3:0] RXFTH RW 0x7 RX-FIFO Threshold Level

Software must program this field with the threshold level of the RX-FIFO.

Table 3-427: FIFOCFG Register




TXFIFO0

Description: HS_SPI TX-FIFO Registers 0



Table 3-428: TXFIFO0 Register


[31:0] TXDATA R0W 0x0 TX-FIFO Register.

Writing to this register puts the data into the next location of TX-FIFO and increments the TX-FIFO write pointer.

Bit 33 of the TX-FIFO word is written with the value in the HSSPIn_FIFOCFG:TXC-TRL field.

Irrespective of the configured width of TX-FIFO, only 32-bit access to this register is allowed. When the configured TX-FIFO width is less than 32 bits, the unused most significant bits from the FIFO locations are not transmitted by the HSSPI, e.g. if config-ured FIFO width is 8 bits, then only the bits TXDATA[7:0] are transmitted by HSSPI and the bits TXDATA[31:08] are unused. The software must not write any valid data to be transmitted in those unused most sig-nificant bits.

A write access to this register while the TX-FIFO is full pushes the new data into the TX-FIFO and triggers a TX-FIFO overrun event. When a TX-FIFO overrun condition occurs, the integrity of the data transmitted over the serial lines is not guaranteed. Therefore, to avoid an overrun the software must ensure that TX-FIFO is not full before writing to it.



TXFIFO1













TXFIFO2













TXFIFO3













TXFIFO4













TXFIFO5













TXFIFO6













TXFIFO7













TXFIFO8













TXFIFO9













TXFIFO10













TXFIFO11













TXFIFO12













TXFIFO13













TXFIFO14













TXFIFO15













RXFIFO0

Description: HS_SPI RX-FIFO Registers 0



Table 3-444: RXFIFO0 Register


[31:0] RXDATA R 0x0 RX-FIFO Register.

Reading this register returns a word of data from the RX-FIFO location pointed to by the RX-FIFO read pointer. After a read access to this register, the RX-FIFO read pointer is incremented provided that the read cycle was initiated by the AHB master.

A read access by a AHB master to this reg-ister also updates the RX-FIFO read pointer.

Irrespective of the configured width of RX-FIFO, only 32-bit read access to this regis-ter is allowed. When the configured FIFO width is less than 32 bits, the unused most significant bits from the FIFO locations con-tain invalid data, e.g. if the configured FIFO width is 8 bits, then only bits RXDATA[7:0] are valid and bits RXDATA[31:8] return logic '0'. The software must not use any data from the unused most significant bits.

A read access to this register while the RX-FIFO is empty pops invalid data out of the RX-FIFO. A RX-FIFO underrun interrupt (HSSPIn_RXF:RFUS) event is triggered if the read cycle was initiated by the AHB master.



RXFIFO1













RXFIFO2













RXFIFO3













RXFIFO4



Instance no 0: 0x000260A0Instance no 1: 0x000B10A0










RXFIFO5













RXFIFO6













RXFIFO7



Instance no 0: 0x000260ACInstance no 1: 0x000B10AC










RXFIFO8



Instance no 0: 0x000260B0Instance no 1: 0x000B10B0










RXFIFO9













RXFIFO10













RXFIFO11



Instance no 0: 0x000260BCInstance no 1: 0x000B10BC










RXFIFO12



Instance no 0: 0x000260C0Instance no 1: 0x000B10C0










RXFIFO13













RXFIFO14













RXFIFO15



Instance no 0: 0x000260CCInstance no 1: 0x000B10CC










CSCFG

Description: HS_SPI Command Sequencer Configuration Register


Instance no 0: 0x000260D0Instance no 1: 0x000B10D0

Table 3-460: CSCFG Register



[19:16] MSEL RW 0x0 Memory Device Selection bits

This field indicates the range of the AHB address space associated with each slave select line. It also indicates the size of each memory banks in the selected device.

This field is used by the command sequencer for two things:

(a) To select which of the 4 slave select output lines should be asserted for the memory mapped serial transfer

(b) To select the size of each memory bank in the selected memory device.

For more details refer to Section 31.5 'Command sequencer mode'.


[11] SSEL3EN RW 0x0 Slave Select 3 Enable

'0': Any access which falls into the memory range mapped onto slave select 3 causes an unmapped memory access fault

'1': Access to the serial memory device mapped onto slave select 3 is enabled









'1': Access to the serial memory device mapped onto slave select 0 are enabled




[2:1] MBM RW 0x0 Multi Bit Mode

'00': Memory device access through the command sequencer uses the legacy SPI protocol. Read data is sampled on SDATA[0]. Memory instruction, address and other control information are transmit-ted on SDATA[1]. The output enables of the other serial data lines are deasserted

'01': Memory device access through the command sequencer uses the half-duplex dual-bit SPI protocol. Read data is sampled on SDATA[1:0]. Memory instruction, address and other control information are transmitted on SDATA[1:0]

'10': Memory device access through the command sequencer uses the quad-bit SPI protocol. Read data is sampled on SDATA[3:0]. Memory instruction, address and other control information are transmit-ted on SDATA[3:0]

'11': Reserved

[0] SRAM RW 0x0 Serial SRAM or Serial Flash Memory Type Select

This bit should be set only if serial SRAM devices are memory mapped through the HSSPI.

'0': Serial Flash memory devices are con-nected. Writes are disabled

'1': Serial SRAM memory devices are con-nected. Writes are enabled

Table 3-460: CSCFG Register




CSITIME

Description: HS_SPI Command Sequencer Idle Time Register



Table 3-461: CSITIME Register



[15:0] ITIME RW 0xFFFF Idle Time

This register is used by the HSSPI in com-mand sequencer mode (i.e. HSSPIn_MCTRL:CSEN = '1') only.

Once the HSSPI completes the required number of memory read or write accesses on the serial interface, it keeps the slave select line asserted. If no further access to the mapped serial memory device is detected within the idle timeout period, then the HSSPI deasserts the slave select line. This gives better performance when the serial memory access is of the same type (i.e. if all are read or write accesses), the accessed locations are continuous and the access occurs within the predefined idle timeout interval. The idle timeout interval is in terms of the AHB clock period.



CSAEXT

Description: HS_SPI Command Sequencer Address Extension Register



Table 3-462: CSAEXT Register


[31:13] AEXT RW 0x0 Address Extension bits

This register is used by the HSSPI in com-mand sequencer mode (i.e. HSSPIn_MCTRL:CSEN = '1') only.

The HSSPIn_CSAEXT register contains the 19 most significant bits [31:13] of the memory address which are generated by the command sequencer. The memory address generated by the HSSPI on each slave select (while in command sequencer mode) is a concatenation of the appropriate number of bits from the HSSPIn_CSAEXT register and from the AHB address bus. For more details refer to Section 'Command sequencer mode'.

If address extension is not to be used, the software should reset this field to 0x0000000.




RDCSDC0

Description: HS_SPI Read Command Sequence Data/Control Register 0


Instance no 0: 0x000260DCInstance no 1: 0x000B10DC

Table 3-463: RDCSDC0 Register


[15:8] RDCSDATA RW 0x0 Command Sequencer Data or Control byte for Memory-Read Transactions

'0': When the HSSPIn_RDCSDC0:DEC bit is '0', the RDCSDATA field contains the 8-bit data to be transmitted on the serial interface

'1': When the HSSPIn_RDCSDC0:DEC bit is '1', the RDCSDATA[2:0] field is decoded as follows

'000': RDCSDATA[2:0] = '000': Transmit address bits [07:0] of the serial memory address




'100': RDCSDATA[2:0] = '100': High-Z byte (i.e. SDATA[3:0] signals are tri-stated for 1 byte time

'101': RDCSDATA[2:0] = '101': High-Z nibble (i.e. transmission of RDCSDATA[7:4] is followed by tri-stating of SDATA output for 1 nibble time

'111': RDCSDATA[2:0] = '111': End of list

All other values of RDCSDATA[2:0] are reserved and must not be used.

Limitations.

The last command in a command sequence (i.e. the entry immediately before the "End of list" or the entry in the last register if the command sequence has a length of 8) must be either "Hi-Z byte" or "Hi-Z nibble".

"End of list", "Hi-Z byte" and "Hi-Z nibble" must not be the first entry on the list

The only commands that can follow "Hi-Z byte" to the "End of list" are "Hi-Z byte" and "End of list"

The only commands that can follow "Hi-Z nibble" to the "End of list" are "Hi-Z byte" and "End of list"




[0] DEC RW 0x0 Decode

'0': Transmit HSSPIn_RDCSDC0:RDCSDATA as it is

'1': Decode HSSPIn_RDCSDC0:RDCS-DATA[2:0] to decide what further action is required





RDCSDC1



Instance no 0: 0x000260DEInstance no 1: 0x000B10DE














Limitations.








RDCSDC2



Instance no 0: 0x000260E0Instance no 1: 0x000B10E0














Limitations.








RDCSDC3

















Limitations.








RDCSDC4

















Limitations.








RDCSDC5

















Limitations.








RDCSDC6

















Limitations.








RDCSDC7



Instance no 0: 0x000260EAInstance no 1: 0x000B10EA














Limitations.








WRCSDC0

Description: HS_SPI Write Command Sequence Data/Control Register 0


Instance no 0: 0x000260ECInstance no 1: 0x000B10EC

Table 3-471: WRCSDC0 Register


[15:8] WRCSDATA RW 0x0 Command Sequencer Data or Control byte for Memory-Write Transactions

'0': When the HSSPIn_WRCSDC0:DEC bit is '0', the WRCSDATA field contains the 8-bit data to be transmitted on the serial inter-face

'1': When the HSSPIn_WRCSDC0:DEC bit is '1', the WRCSDATA[2:0] field is decoded as follows

'000': WRCSDATA[2:0] = '000': Transmit address bits [07:00] of the serial memory address




'100': WRCSDATA[2:0] = '100': High-Z byte (i.e. SDATA[3:0] signals are tri-stated for 1 byte time

'101': WRCSDATA[2:0] = '101': High-Z nib-ble (i.e. transmission of WRCSDATA[7:4] is followed by tri-stating of SDATA output for 1 nibble time

'111': WRCSDATA[2:0] = '111': End of list

All other values of WRCSDATA[2:0] are reserved and must not be used.

Limitations.







[0 ] DEC RW 0x0 Decode

'0': Transmit HSSPIn_WRCSDC0:WRCS-DATA as it is

'1': Decode the HSSPIn_WRCSDC0:WRC-SDATA[2:0] to decide what further action ir required





WRCSDC1



Instance no 0: 0x000260EEInstance no 1: 0x000B10EE














Limitations.








'0': Transmit the HSSPIn_WRCSDC1:WRCSDATA as it is

'1': Decode the HSSPIn_WRCSDC1:WRC-SDATA[2:0] to decide what further action is required





WRCSDC2



Instance no 0: 0x000260F0Instance no 1: 0x000B10F0














Limitations.







WRCSDC3













'100': WRCSDATA[2:0] = '100': High-Z byte (i.e. SDATA[3:0] signals are tri-stated for 1 byte times

'101': WRCSDATA[2:0] = '101': High-Z nib-ble (i.e. transmission of WRCSDATA[7:4] is followed by tri-stating of SDATA output for 1 nibble times



Limitations.







WRCSDC4

















Limitations.







WRCSDC5

















Limitations.







WRCSDC6









'000': WRCSDATA[2:0] = '000': Transmit address bits [07:00] of the serial memory addres








Limitations.







WRCSDC7



Instance no 0: 0x000260FAInstance no 1: 0x000B10FA














Limitations.







MID

Description: HS_SPI Module ID Register


Instance no 0: 0x000260FCInstance no 1: 0x000B10FC

Table 3-479: MID Register


[31:0] MID R 0x1 Module ID

This read-only register gives the unique module identification (ID) number of the HSSPI module, which in turn identifies the version of the HSSPI module used in the MCU.

The module ID number of an HSSPI is found in the device specific datasheet.




3.4 Programmable CRC Registers

In this section, the ‘Register Overview’ table summarizes all Programmable CRC registers, includingbase address of the module and name, description, and the absolute address of each register, whichare then described separately in the following tables.


3.4.1 Programmable CRC Register Overview




BASEADDR + 0x0000 PRGCRCn_CRCPOLY CRC Polynomial Register

BASEADDR + 0x0004 PRGCRCn_CRCSEED CRC Seed Register

BASEADDR + 0x0008 PRGCRCn_CRCFXOR CRC Final XOR Register

BASEADDR + 0x000C PRGCRCn_CRCCFG CRC Configuration Register

BASEADDR + 0x0010 PRGCRCn_CRCWR CRC Write Register

BASEADDR + 0x0014 PRGCRCn_CRCRD CRC Read Register



This page intentionally left blank



PRGCRCn_CRCPOLY

Description: CRC Polynomial Register



Table 3-481: PRGCRCn_CRCPOLY Register


[31:0] POLY RW 0x4C11DB7

CRC Polynomial

The CRCPOLYn contains the CRC polyno-mial. The degree of the polynomial must be between 2 to 32. Initial value is the com-mon CRC-32 polynomial 0x04C11DB7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). The highest degree of coefficient should be used to configure polynomial/checksum length (CRCCFGn:LEN).



PRGCRCn_CRCSEED

Description: CRC Seed Register



Table 3-482: PRGCRCn_CRCSEED Register


[31:0] SEED RW 0xFFFFFFFF

CRC SEED

CRCSEEDn contains the initial value for checksum calculation. If the seed value is not initialized for the next operation (even if the seed value is identical to the previous operation), then calculation is continued from the last state with the current check-sum value as initial value. Initial value for seed register is 0xFFFFFFFF.



PRGCRCn_CRCFXOR

Description: CRC Final XOR Register



Table 3-483: PRGCRCn_CRCFXOR Register


[31:0] FXOR RW 0xFFFFFFFF

CRC XOR data

The contents of CRCFXORn register are XOR'ed with the preliminary checksum data (after CRCCFGn:ROBIT/ROBYT set-tings have been applied) and then the final checksum is moved to CRCRDn register. Initial value for final XOR register is 0xFFFFFFFF.



PRGCRCn_CRCCFG

Description: CRC Configuration Register



Table 3-484: PRGCRCn_CRCCFG Register



[28] LOCK R 0x0 CRC engine status bit

This bit indicates the status of the CRC engine.

'1' = CRC engine is busy and writing to CRC registers is not possible.

'0' = CRC engine is ready, new data can be written to CRC registers.


[26] CDEN RW 0x0 DMA request enable Bit

This bit enables/disables the DMA request.

'1'= Enable the DMA request.

'0'= Disable the DMA request.

DMA request is generated when CRC is in buffer empty state and CRCCFGn:CDEN is set. DMA ISR should clear this bit after final transfer. Clearing this bit by CPU at any other time might lead to unwanted behav-ior.

[25] CIEN RW 0x0 CRC Interrupt enable bit to CPU

This bit enables/disables the interrupt requests.

'1'= Enable the interrupt requests.

'0'= Disable the interrupt requests.

The IRQ is triggered when CRC-CFGn:CIEN bit is enabled and CRC inter-rupt flag (CRCCFGn:CIRQ) is set.

[24] CIRQ R 0x0 CRC Interrupt flag

This bit indicates the interrupt status of CRC.

'1' = Interrupt request.

Checksum has been calculated by CRC engine and is available in CRCRDn regis-ter.

'0' = No interrupt request.

Note: CPU clears interrupt flag by writing CRCCFGn:CIRQCLR bit to '1'.



[23:22] SZ RW 0x3 CRC input data size configuration bits

These bits are used to configure the input data size as follows:

00 = 8-Bit

01 = 16-Bit

10 = 24-Bit

11 = 32-Bit

[21:16] LEN RW 0x20 CRC Polynomial/Checksum length config-uration bits

These bits are used to configure the length (degree) of CRC Polynomial/Checksum as follows:

100000 = 32

011111 = 31

.................

.................

000010 = 2

Note: The following settings are not sup-ported:

CRCCFGn:LEN greater than 32

CRCCFGn:LEN less than 2


[11] RIBIT RW 0x0 Reflect Input Bits

'1' = Enable input bit reflection.

'0' = Disable input bit reflection.

When the input data in the CRCWRn reg-ister is passed to the CRC engine, the bit ordering of each byte within input data is reversed. Refer Section 1.3 "Operation of Programmable CRC".

[10] RIBYT RW 0x0 Reflect Input Bytes

'1' = Enable input byte reflection (swap-ping).

'0' = Disable input byte reflection (swap-ping).

When the input data in the CRCWRn reg-ister is passed to the CRC engine, the byte ordering of input data is reversed. Only the bytes of the configured input data size CRCCFGn:SZ are affected. Refer Section 1.3 "Operation of Programmable CRC".

Note: For 8-bit input data, this setting has no effect.





[9] ROBIT RW 0x0 Reflect Output Bits

'1' = Enable output bit reflection.

'0' = Disable output bit reflection.

The bit ordering of each byte within check-sum is reversed, before passing the check-sum to final XOR'ing stage. Refer Section 1.3 "Operation of Programmable CRC".

[8] ROBYT RW 0x0 Reflect Output Bytes

'1' = Enable output byte reflection (swap-ping).

'0' = Disable output byte reflection (swap-ping).

The byte ordering of checksum data is reversed, before passing the byte aligned polynomial length of checksum data to final XOR'ing stage. Refer Section 1.3 "Opera-tion of Programmable CRC".

Note: For the checksum data less than or equal to 8-bits, this settings has no effect.


[0] CIRQCLR R0W1

0x0 Interrupt Clear

This bit clears the CRC interrupt flag.

'1' = Clear CRC interrupt flag (CRC-CFGn:CIRQ).

'0' = Write '0' is ignored, reading this bit always returns '0'.





PRGCRCn_CRCWR

Description: CRC Write Register



Table 3-485: PRGCRCn_CRCWR Register


[31:0] CRCWR RW 0x0 CRC Write data

The CRCWRn register contains the input data, for which the CRC checksum is to be calculated. Writing to this register starts the CRC calculation process. After pre-pro-cessing (bit/byte reflection/swapping) the contents of the CRCWRn register are passed to the CRC engine (the contents of CRCSEEDn register are also pro-vided).There it is divided by the content of CRCPOLYn register in modulo-2 arithme-tic to get the final checksum after post-pro-cessing (bit/byte reflection/swapping and XOR'ing).



PRGCRCn_CRCRD

Description: CRC Read Register



Table 3-486: PRGCRCn_CRCRD Register


[31:0] CRCRD RW 0x0 CRC Read data

The CRC Read Register contains the result (final checksum) of the CRC calcula-tion after post-processing (applying CRC-CFGn:ROBIT, CRCCFGn:ROBYT and CRCFXORn settings). Writing any value on CRCRDn register changes its content and it does not affect CRC calculation.




3.5 DMAC Registers

In this section, the ‘Register Overview’ table summarizes all DMAC registers, including base address ofthe module and name, description, and the absolute address of each register, which are then describedseparately in the following tables.


3.5.1 DMAC Register Overview




BASEADDR + 0x0000 DMAi_A0 DMAC Channel Configuration A Register Channel 0

BASEADDR + 0x0004 DMAi_B0 DMAC Channel Configuration B Register Channel 0

BASEADDR + 0x0008 DMAi_SA0DMAC Channel Configuration Source Address Register Channel 0

BASEADDR + 0x000C DMAi_DA0DMAC Channel Configuration Destination Address Register Channel 0

BASEADDR + 0x0010 DMAi_C0 DMAC Channel Configuration C Register Channel 0

BASEADDR + 0x0014 DMAi_D0 DMAC Channel Configuration D Register Channel 0

BASEADDR + 0x0018 DMAi_SASHDW0DMAC Channel Configuration Source Address Shadow Register Channel 0

BASEADDR + 0x001C DMAi_DASHDW0DMAC Channel Configuration Destination Address Shadow Register Channel 0

BASEADDR + 0x0040 DMAi_A1 DMAC Channel Configuration A Register Channel 1

BASEADDR + 0x0044 DMAi_B1 DMAC Channel Configuration B Register Channel 1

BASEADDR + 0x0048 DMAi_SA1DMAC Channel Configuration Source Address Register Channel 1

BASEADDR + 0x004C DMAi_DA1DMAC Channel Configuration Destination Address Register Channel 1

BASEADDR + 0x0050 DMAi_C1 DMAC Channel Configuration C Register Channel 1

BASEADDR + 0x0054 DMAi_D1 DMAC Channel Configuration D Register Channel 1

BASEADDR + 0x0058 DMAi_SASHDW1DMAC Channel Configuration Source Address Shadow Register Channel 1

BASEADDR + 0x005C DMAi_DASHDW1DMAC Channel Configuration Destination Address Shadow Register Channel 1

BASEADDR + 0x1000 DMAi_R DMAC Global Configuration Register

BASEADDR + 0x1004 DMAi_DIRQ1 DMAC Global Completion Interrupt 1 Register

BASEADDR + 0x1008 DMAi_DIRQ2 DMAC Global Completion Interrupt 2 Register

BASEADDR + 0x100C DMAi_EDIRQ1 DMAC Global Error Interrupt 1 Register

BASEADDR + 0x1010 DMAi_EDIRQ2 DMAC Global Error Interrupt 2 Register

BASEADDR + 0x1014 DMAi_ID DMAC ID Register


BASEADDR + 0x2020 DMAi_CMICIC0DMAC Client Matrix Internal Client Interface Configuration Register 0 (for Client 8)



BASEADDR + 0x202C DMAi_CMICIC3DMAC Client Matrix Internal Client Interface Configuration Register 3 (for Client 11)





















BASEADDR + 0x2800 DMAi_CMCHIC0DMAC Client Matrix Channel Interface Configuration Regis-ter 0

BASEADDR + 0x2804 DMAi_CMCHIC1DMAC Client Matrix Channel Interface Configuration Regis-ter 1






DMAi_A0

Description: DMAC Channel Configuration A Register Channel 0



Table 3-488: DMAi_A0 Register


[31] EB RW 0x0 Enable Bit

This bit is used to enable/disable a DMA channel. If this bit is set to 1, the channel is enabled and waits for a request to start a DMA transfer. (Before that, DMAi_R:DE bit needs to be set to 1 already.) If this bit is set to 0, the channel is disabled and does not perform a DMA transfer. When this bit is set to 0 during a running DMA transfer, the DMA transfer terminates at the next transfer gap. This is regarded as a forced stop and an error interrupt is generated. About the transfer gap, please refer to the description of DMAi_R:DE bit. This bit is useful to re-configure each configuration register of the channel after a DMA trans-fer.

0: Channel is disabled. (Initial value)

1: Channel is enabled.

[30] PB RW 0x0 Pause Bit

This bit is used to halt the transfer of the DMA channel. If this bit is set to 1, this channel halts the transfer and does not per-form a DMA transfer until this bit is cleared.

When this bit is set to 1 while no transfer is ongoing DMAC enters the halt state imme-diately. When it was set to 1 during a run-ning transfer, the halt state is entered at the next transfer gap. If the DMA transfer com-pletes at the next transfer gap a completion interrupt is issued.

When this bit is set to 0 the halt condition is cleared and DMAC waits for the next request to continue the DMA transfer.

This bit is useful to halt a DMA transfer without re-configuration of each configura-tion register of the channel.

0: Channel is not halted. (Initial value)

1: Channel is halted.



[29] ST R0W1

0x0 Software Trigger

This bit is used to generate a software request. This bit can only be set when DMAi_Bn:SR = 1 and the stop status is either initial or normal. When this bit is set to 1, DMA transfer is requested because software request has been received. The DMAC sets this bit to 0 if the Software Trig-ger has been recognized and an internal channel request for service was set and Software Trigger Ready (DMAi_Bn:SR) is set to 0. The software request was suc-cessful when DMAi_Bn:SR changes its sta-tus from 1 to 0. ST can only be read as 0.

0: No software request. (Initial value)

1: Software request.

[28:27] IS RW 0x0 Input Select

These bits are used to select the trigger source of a DMA transfer request. When the trigger source of a DMA transfer shall be a software request, IS bits must be set to 00. When the trigger source of a DMA transfer shall be a hardware request, IS bits must be set to 01.

00: Software request. (Initial value)

01: Hardware request.

10: Reserved.

11: Reserved.

Note: When the transfer mode is block transfer or burst transfer, edge detection is used. When the transfer mode is demand transfer, level detection is used.

[26] AL RW 0x0 Alternate

This bit decides whether the data transfers should alternate between Read and Write or should be contiguous Reads followed by contiguous Writes. The alternation will take place after each incremental read burst and after each single data read.

0: Contiguous. (Initial value)

1: Alternate.





[25:24] BL RW 0x0 Beat Limit

Beat Limit controls the maximum burst length the AHB Master can make on the AHB bus for this DMA channel.

00: Single Transfer (SINGLE). (Initial Value)

01: 4-beat incrementing burst (INCR4).



These bits are used in combination with Block Count to decide which type of burst has to be transmitted over the AHB inter-face.

[23:20] BC RW 0x0 Block Count

These bits specify the total length of a sin-gle block in block/burst transfer mode. The maximum block count is 16. For e.g. if BC = 4 the number of data transfers is 5 (BC+1).

Alternate, Block Count, and Beat Limit together decide the bursts generated by the AHB Master.

In demand transfer mode, Block Count has a different meaning, here it is used to deter-mine the max. number of data transfers that can be made in one arbitration phase.

[19:16] TO RW 0xF Timeout

Timeout is applicable only in Demand transfer mode. When signal DMA Request (DREQ) is de-asserted the Timeout count starts down counting on every DMAC clock cycle. If Timeout reaches zero, the DMAC finishes the current arbitration phase after completing the current data transfer, which allows the channel arbiter to arbitrate the next requesting channel.





[15:0] TC RW 0x0 Transfer Count

These bits are used to specify the transfer count for the block/burst/demand transfer. The maximum transfer count is 65536. If TC is set to 0 then 1 transfer will be done and if TC is set to 65535 then 65536 trans-fers will be done.

In burst and block transfer mode the TC represents the number of blocks of data transfers that the channel has to make before DMA 'End of Processing' is gener-ated. For e.g. if TC = 9 and BC = 9 then total number of transfers the DMAC does = (BC+1)*(TC+1) = 10*10 = 100 transfers.

In demand transfer mode, TC represents the maximum number of data transfers that the channel has to make. For example if TC = 99, then the channel can make 100 DMA transfers.





DMAi_B0

Description: DMAC Channel Configuration B Register Channel 0



Table 3-489: DMAi_B0 Register


[31] DQ R 0x0 Flag of DIRQ

DQ is set to 1 when a DMA transfer com-pleted successfully. DQ is cleared by hard-ware if DMAi_Cn:CD (clear DIRQ) bit is set to 1. Otherwise the value is retained.

[30] EQ R 0x0 Flag of EDIRQ

EQ is set to 1 when a DMA transfer is fin-ished with an error. EQ is cleared by hard-ware if DMAi_Cn:CE (clear EDIRQ) bit is set to 1. Otherwise the value is retained.

[29:28] MS RW 0x0 Mode Select

MS sets the transfer mode of the channel.

00: Block transfer mode (Initial value)

01: Burst transfer mode

10: Demand transfer mode

11: Reserved

[27:26] TW RW 0x0 Transfer Width

TW specifies the data width for every data transfer of the DMA transfer.

00: Byte (Initial value)

01: Half-Word

10: Word

11: Double Word



[25] SR R 0x1 Software Trigger Ready

This bit is used to signal that the DMA channel is ready to receive a software request. The following conditions can cause that the DMA channel is not ready to receive a software request. If one or more of the conditions below is true SR is set to 0 by hardware. If none of the conditions is true SR is set to 1 by hardware.

- DMAi_R:DE == 0; DMAC is disabled.

- DMAi_R:DH == 1; All DMA channels are halted.

- DMAi_An:EB == 0; DMA channel is dis-abled.

- DMAi_An:PB == 1; DMA channel is halted.

- DMAi_An:IS != 00; Input select is not set to Software.

- DMA transfer is active and a software request is pending.


[20] EI RW 0x0 Error Interrupt Enable

This bit is used to control the issue of an error interrupt (EDIRQ). If this bit is set to 1, an error interrupt is issued due to any of the following transfer errors:

- Transfer stop request by disable the transfer with DMAi_An:EB or DMAi_R:DE.

- Source access error.

- Destination access error.

0: Error interrupt issuance is disabled. (Ini-tial value)

1: Error interrupt issuance is enabled.

[19] CI RW 0x0 Completion Interrupt Enable

This bit is used to control the issue of a completion interrupt (DIRQ). If this bit is set to 1, a completion interrupt is issued after the DMA transfer completed normally.

0: Completion interrupt issuance is dis-abled. (Initial value)

1: Completion interrupt issuance is enabled.





[18:16] SS R 0x0 Stop Status

These bits are used to show the end code of DMA transfer. SS is set by hardware when an error or completion interrupt is raised and it is cleared by hardware when either DMAi_Cn:CE or DMAi_Cn:CD is set to 1.

SS Description Status type

000 Initial value None

001 Reserved n/a

010 Stop Request by Stop

- Channel disable (DMAi_An:EB=0) or

- DMA disable (DMAi_R:DE=0) )

011 Source access error Error

100 Destination access error Error

101 Normal end End

110 Reserved n/a

111 Reserved n/a

When different events occur at the same time, the end code is displayed according to the following priority:

Priority

Highest Reset

. Cleared by clearing completion/error interrupt (DIRQ/EDIRQ)

. Source access error

. Destination access error

Lowest Stop request

Note: If the interrupt bit is cleared then Stop Status is also cleared.





[15:12] SP RW 0x3 Source Protection

These bits are used to control source access protection. During source accesses HPROTM is driven with SP during the AHB address phase.

SP[3]: 0: Not cacheable (Initial value)

1: Cacheable

SP[2]: 0: Not bufferable (Initial value)

1: Bufferable

SP[1]: 0: User access

1: Privileged access (Initial value)

SP[0]: 0: Instruction access (DMAC will only make data accesses thus SP[0] is fixed to 1 and writing it to 0 has no effect.)

1: Data access (Initial value)

SP will only be considered by sources which support protection control function.

[11:8] DP RW 0x3 Destination Protection

These bits are used to control destination access protection. During destination accesses HPROTM is driven with DP dur-ing the AHB address phase.

DP[3]: 0: Not cacheable (Initial value)

1: Cacheable

DP[2]: 0: Not bufferable (Initial value)

1: Bufferable

DP[1]: 0: User access


DP[0]: 0: Instruction access (DMAC will only make data accesses thus DP[0] is fixed to 1 and writing it to 0 has no effect.)


DP will only be considered by destinations which support protection control function.


[6:0] PN RW 0x7F Priority Number

These bits are used to specify the Priority Number. The Priority Number is needed if Fixed Priority or Dynamic Priority has been selected as arbitration scheme. It has no significance if Round Robin arbitration scheme is selected. The channel with lower priority number value will have a higher pri-ority.





DMAi_SA0

Description: DMAC Channel Configuration Source Address Register Channel 0



Table 3-490: DMAi_SA0 Register


[31:0] SA RW 0x0 Source Address

These bits are used to specify the source address to start a DMA transfer. Source Address is updated with the value of DMAi_SASHDW at the end of a DMA transfer if Update Source Address (DMAi_Dn:US) is set to 1, Fixed Block Source Address (DMAi_Dn:FBS) is set to 0, and the transfer ended successfully. Oth-erwise it will retain its value.

Warning: DMAi_SAn register must be loaded with aligned addresses with respect to the transfer width. If non-aligned addresses are loaded the DMAC will con-vert it to an aligned address according to the setting of Transfer Width (DMAi_Bn:TW).



DMAi_DA0

Description: DMAC Channel Configuration Destination Address Register Channel 0



Table 3-491: DMAi_DA0 Register


[31:0] DA RW 0x0 Destination Address

These bits are used to specify the destina-tion address to start a DMA transfer. Desti-nation Address is updated with the value of DMAi_DASHDW at the end of a DMA transfer if Update Destination Address (DMAi_Dn:UD) is set to 1, Fixed Block Des-tination Address (DMAi_Dn:FBD) is set to 0, and the transfer ended successfully. Oth-erwise it will retain its value.

Warning: DMAi_DAn register must be loaded with aligned addresses with respect to the transfer width. If non-aligned addresses are loaded the DMAC will con-vert it to an aligned address according to the setting of Transfer Width (DMAi_Bn:TW).



DMAi_C0

Description: DMAC Channel Configuration C Register Channel 0



Table 3-492: DMAi_C0 Register



[8] CE WP1 0x0 Clear EDIRQ

Setting this bit clears the EDIRQ flag bit (DMAi_Bn:EQ). DMAC will clear this bit automatically.


[0] CD WP1 0x0 Clear DIRQ

Setting this bit clears the DIRQ flag bit (DMAi_Bn:DQ). DMAC will clear this bit automatically.



DMAi_D0

Description: DMAC Channel Configuration D Register Channel 0



Table 3-493: DMAi_D0 Register


[31] FS RW 0x0 Fixed Source Address

This bit is used to keep the source address at a fix value.

0: Source address is incremented. (Initial value)

1: Source address is kept fix. AHB Master will only make SINGLE transfers to access the source.

[30] DES RW 0x0 Decrement Source Address

If this bit is set the source address on the AHB interface is decremented on each AHB transfer. In this mode the AHB Master will make only SINGLE transfers to access the source.

0: Source address will be incremented. (Initial value)

1: Source address will be decremented.

Note: Fixed Source Address (FS) has higher priority than Decrement Source Address. This bit is only effective if FS = 0 and FBS = 0.

[29] US RW 0x0 Update Source Address

0: DMAi_SAn is NOT updated after DMA transfer was successfully completed. DMAi_SAn is retained. (Initial value)

1: DMAi_SAn is updated with the next address after the DMA transfer was suc-cessfully completed. E.g. last source address was 0x0BF000FC, DMAi_Bn:TW = 10 (Word) then DMAi_SAn will be updated with address 0x0BF00100.

Note: This bit is only effective if FBS = 0



[28] FBS RW 0x0 Fixed Block Source Address

0: Start address of first block of DMA trans-fer is set to the value stored in DMAi_SAn. Start address of consecutive blocks is the address following the previous block last address (according to Transfer Width (DMAi_Bn:TW)). (Initial value)

1: Start address of each block is set to the value stored in DMAi_SAn.

Note: Setting of FBS is only effective if FS = 0 and (DMAi_Bn:MS = 00 (Block transfer mode) or DMAi_Bn:MS = 01 (Burst transfer mode)).


[15] FD RW 0x0 Fixed Destination Address

This bit is used to keep the destination address at a fix value.

0: Destination address is incremented. (Ini-tial value)

1: Destination address is kept fix. AHB Master will only make SINGLE transfers to access the destination.

[14] DED RW 0x0 Decrement Destination Address

If this bit is set the destination address on the AHB interface is decremented on each AHB transfer. In this mode the AHB Master will make only SINGLE transfers to access the destination.

0: Destination address will be incre-mented. (Initial value)

1: Destination address will be decre-mented.

Note: Fixed Destination Address (FD) has higher priority than Decrement Destination Address. This bit is only effective if FD = 0 and FBD = 0.

[13] UD RW 0x0 Update Destination Address

0: DMAi_DAn is NOT updated after DMA transfer was successfully completed. DMAi_DAn is retained. (Initial value)

1: DMAi_DAn is updated with the next address after the DMA transfer was suc-cessfully completed. E.g. last destination address was 0x0BF40010, DMAi_Bn:TW = 10 (Word) then DMAi_DAn will be updated with address 0x0BF40014.

Note: This bit is only effective if FBD = 0





[12] FBD RW 0x0 Fixed Block Destination Address

0: Start address of first block of DMA trans-fer is set to the value stored in DMAi_DAn. Start address of consecutive blocks is the address following the previous block last address (according to Transfer Width (DMAi_Bn:TW)). (Initial value)

1: Start address of each block is set to the value stored in DMAi_DAn.

Note: Setting of FBD is only effective if FD = 0 and (DMAi_Bn:MS = 00 (Block transfer mode) or DMAi_Bn:MS = 01 (Burst transfer mode)).






DMAi_SASHDW0

Description: DMAC Channel Configuration Source Address Shadow Register Channel 0



Table 3-494: DMAi_SASHDW0 Register


[31:0] SASHDW R 0x0 Source Address Shadow

At the start of a DMA transfer this register contains a copy of DMAi_SAn. During a DMA transfer it will be either incremented, decremented, or stays constant according to the settings of DMAi_Dn:FS, DMAi_Dn:DES, DMAi_Dn:US, and DMAi_Dn:FBS. In case of a source access error SASHDW shows the address of the read access which caused the error. In case of a stop of the DMA transfer it shows the next address following the last read access done.

Warning: SASHDW will not show an aligned address if a non-aligned address was loaded into DMAi_SAn initially. How-ever the DMAC will have made the read access to address SASHDW aligned according to the setting of Transfer Width (DMAi_Bn:TW).



DMAi_DASHDW0

Description: DMAC Channel Configuration Destination Address Shadow Register Channel 0



Table 3-495: DMAi_DASHDW0 Register


[31:0] DASHDW R 0x0 Destination Address Shadow

At the start of a DMA transfer this register contains a copy of DMAi_DAn. During a DMA transfer it will be either incremented, decremented, or stays constant according to the settings of DMAi_Dn:FD, DMAi_Dn:DED, DMAi_Dn:UD, and DMAi_Dn:FBD. In case of a destination access error DASHDW shows the address of the write access which caused the error. In case of a stop of the DMA transfer it shows the next address following the last write access done.

Warning: DASHDW will not show an aligned address if a non-aligned address was loaded into DMAi_DAn initially. How-ever the DMAC will have made the write access to address DASHDW aligned according to the setting of Transfer Width (DMAi_Bn:TW).



DMAi_A1

Description: DMAC Channel Configuration A Register Channel 1





[31] EB RW 0x0 Enable Bit

This bit is used to enable/disable a DMA channel. If this bit is set to 1, the channel is enabled and waits for a request to start a DMA transfer. (Before that, DMAi_R:DE bit needs to be set to 1 already.) If this bit is set to 0, the channel is disabled and does not perform a DMA transfer. When this bit is set to 0 during a running DMA transfer, the DMA transfer terminates at the next transfer gap. This is regarded as a forced stop and an error interrupt is generated. About the transfer gap, please refer to the description of DMAi_R:DE bit. This bit is useful to re-configure each configuration register of the channel after a DMA trans-fer.

0: Channel is disabled. (Initial value)

1: Channel is enabled.

[30] PB RW 0x0 Pause Bit

This bit is used to halt the transfer of the DMA channel. If this bit is set to 1, this channel halts the transfer and does not per-form a DMA transfer until this bit is cleared.

When this bit is set to 1 while no transfer is ongoing DMAC enters the halt state imme-diately. When it was set to 1 during a run-ning transfer, the halt state is entered at the next transfer gap. If the DMA transfer com-pletes at the next transfer gap a completion interrupt is issued.

When this bit is set to 0 the halt condition is cleared and DMAC waits for the next request to continue the DMA transfer.

This bit is useful to halt a DMA transfer without re-configuration of each configura-tion register of the channel.

0: Channel is not halted. (Initial value)

1: Channel is halted.



[29] ST R0W1

0x0 Software Trigger

This bit is used to generate a software request. This bit can only be set when DMAi_Bn:SR = 1 and the stop status is either initial or normal. When this bit is set to 1, DMA transfer is requested because software request has been received. The DMAC sets this bit to 0 if the Software Trig-ger has been recognized and an internal channel request for service was set and Software Trigger Ready (DMAi_Bn:SR) is set to 0. The software request was suc-cessful when DMAi_Bn:SR changes its sta-tus from 1 to 0. ST can only be read as 0.

0: No software request. (Initial value)

1: Software request.

[28:27] IS RW 0x0 Input Select

These bits are used to select the trigger source of a DMA transfer request. When the trigger source of a DMA transfer shall be a software request, IS bits must be set to 00. When the trigger source of a DMA transfer shall be a hardware request, IS bits must be set to 01.

00: Software request. (Initial value)

01: Hardware request.

10: Reserved.

11: Reserved.

Note: When the transfer mode is block transfer or burst transfer, edge detection is used. When the transfer mode is demand transfer, level detection is used.

[26] AL RW 0x0 Alternate

This bit decides whether the data transfers should alternate between Read and Write or should be contiguous Reads followed by contiguous Writes. The alternation will take place after each incremental read burst and after each single data read.

0: Contiguous. (Initial value)

1: Alternate.





[25:24] BL RW 0x0 Beat Limit

Beat Limit controls the maximum burst length the AHB Master can make on the AHB bus for this DMA channel.

00: Single Transfer (SINGLE). (Initial Value)




These bits are used in combination with Block Count to decide which type of burst has to be transmitted over the AHB inter-face.

[23:20] BC RW 0x0 Block Count

These bits specify the total length of a sin-gle block in block/burst transfer mode. The maximum block count is 16. For e.g. if BC = 4 the number of data transfers is 5 (BC+1).

Alternate, Block Count, and Beat Limit together decide the bursts generated by the AHB Master.

In demand transfer mode, Block Count has a different meaning, here it is used to deter-mine the max. number of data transfers that can be made in one arbitration phase.

[19:16] TO RW 0xF Timeout

Timeout is applicable only in Demand transfer mode. When signal DMA Request (DREQ) is de-asserted the Timeout count starts down counting on every DMAC clock cycle. If Timeout reaches zero, the DMAC finishes the current arbitration phase after completing the current data transfer, which allows the channel arbiter to arbitrate the next requesting channel.





[15:0] TC RW 0x0 Transfer Count

These bits are used to specify the transfer count for the block/burst/demand transfer. The maximum transfer count is 65536. If TC is set to 0 then 1 transfer will be done and if TC is set to 65535 then 65536 trans-fers will be done.

In burst and block transfer mode the TC represents the number of blocks of data transfers that the channel has to make before DMA 'End of Processing' is gener-ated. For e.g. if TC = 9 and BC = 9 then total number of transfers the DMAC does = (BC+1)*(TC+1) = 10*10 = 100 transfers.

In demand transfer mode, TC represents the maximum number of data transfers that the channel has to make. For example if TC = 99, then the channel can make 100 DMA transfers.





DMAi_B1

Description: DMAC Channel Configuration B Register Channel 1





[31] DQ R 0x0 Flag of DIRQ

DQ is set to 1 when a DMA transfer com-pleted successfully. DQ is cleared by hard-ware if DMAi_Cn:CD (clear DIRQ) bit is set to 1. Otherwise the value is retained.

[30] EQ R 0x0 Flag of EDIRQ

EQ is set to 1 when a DMA transfer is fin-ished with an error. EQ is cleared by hard-ware if DMAi_Cn:CE (clear EDIRQ) bit is set to 1. Otherwise the value is retained.

[29:28] MS RW 0x0 Mode Select

MS sets the transfer mode of the channel.

00: Block transfer mode (Initial value)

01: Burst transfer mode

10: Demand transfer mode

11: Reserved

[27:26] TW RW 0x0 Transfer Width

TW specifies the data width for every data transfer of the DMA transfer.

00: Byte (Initial value)

01: Half-Word

10: Word

11: Double Word



[25] SR R 0x1 Software Trigger Ready

This bit is used to signal that the DMA channel is ready to receive a software request. The following conditions can cause that the DMA channel is not ready to receive a software request. If one or more of the conditions below is true SR is set to 0 by hardware. If none of the conditions is true SR is set to 1 by hardware.

- DMAi_R:DE == 0; DMAC is disabled.

- DMAi_R:DH == 1; All DMA channels are halted.

- DMAi_An:EB == 0; DMA channel is dis-abled.

- DMAi_An:PB == 1; DMA channel is halted.

- DMAi_An:IS != 00; Input select is not set to Software.

- DMA transfer is active and a software request is pending.


[20] EI RW 0x0 Error Interrupt Enable

This bit is used to control the issue of an error interrupt (EDIRQ). If this bit is set to 1, an error interrupt is issued due to any of the following transfer errors:

- Transfer stop request by disable the transfer with DMAi_An:EB or DMAi_R:DE.

- Source access error.

- Destination access error.

0: Error interrupt issuance is disabled. (Ini-tial value)

1: Error interrupt issuance is enabled.

[19] CI RW 0x0 Completion Interrupt Enable

This bit is used to control the issue of a completion interrupt (DIRQ). If this bit is set to 1, a completion interrupt is issued after the DMA transfer completed normally.

0: Completion interrupt issuance is dis-abled. (Initial value)

1: Completion interrupt issuance is enabled.





[18:16] SS R 0x0 Stop Status

These bits are used to show the end code of DMA transfer. SS is set by hardware when an error or completion interrupt is raised and it is cleared by hardware when either DMAi_Cn:CE or DMAi_Cn:CD is set to 1.

SS Description Status type

000 Initial value None

001 Reserved n/a

010 Stop Request by Stop

- Channel disable (DMAi_An:EB=0) or

- DMA disable (DMAi_R:DE=0) )

011 Source access error Error

100 Destination access error Error

101 Normal end End

110 Reserved n/a

111 Reserved n/a

When different events occur at the same time, the end code is displayed according to the following priority:

Priority

Highest Reset

. Cleared by clearing completion/error interrupt (DIRQ/EDIRQ)

. Source access error

. Destination access error

Lowest Stop request

Note: If the interrupt bit is cleared then Stop Status is also cleared.





[15:12] SP RW 0x3 Source Protection

These bits are used to control source access protection. During source accesses HPROTM is driven with SP during the AHB address phase.

SP[3]: 0: Not cacheable (Initial value)

1: Cacheable

SP[2]: 0: Not bufferable (Initial value)

1: Bufferable

SP[1]: 0: User access


SP[0]: 0: Instruction access (DMAC will only make data accesses thus SP[0] is fixed to 1 and writing it to 0 has no effect.)


SP will only be considered by sources which support protection control function.

[11:8] DP RW 0x3 Destination Protection

These bits are used to control destination access protection. During destination accesses HPROTM is driven with DP dur-ing the AHB address phase.

DP[3]: 0: Not cacheable (Initial value)

1: Cacheable

DP[2]: 0: Not bufferable (Initial value)

1: Bufferable

DP[1]: 0: User access


DP[0]: 0: Instruction access (DMAC will only make data accesses thus DP[0] is fixed to 1 and writing it to 0 has no effect.)


DP will only be considered by destinations which support protection control function.


[6:0] PN RW 0x7F Priority Number

These bits are used to specify the Priority Number. The Priority Number is needed if Fixed Priority or Dynamic Priority has been selected as arbitration scheme. It has no significance if Round Robin arbitration scheme is selected. The channel with lower priority number value will have a higher pri-ority.





DMAi_SA1

Description: DMAC Channel Configuration Source Address Register Channel 1



Table 3-498: DMAi_SA1 Register


[31:0] SA RW 0x0 Source Address

These bits are used to specify the source address to start a DMA transfer. Source Address is updated with the value of DMAi_SASHDW at the end of a DMA transfer if Update Source Address (DMAi_Dn:US) is set to 1, Fixed Block Source Address (DMAi_Dn:FBS) is set to 0, and the transfer ended successfully. Oth-erwise it will retain its value.

Warning: DMAi_SAn register must be loaded with aligned addresses with respect to the transfer width. If non-aligned addresses are loaded the DMAC will con-vert it to an aligned address according to the setting of Transfer Width (DMAi_Bn:TW).



DMAi_DA1

Description: DMAC Channel Configuration Destination Address Register Channel 1



Table 3-499: DMAi_DA1 Register


[31:0] DA RW 0x0 Destination Address

These bits are used to specify the destina-tion address to start a DMA transfer. Desti-nation Address is updated with the value of DMAi_DASHDW at the end of a DMA transfer if Update Destination Address (DMAi_Dn:UD) is set to 1, Fixed Block Des-tination Address (DMAi_Dn:FBD) is set to 0, and the transfer ended successfully. Oth-erwise it will retain its value.

Warning: DMAi_DAn register must be loaded with aligned addresses with respect to the transfer width. If non-aligned addresses are loaded the DMAC will con-vert it to an aligned address according to the setting of Transfer Width (DMAi_Bn:TW).



DMAi_C1

Description: DMAC Channel Configuration C Register Channel 1



Table 3-500: DMAi_C1 Register



[8] CE WP1 0x0 Clear EDIRQ

Setting this bit clears the EDIRQ flag bit (DMAi_Bn:EQ). DMAC will clear this bit automatically.


[0] CD WP1 0x0 Clear DIRQ

Setting this bit clears the DIRQ flag bit (DMAi_Bn:DQ). DMAC will clear this bit automatically.



DMAi_D1

Description: DMAC Channel Configuration D Register Channel 1





[31] FS RW 0x0 Fixed Source Address

This bit is used to keep the source address at a fix value.

0: Source address is incremented. (Initial value)

1: Source address is kept fix. AHB Master will only make SINGLE transfers to access the source.

[30] DES RW 0x0 Decrement Source Address

If this bit is set the source address on the AHB interface is decremented on each AHB transfer. In this mode the AHB Master will make only SINGLE transfers to access the source.

0: Source address will be incremented. (Initial value)

1: Source address will be decremented.

Note: Fixed Source Address (FS) has higher priority than Decrement Source Address. This bit is only effective if FS = 0 and FBS = 0.

[29] US RW 0x0 Update Source Address

0: DMAi_SAn is NOT updated after DMA transfer was successfully completed. DMAi_SAn is retained. (Initial value)

1: DMAi_SAn is updated with the next address after the DMA transfer was suc-cessfully completed. E.g. last source address was 0x0BF000FC, DMAi_Bn:TW = 10 (Word) then DMAi_SAn will be updated with address 0x0BF00100.

Note: This bit is only effective if FBS = 0



[28] FBS RW 0x0 Fixed Block Source Address

0: Start address of first block of DMA trans-fer is set to the value stored in DMAi_SAn. Start address of consecutive blocks is the address following the previous block last address (according to Transfer Width (DMAi_Bn:TW)). (Initial value)

1: Start address of each block is set to the value stored in DMAi_SAn.

Note: Setting of FBS is only effective if FS = 0 and (DMAi_Bn:MS = 00 (Block transfer mode) or DMAi_Bn:MS = 01 (Burst transfer mode)).


[15] FD RW 0x0 Fixed Destination Address

This bit is used to keep the destination address at a fix value.

0: Destination address is incremented. (Ini-tial value)

1: Destination address is kept fix. AHB Master will only make SINGLE transfers to access the destination.

[14] DED RW 0x0 Decrement Destination Address

If this bit is set the destination address on the AHB interface is decremented on each AHB transfer. In this mode the AHB Master will make only SINGLE transfers to access the destination.

0: Destination address will be incre-mented. (Initial value)

1: Destination address will be decre-mented.

Note: Fixed Destination Address (FD) has higher priority than Decrement Destination Address. This bit is only effective if FD = 0 and FBD = 0.

[13] UD RW 0x0 Update Destination Address

0: DMAi_DAn is NOT updated after DMA transfer was successfully completed. DMAi_DAn is retained. (Initial value)

1: DMAi_DAn is updated with the next address after the DMA transfer was suc-cessfully completed. E.g. last destination address was 0x0BF40010, DMAi_Bn:TW = 10 (Word) then DMAi_DAn will be updated with address 0x0BF40014.

Note: This bit is only effective if FBD = 0





[12] FBD RW 0x0 Fixed Block Destination Address

0: Start address of first block of DMA trans-fer is set to the value stored in DMAi_DAn. Start address of consecutive blocks is the address following the previous block last address (according to Transfer Width (DMAi_Bn:TW)). (Initial value)

1: Start address of each block is set to the value stored in DMAi_DAn.

Note: Setting of FBD is only effective if FD = 0 and (DMAi_Bn:MS = 00 (Block transfer mode) or DMAi_Bn:MS = 01 (Burst transfer mode)).






DMAi_SASHDW1

Description: DMAC Channel Configuration Source Address Shadow Register Channel 1



Table 3-502: DMAi_SASHDW1 Register


[31:0] SASHDW R 0x0 Source Address Shadow

At the start of a DMA transfer this register contains a copy of DMAi_SAn. During a DMA transfer it will be either incremented, decremented, or stays constant according to the settings of DMAi_Dn:FS, DMAi_Dn:DES, DMAi_Dn:US, and DMAi_Dn:FBS. In case of a source access error SASHDW shows the address of the read access which caused the error. In case of a stop of the DMA transfer it shows the next address following the last read access done.

Warning: SASHDW will not show an aligned address if a non-aligned address was loaded into DMAi_SAn initially. How-ever the DMAC will have made the read access to address SASHDW aligned according to the setting of Transfer Width (DMAi_Bn:TW).



DMAi_DASHDW1

Description: DMAC Channel Configuration Destination Address Shadow Register Channel 1



Table 3-503: DMAi_DASHDW1 Register


[31:0] DASHDW R 0x0 Destination Address Shadow

At the start of a DMA transfer this register contains a copy of DMAi_DAn. During a DMA transfer it will be either incremented, decremented, or stays constant according to the settings of DMAi_Dn:FD, DMAi_Dn:DED, DMAi_Dn:UD, and DMAi_Dn:FBD. In case of a destination access error DASHDW shows the address of the write access which caused the error. In case of a stop of the DMA transfer it shows the next address following the last write access done.

Warning: DASHDW will not show an aligned address if a non-aligned address was loaded into DMAi_DAn initially. How-ever the DMAC will have made the write access to address DASHDW aligned according to the setting of Transfer Width (DMAi_Bn:TW).



DMAi_R

Description: DMAC Global Configuration Register



Table 3-504: DMAi_R Register


[31] DE RW 0x0 DMA Enable

If this bit is set to 0, the DMAC is disabled. This also means that all DMA channels are disabled independent of the settings of DMAi_An:EB.

If this bit is set to 1, the DMAC is enabled and the enabling of the channels depend on the setting of DMAi_An:EB.

When this bit is set to 0 during a DMA transfer, the channel which is in the middle of a transfer stops at the next transfer gap.

The transfer gap means that DMAC de-asserts bus request to the bus arbiter for a short time in the middle of a DMA transfer after a block of data has been transferred. This ensures that the bus is not completely blocked by a very long DMA transfer.

0: DMAC globally disabled. (Initial value)

1: DMAC globally enabled.

[30] DSHR R 0x1 DMA Stop/Halt Request Flag

This bit indicates that the DMA transfers of all channels have been requested to halt or disable.

This bit is set to 0 by hardware if none of the conditions below is true.

This bit is set to 1 by hardware if one or more of the conditions below is true.

Conditions for DMA Stop/Halt Request Flag:

- DMAi_R:DE is set to 0 (all channels are disabled)

- DMAi_R:DH is set to 1 (all channels are halted)

0: Indicates that global halt/disable condi-tion of DMAC is removed.

1: Indicates that DMA transfers of all chan-nels are requested to halt or disable. (Initial value)




[28:27] PR RW 0x0 Priority Type

These bits select the arbitration scheme of the DMAC Arbiter. In case of Dynamic Pri-ority, channel priority is updated at the transfer gap.

00: Fixed Priority. (Initial value)

01: Dynamic Priority.

10: Round Robin.

11: Reserved

[26] DH RW 0x0 DMA Halt

When this bit is set to a 1, all DMA chan-nels are halted and do not perform DMA transfers until this bit is set back to 0. After it is cleared the halted DMA transfers con-tinue at the point they were halted.

If this bit is set to 1 while a DMA transfer is ongoing, DMAC halts the transfer at the next transfer gap.

About the transfer gap, please refer to the description of DE bit.



[0] DSHS R 0x1 DMA Stop/Halt Status Flag

0: Indicates that DMA transfer of at least one channel is running.

1: Indicates that DMA transfers of all chan-nels are halted or disabled. (Initial value)

Table 3-504: DMAi_R Register




DMAi_DIRQ1

Description: DMAC Global Completion Interrupt 1 Register



Table 3-505: DMAi_DIRQ1 Register


[31:0] DIRQ R 0x0 Global Completion Interrupt 1

This is a read only register which gives the status of DIRQ of channels 0 to 31. Chan-nels which are not available on a particular device will read 0.



DMAi_DIRQ2

Description: DMAC Global Completion Interrupt 2 Register



Table 3-506: DMAi_DIRQ2 Register


[31:0] DIRQ R 0x0 Global Completion Interrupt 2

This is a read only register which gives the status of DIRQ of channels 32 to 63. Chan-nels which are not available on a particular device will read 0.



DMAi_EDIRQ1

Description: DMAC Global Error Interrupt 1 Register



Table 3-507: DMAi_EDIRQ1 Register


[31:0] EDIRQ R 0x0 Global Error Interrupt 1

This is a read only register which gives the status of EDIRQ of channels 0 to 31. Chan-nels which are not available on a particular device will read 0.



DMAi_EDIRQ2

Description: DMAC Global Error Interrupt 2 Register



Table 3-508: DMAi_EDIRQ2 Register


[31:0] EDIRQ R 0x0 Global Error Interrupt 2

This is a read only register which gives the status of EDIRQ of channels 32 to 63. Channels which are not available on a par-ticular device will read 0.



DMAi_ID

Description: DMAC ID Register



Table 3-509: DMAi_ID Register


[31:0] MID R 0x0 Module Number

This read-only register gives the unique module identification number of the DMAC module.

The unique module ID number identifies the version of the DMAC module used in the MCU.

Refer to the device specific datasheet for the module identification number of the DMAC.



DMAi_CMICIC0

Description: DMAC Client Matrix Internal Client Interface Configuration Register 0 (for Client 8)



Table 3-510: DMAi_CMICIC0 Register





[25] BEHREQACK RW 0x0 Behaviour Request Acknowledge

BEHREQACK sets the behaviour of the Internal DMA Client Interface j output signal DREQ_ACK[j] if the client interface is not selected in any of the Channel Configura-tion registers (DMAi_CMCHICn).

Note: This configuration bit is read0 if the associated peripheral is not available in a particular device. Please refer to the data-sheet for its availability.

0: DREQ_ACK[j] outputs inactive logic level. (Initial value)

1: DREQ[j] connected directly to DREQ_ACK[j].




DMAi_CMICIC1

















DMAi_CMICIC2

















DMAi_CMICIC3



Instance no 0: 0x0002A02C














DMAi_CMICIC4

















DMAi_CMICIC5

















DMAi_CMICIC6

















DMAi_CMICIC7

















DMAi_CMICIC8

















DMAi_CMICIC9

















DMAi_CMICIC10

















DMAi_CMICIC11

















DMAi_CMICIC12

















DMAi_CMICIC13

















DMAi_CMICIC14

















DMAi_CMICIC15

















DMAi_CMICIC16

















DMAi_CMICIC17

















DMAi_CMICIC18

















DMAi_CMICIC19

















DMAi_CMICIC20

















DMAi_CMICIC21

















DMAi_CMCHIC0

Description: DMAC Client Matrix Channel Interface Configuration Register 0



Table 3-532: DMAi_CMCHIC0 Register



[8:0] CI RW 0x0 Client Interface

Client Interface specifies that DMA channel n is routed to the DMA Client given by the binary value of CI.



DMAi_CMCHIC1

Description: DMAC Client Matrix Channel Interface Configuration Register 1



Table 3-533: DMAi_CMCHIC1 Register



[8:0] CI RW 0x0 Client Interface

Client Interface specifies that DMA channel n is routed to the DMA Client given by the binary value of CI.




3.6 Command Sequencer Registers

In this section, the ‘Register Overview’ table summarizes all Command Sequencer registers, includingbase address of the module and name, description, and the absolute address of each register, whichare then described separately in the following tables.



3.6.1 Command Sequencer Register Overview


Base Address(es) Instance no 0: BASEADDR="0002C000"


BASEADDR + 0x0000 FIFOBuffer Command input buffer

BASEADDR + 0x0100 FIFOStatus Status register

BASEADDR + 0x0104 FIFOControl Control register

BASEADDR + 0x0108 FIFOWatermarkControl Watermark Control register




BASEADDR + 0x0204 Status Status register

BASEADDR + 0x0208 Control Control register







FIFOBuffer

Description: Command input buffer



Table 3-535: FIFOBuffer Register


[31:0] FIFOBuffer RW X Reading always returns 0



FIFOStatus

Description: Status register



Table 3-536: FIFOStatus Register



[26] FIFOWMState R 0x0 Water mark state

[25] FIFOFull R 0x0 Command FIFO full flag

[24] FIFOEmpty R 0x1 Command FIFO empty flag


[16:0] FIFOSpace R 0x20 Available space in command FIFO



FIFOControl

Description: Control register



Table 3-537: FIFOControl Register


[31] FIFOClear R0W1

0x0 Clear command buffer by writing a 1




FIFOWatermarkControl

Description: Watermark Control register



Table 3-538: FIFOWatermarkControl Register


[31:16] FIFOHighWM RW 0x18 High water mark

[15:0] FIFOLowWM RW 0x8 Low water mark



Status

Description: Status register



Table 3-539: Status Register








[25] Error0 R 0x0 Execution of core #0 stopped after illegal instruction

0: Ready

1: Error

[24] Halt0 R 0x0 Halt status of core #0

0: Ready

1: Halt


[8] Watchdog R 0x0 Watchdog expired

0: Watchdog not expired

1: Watchdog expired


[0] Idle R 0x0 Idle state

0: Operating

1: Idle



Control

Description: Control register



Table 3-540: Control Register






[1] Terminate RW 0x0 Force termination; Core #0 will enter halt state

[0] Restart R0W1

0x0 Restart core #0 when hanging in Error or Halt state by writing a 1




3.7 Internal Flash Memory Registers

In this section, the ‘Register Overview’ table summarizes all internal flash memory registers, includingbase address of the module and name, description, and the absolute address of each register, whichare then described separately in the following tables.



3.7.1 Internal Flash Control Register Overview


Base Address(es) Instance no 0: BASEADDR="0002D000"


BASEADDR + 0x0000 TCFCFG_FCPROTKEY Flash Configuration Protection Key Register


BASEADDR + 0x0008 TCFCFG_FCFGR Flash Configuration Register


BASEADDR + 0x0010 TCFCFG_FECCCTRL Flash ECC Control Register




BASEADDR + 0x0020 TCFCFG_FICTRL0 Flash Interrupt Control Register 0






BASEADDR + 0x0038 TCFCFG_FSTAT0 Flash Status Register 0






BASEADDR + 0x0050 TCFCFG_FSECIR Flash SEC Interrupt Register

BASEADDR + 0x0054 TCFCFG_FECCEAR Flash ECC Error Address Register












TCFCFG_FCPROTKEY

Description: Flash Configuration Protection Key Register



Table 3-542: TCFCFG_FCPROTKEY Register


[31:0] FCPROTKEY RW 0x0 Flash Configuration Protection Key

This register protects the Flash Configura-tion Register (TCFCFG_FCFGR) and Flash ECC Control Register (TCFCFG_FECCCTRL) from accidental modification by software.

Writing correct key value (0xCF61F1A5) to this register unlocks write access to TCFCFG_FCFGR and TCFCFG_FECCCTRL registers.

Writing any other value to this register causes data abort.

Reading this register always returns 0xFFFFFFFF when write access to TCFCFG_FCFGR and TCFCFG_FECCCTRL is unlocked.

Reading this register always returns 0x00000000 when write access to TCFCFG_FCFGR and TCFCFG_FECCCTRL is locked (default).



TCFCFG_FCFGR

Description: Flash Configuration Register



Table 3-543: TCFCFG_FCFGR Register



[6] SWFRST R0WPS1

0x0 Software Triggered Flash Reset

This bit is used to reset Flash macro by software.

'0': No effect

'1': Triggers Flash macro reset. As soon as TCFCFG_FSTATn:RDY flag is read as '1', the Flash macro is ready for reading or writ-ing next command

Reading this bit returns '0'.

[5] Reserved RWPS

0x0 -

[4] WE RWPS

0x0 Flash Write Enable

This bit enables/disables writing to the Flash.

'0': Flash write is disabled (default)

'1': Flash write is enabled

Write access to Flash with this bit set to '0' results into bus error.

Setting this bit to '1' reduces read perfor-mance as prefetch access to the inter-leaved address is disabled with this bit set to '1', to avoid hardware sequence flags (of Flash program) and prefetch disturb each other.


[1:0] Reserved RWPS

0x3 -



TCFCFG_FECCCTRL

Description: Flash ECC Control Register



Table 3-544: TCFCFG_FECCCTRL Register



[0] ECCOFF RWPS

0x0 ECC Disable/Switch-Off

This bit disables ECC generation and checking for AXI accesses.

'0': ECC generation/checking is ON (default)

'1': ECC generation/checking is OFF

This register can be written once, further writes are blocked and signaled as error.



TCFCFG_FICTRL0

Description: Flash Interrupt Control Register 0



Table 3-545: TCFCFG_FICTRL0 Register



[10] WR32FC R0W1

0x0 32-bit Write Flag Clear

'0': No effect

'1': Clears TCFCFG_FSTATn:WR32F bit (32-bit write control flag)


[9] HANGIC R0W1

0x0 Hangup-1 Interrupt Clear

'0': No effect

'1': Clears TCFCFG_FSTATn:HANGINT bit (hangup-1 interrupt status bit)


[8] RDYIC R0W1

0x0 Flash Ready Interrupt Clear

'0': No effect

'1': Clears TCFCFG_FSTATn:RDYINT bit (Flash ready interrupt status bit)



[1] HANGIE RW 0x0 Hangup-1 Interrupt Enable

'0': Disables hangup-1 interrupt (default)

'1': Enables hangup-1 interrupt

[0] RDYIE RW 0x0 Flash Ready Interrupt Enable

'0': Disables Flash ready interrupt (default)

'1': Enables Flash ready interrupt



TCFCFG_FSTAT0

Description: Flash Status Register 0



Table 3-546: TCFCFG_FSTAT0 Register



[9] HANGINT R 0x0 Hangup-1 Interrupt

This bit is set at the rising edge of HANG output of Flash.

This bit is cleared by writing '1' to TCFCFG_FICTRLn:HANGIC (hangup-1 interrupt clear) bit.

'0': Hangup-1 condition has not occurred (default)

'1': Hangup-1 condition has occurred

[8] RDYINT R 0x0 Flash Ready Interrupt

This bit is set on the rising edge of RDY output of Flash.

This bit is cleared by writing '1' to TCFCFG_FICTRLn:RDYIC (RDY interrupt clear) bit.

'0': Rising edge of Flash RDY output is not detected (default)

'1': Rising edge of Flash RDY output is detected (i.e. Flash write or erase operation is completed)


[4] WR32F R 0x0 32-bit Write Control Flag

This bit is valid only for 32-bit write accesses.

This bit is toggled every time a Flash write sequence is completed.

This bit can be cleared by writing '1' to TCFCFG_FICTRLn:WR32FC (32-bit write flag clear) bit.

This bit is also cleared if TCFCFG_FCFGR:WE bit is '0'.

'0': Flash interface writes lower half-word to Flash (default)

'1': Flash interface writes upper half-word to Flash with ECC. ECC check is disabled temporarily when this bit is '1'




[1] HANG R 0x0 Hangup-1 Status

This bit reflects the status of (sampled) 'HANG' output of Flash macro.

This bit indicates whether Flash macro is in hangup-1 state or not.

'0': Flash macro is in normal operation (default)

'1': Flash macro is in hangup-1 state

This bit is set to '1' in any of the following conditions.

- Writing '1' to a memory cell containing '0'

- Automatic algorithm is not completed within restricted time

Note: When Flash macro enters hangup-1 state, it can be brought back to normal state by hard reset or by reset command or by software triggered Flash reset (i.e. TCFCFG_FCFGR:SWFRST).

[0] RDY R 0x0 Flash Ready Status

This bit reflects the status (sampled) of Flash RDY output.

This bit indicates whether Flash macro is ready to accept new command or not.

'0': Flash auto-algorithm (write or erase) is in progress, only read or suspend com-mand is accepted

'1': Flash is returned from auto-algorithm (write or erase) and is ready for new com-mand (default)

RDY output (and so is this bit) also goes low during Flash reset and is set to '1' after reset completion.

Table 3-546: TCFCFG_FSTAT0 Register




TCFCFG_FSECIR

Description: Flash SEC Interrupt Register



Table 3-547: TCFCFG_FSECIR Register



[16] SECINT R 0x0 ECC Single Error Correction Interrupt

This read-only bit is set when single error is detected or corrected during ECC check-ing.

This bit is cleared by writing '1' to TCFCFG_FSECIR:SECIC (ECC single error interrupt clear) bit.

'0': ECC single error has not occurred (default)

'1': ECC single error has occurred


[8] SECIC R0W1

0x0 ECC Single Error Correction Interrupt Clear

'0': No effect

'1': Clears TCFCFG_FSECIR:SECINT (ECC single error interrupt) bit



[0] SECIE RW 0x0 ECC Single Error Correction Interrupt Enable

'0': Disables ECC single error correction interrupt (default)

'1': Enables ECC single error correction interrupt



TCFCFG_FECCEAR

Description: Flash ECC Error Address Register



Table 3-548: TCFCFG_FECCEAR Register


[31:0] FECCEAR R 0x0 Flash ECC Error Address Register

This read-only register contains the Flash address where ECC single bit error has occurred and it is always the latest address where the ECC single bit error has occurred.

This address may be helpful to mark the memory location as a weak cell.




3.8 ConfigFIFO Registers

In this section, the ‘Register Overview’ table summarizes all ConfigFIFO registers, including baseaddress of the module and name, description, and the absolute address of each register, which are thendescribed separately in the following tables.


3.8.1 Configuration FIFO Register Overview


Base Address(es) Instance no 0: BASEADDR="0002E000"


BASEADDR + 0x0000 FFISTS Interrupt status flags.

BASEADDR + 0x0004 FFIEN Interrupt Enable register. '1' enables.



BASEADDR + 0x0010 CFG_IDLE The state of all the channels is shown.

BASEADDR + 0x0014 CHPriority Priority of Trigger Request.

BASEADDR + 0x0100 SW_RT0 Software Reset and Trigger

BASEADDR + 0x0104 FFCfg0 The function of FIFO is set up.

BASEADDR + 0x0108 FFB0

This address sets the boundary address of sharing FIFO. Do not overlap that each channels boundary area setting. When the area overlaps, the operation guarantee cannot be done. When using this channel, it sets up so that it may be set to 'UpperBoundAdr >= LowerBoundAdr'. The maximum size for 'UpperBoundAdr - LowerBoundAdr' is 0x1FE.

BASEADDR + 0x010C FFT0Sets the threshhold level for the corresponding FIFO in Bytes.

BASEADDR + 0x0110 DestAddress0 Local AHB-master transfer Destination address

BASEADDR + 0x0114 AdrCfg0 Address generation Configuration

BASEADDR + 0x0118 TransferCfg0 Local AHB master transfer Configuration

BASEADDR + 0x011C FFStatus0 Status Register

BASEADDR + 0x0120 FFISTS_TH0

Interrupt status flags, a '1' signifies that the corresponding interrupt condition occurred (even if interrupt is disabled), write '1' clears the flag. Even if the factor of Interrupt is can-celled (e.g. not empty), Or if an external clear signal is set to 1, this bit will be cleared automatically. When the rising edge and StatusClear of an interrupt factor happen simulta-neously, Status Register gives priority to an interrupt factor.

BASEADDR + 0x0124 FFIEN_TH0 Interrupt Enable register. '1' is enable.


BASEADDR + 0x012C FFIEN_DW0 Interrupt Enable register. '1' is enable.

BASEADDR + 0x0130 READ_CNT0

32 Bit Counter. Is incremented with every read from the FIFO. This does not correspond with the size of the read (e.g. WORD, HALF WORD or BYTE). For each access regardless of size the counter is incremented by one. An overflow will occur at the boundary of 32 Bit.

BASEADDR + 0x0134 WRITE_CNT0

32 Bit Counter. Is incremented with every write from the FIFO. This does not correspond with the size of the write (e.g. WORD, HALF WORD or BYTE). For each access regardless of size the counter is incremented by one. An overflow will occur at the boundary of 32 Bit.

BASEADDR + 0x0138 INT_READ_ADDR0

Readback register for the read address pointer to the FIFO. NOTE: This is an internal address. It is derived from the lower bound address but translated internally (left shift by three '0'). The value is the next address that will be read from. For an example refer to the chapter 'Readback address pointers'.

BASEADDR + 0x013C INT_WRITE_ADDR0

Readback register for the current write address pointers to the FIFO. NOTE: These are internal addresses. They are derived from the lower bound address but translated inter-nally (left shift by three '0'). The value is the last address that has been written to. For an example refer to the chapter 'Readback address pointers'.



BASEADDR + 0x0140 FFEDataInL0 Last FIFO Data In Lower

BASEADDR + 0x0144 FFEDataInU0 Last FIFO Data In Upper

BASEADDR + 0x0148 FFDataInL0 FIFO Data In Lower

BASEADDR + 0x014C FFDataInU0 FIFO Data In Upper

BASEADDR + 0x0150 FFDataSize0 Number of bytes that will be written to the FIFO

BASEADDR + 0x0154 MetaDestAddress0

Local AHB-master transfer Destination address for Meta Command operation. NOTEs: The first and the last com-mand to in a transmission sequence cannot be a meta com-mand! The Meta address register has to be always written prior to the Meta Config register! For transmissions sequences that contain meta command only indefinite length bursts can be configured (for both fields 'MetaTrans-ferINCR' and 'TransferINCR')!

BASEADDR + 0x0158 MetaCfg0

Local AHB master transfer and address generation Config-uration for Meta Command operation. NOTEs: The first and the last command to in a transmission sequence cannot be a meta command! The Meta address register has to be always written prior to the Meta Config register! For trans-missions sequences that contain meta command only indef-inite length bursts can be configured (for both fields 'MetaTransferINCR' and 'TransferINCR')!










BASEADDR + 0x01A0 FFISTS_TH1


BASEADDR + 0x01A4 FFIEN_TH1 Interrupt Enable register. '1' is enable.

BASEADDR + 0x01A8 Reserved Do not modify

BASEADDR + 0x01AC FFIEN_DW1 Interrupt Enable register. '1' is enable.

BASEADDR + 0x01B0 READ_CNT1


BASEADDR + 0x01B4 WRITE_CNT1







BASEADDR + 0x01B8 INT_READ_ADDR1


BASEADDR + 0x01BC INT_WRITE_ADDR1


BASEADDR + 0x01C0 FFEDataInL1 Last FIFO Data In Lower

BASEADDR + 0x01C4 FFEDataInU1 Last FIFO Data In Upper

BASEADDR + 0x01C8 FFDataInL1 FIFO Data In Lower

BASEADDR + 0x01CC FFDataInU1 FIFO Data In Upper

BASEADDR + 0x01D0 FFDataSize1 Number of bytes that will be written to the FIFO

BASEADDR + 0x01D4 MetaDestAddress1


BASEADDR + 0x01D8 MetaCfg1




















FFISTS

Description: Interrupt status flags.A '1' signifies that the corresponding interrupt condition occurred (even if interrupt isdisabled), write '1' clears the flag. Even if the factor of the interrupt is cancelled (e.g. notempty) or if an external clear signal is set to 1, this bit will be cleared automatically. When therising edge and StatusClear of an interrupt factor happen simultaneously, Status Registergives priority to an interrupt factor.



Table 3-550: FFISTS Register


[31] IStsOverFlow7 RW1C

0x0 Interrupt Status for condition: FIFO over-flow, FIFO input written during FIFO full, no data is overwritten, data is skipped, the application must avoid this situation! This bit will be cleared if "1" is written in this reg-ister or an i_OF_INT_clr[7] signal is set to "1."

[30] IStsUnderFlow7 RW1C

0x0 Interrupt Status for condition: FIFO under-flow, FIFO output triggered during FIFO empty. This bit will be cleared if "1" is writ-ten in this register or an i_UF_INT_clr[7] signal is set to "1."


[28] SLV_ERR7 RW1C

0x0 Interrupt Status for condition: AHB Slave module signal HRESP is set to ERROR. This bit will be cleared if "1" is written in this register or an i_VAR_INT_clr signal is set to "1."






[24] SLV_ERR6 RW1C









[20] SLV_ERR5 RW1C







[16] SLV_ERR4 RW1C











[12] SLV_ERR3 RW1C







[8] SLV_ERR2 RW1C







[4] SLV_ERR1 RW1C











[0] SLV_ERR0 RW1C






FFIEN

Description: Interrupt Enable register. '1' enables.



Table 3-551: FFIEN Register


[31] IEnOverFlow7 RW 0x0 Interrupt enable. This bit controls the output to o_OF_INT[7] in a IStsOverFlow7 bit of the Status Register.

[30] IEnUnderFlow7 RW 0x0 Interrupt enable. This bit controls the output to o_UF_INT[7] in a IStsUnderFlow7 bit of the Status Register.


[28] IESLV_ERR7 RW 0x0 Interrupt enable. This bit controls the output to o_VAR_INT in a SLV_ERR7 bit of the Status Register.















[15] IEnOverFlow3 RW 0x0 Interrupt enable. This bit controls the output to o_UF_INT[3] in a IStsOverFlow3 bit of the Status Register.
















Table 3-551: FFIEN Register




CFG_IDLE

Description: The state of all the channels is shown.



Table 3-552: CFG_IDLE Register



[0] CFG_IDLE R 0x0 ConfigFIFO IDLE

0: IDLE - All the channels of the Config-FIFO are in the idle state

1: ACTIVE - Some channels are in an active state.



CHPriority

Description: Priority of Trigger Request.Set up by initial setting before a trigger request comes. If a value is changed during operation,correct operation can not be guaranteed.



Table 3-553: CHPriority Register



[2:0] Priority RW 0x0 Trigger Priority select.

0: Ch0 - Priority High Ch0 - Ch1 - Ch2 - Ch3 - Ch4 - Ch5 - Ch6 - Ch7 Priority Low










SW_RT0

Description: Software Reset and Trigger



Table 3-554: SW_RT0 Register



[2] SW_Trigger0 RW1C

0x0 Software Trigger triggers the FIFO channel 0. A single trigger pulse is generated when "1" is written to the register. This register is cleared automatically to "0" again after writ-ing "1".

[1] SW_RW_CNT_Reset0 RW 0x0 Software Reset for the Read/Write Counter only (Registers READ_CNT0 and WRITE_CNT0). Counters are reset when "1" is written to SW_RW_CNT_ResetX. If "0" is written, reset is released.

[0] SWReset0 RW 0x0 Software reset (flush FIFO0, resets DMA target address counter).

ConfigFIFO register is not cleared. Trigger request is not permitted when SWReset is "1." After checking that the state of FFStates register is IDLE, it is necessary to reset, because it is for EBT to occur if it resets during BURST transmission. NOTE: Reset has to be asserted at least 2 bus cycles long and after de-assertion the user has to wait at least 2 bus cycles before any read or write access.

1: Reset active -

0: Reset inactive -



FFCfg0

Description: The function of FIFO is set up.



Table 3-555: FFCfg0 Register



[2] FFTempMode0 RW 0x0 The mode of FIFO writing is chosen.

1: ON - Temporary latch feature mode is enable

0: OFF - Temporary latch feature mode is disable

[1] FFEmptyMode0 RW 0x0 This register specifies behavior when FIFO becomes empty. 0b=If FIFO becomes empty, FFEnO will be automatically set as 0. When the data of FIFO empties during the burst forwarding, AHB master keeps outputting the last data. FFEnO is automat-ically set as 0 after completing burst trans-mission. 1b=If a Trigger request comes when FIFO is empty, transmitting the last data is continued. When data is written in FIFO and Empty is cancelled if a request comes, transmission will be resumed auto-matically.

[0] FFEnO0 RW 0x0 Enable or disable the FIFO Output.

If the FIFO output is disabled, it waits to complete the present transmission. The next request is not received after comple-tion. If the FIFO is enabled and a trigger request is received the FIFO will start to output data. In the case of FFEmptyMode0=1 and the FIFO becomes empty, it will be automatically set to 0 (dis-abled). And when FIFO is empty, it cannot be set as 1.

1: FIFO output ON -

0: FIFO output OFF -



FFB0

Description: This address sets the boundary address of sharing FIFO. Do not overlap that each channelsboundary area setting. When the area overlaps, the operation guarantee cannot be done.When using this channel, it sets up so that it may be set to 'UpperBoundAdr >=LowerBoundAdr'. The maximum size for 'UpperBoundAdr - LowerBoundAdr' is 0x1FE.



Table 3-556: FFB0 Register



[24:16] UpperBoundAdr0 RW 0x0 Memory address for Upper Boundary of FIFO (Double Word Address)


[8:0] LowerBoundAdr0 RW 0x0 Memory address for Lower Boundary of FIFO (Double Word Address)



FFT0

Description: Sets the threshhold level for the corresponding FIFO in Bytes.


Instance no 0: 0x0002E10C

Table 3-557: FFT0 Register



[27:16] UpperThres0 RW 0x0 Sets the upper threshhold level in bytes. If the fill level becomes greater than this threshhold and a write occures from the corresponding FIFO a "Upper Threshhold Interrupt" is generated.


[11:0] LowerThres0 RW 0x0 Sets the lower threshhold level in bytes. If the fill level becomes lower than this threshhold and a read occures from the corresponding FIFO a "Lower Threshhold Interrupt" is generated.



DestAddress0

Description: Local AHB-master transfer Destination address



Table 3-558: DestAddress0 Register


[31:0] AHBMDA0 RW 0x0 Destination address to start AHB-master transfer. A value does not change during transmission.



AdrCfg0

Description: Address generation Configuration



Table 3-559: AdrCfg0 Register



[1] AdrMode10 RW 0x0 Address start

0: RESET - Destination address is reset with each trigger to AHBMDA0.

1: HOLD - Destination address is not reset (It continues from the last destination address), only with SWRESET.

[0] AdrMode00 RW 0x0 Address increment

0: INCR - Destination address is incre-mented (TransferWidth is byte=+1, hword=+2, word=+4).

1: FIXED - Destination address is fixed. A value does not change during transmission.



TransferCfg0

Description: Local AHB master transfer Configuration



Table 3-560: TransferCfg0 Register



[20] TransferINCR0 RW 0x0 0b = INCR transmission is disabled

Modes INCR (Indefinite length burst), INCR4, INCR8, INCR16 are not supported. All the transmission is set to SINGLE.

1b = INCR transmission is enabled

INCR(Indefinite length burst) and SINGLE, INCR4, INCR, INCR16 are supported.

When TransferNumber is 1 or AdrCfg0=1(Address is Fixed mode), o_mHBURST becomes SINGLE.

When TransferNumber is 4, o_mHBURST becomes INCR4.



As for other values, o_mHBURST becomes INCR.

When a transmission address exceeds 1KB, transmission is not carried out by INCR4, and 8 and 16. It transmits by INCR.


[17:16] TransferWidth0 RW 0x0 HSIZE set. A value does not change during transmission.

0x0: BYTE - Transferwidth is set to BYTE

0x1: HWORD - Transferwidth is set to HWORD

0x2: WORD - Transferwidth is set to WORD

0x3: RESERVED - RESERVED




[5:0] TransferNumber0 RW 0x0 Number of AHB-master Transfers for each Trigger beat. A value does not change dur-ing transmission.

TransferNumber = 00000000b -> 64 trans-fers.

TransferWidth = 00b(byte), TransferNum-ber = 00000001b -> 1 transfer by the byte size.

TransferWidth = 01b(hword), TransferNum-ber = 00000001b -> 1 transfer by the hword size.

TransferWidth = 10b(word), TransferNum-ber = 00000001b -> 1 transfer by the word size.

NOTE: In case the transmission contains "Meta Transfers" the two meta commands and subsequent data transfers have to be counted too! (E.g. : 4 Data Transfers + 2 Meta Commands + 6 Meta Data Transfers = TransferNumber0 = 12)





FFStatus0

Description: Status Register



Table 3-561: FFStatus0 Register



[27:16] FillLevel0 R 0x0 FIFO fill level.

[15:12] UBLV0 R 0x0 It can be checked which byte lane of Upper Temporary Latch Register has been updated. The byte lane which wrote in FFDataInL is set to 1. If all the bits of LBLV and UBLV are set to 1, it will write in FIFO. And this bit is cleared by 0. If this register becomes FIFO full, it will be cleared by 0.

[11:8] LBLV0 R 0x0 It can be checked which byte lane of Lower Temporary Latch Register has been updated. If all the bits of LBLV and UBLV are set to 1, it will write in FIFO. And this bit is cleared by 0. If this register becomes FIFO full, it will be cleared by 0.

[7] state0 R 0x0 The IDLE state of each channel is shown.

0: Idle -

1: Active -


[1] full0 R 0x0 Indicates if the FIFO is full or not.

0: Not Full -

1: Full -

[0] empty0 R 0x1 Indicates if the FIFO is empty or not.

0: Not Empty -

1: Empty -



FFISTS_TH0

Description: Interrupt status flags, a '1' signifies that the corresponding interrupt condition occurred (evenif interrupt is disabled), write '1' clears the flag. Even if the factor of Interrupt is cancelled (e.g.not empty), Or if an external clear signal is set to 1, this bit will be cleared automatically. Whenthe rising edge and StatusClear of an interrupt factor happen simultaneously, Status Registergives priority to an interrupt factor.



Table 3-562: FFISTS_TH0 Register



[8] IStsUT0 RW1C

0x0 Interrupt Status for condition: FIFO fill level over UpperThres. This bit will be cleared if "1" is written in this register or an i_UT_INT_clr[0] signal is set to "1"

0: No Interrupt -

1: Interrupt -


[0] IStsLT0 RW1C

0x0 Interrupt Status for condition: FIFO fill level below LowerThres. This bit will be cleared if "1" is written in this register or an i_LT_INT_clr[0] signal is set to "1"

0: No Interrupt -

1: Interrupt -



FFIEN_TH0

Description: Interrupt Enable register. '1' is enable.



Table 3-563: FFIEN_TH0 Register



[8] IEnUT0 RW 0x0 Interrupt enable. This bit controls the output of the Upper Threshold interrupt of channel 0 to o_UT_INT[0].

0: Disabled -

1: Enabled -


[0] IEnLT0 RW 0x0 Interrupt enable. This bit controls the output of the Lower Threshold interrupt of channel 0 to o_LT_INT[0].

0: Disabled -

1: Enabled -



FFIEN_DW0




Table 3-564: FFIEN_DW0 Register



[0] IEnDW0 RW 0x0 Interrupt enable This bit controls the output to o_DW_INT[0] in a IStsDW0 bit of the Status Register.

0: Disabled -

1: Enabled -



READ_CNT0

Description: 32 Bit Counter. Is incremented with every read from the FIFO. This does not correspond withthe size of the read (e.g. WORD, HALF WORD or BYTE). For each access regardless of sizethe counter is incremented by one. An overflow will occur at the boundary of 32 Bit.



Table 3-565: READ_CNT0 Register


[31:0] READ_CNT0 R 0x0 Counter for every read to the FIFO. The counter can be reset by writing "1" to Bit 1 of reset register "SWReset0".



WRITE_CNT0

Description: 32 Bit Counter. Is incremented with every write from the FIFO. This does not correspond withthe size of the write (e.g. WORD, HALF WORD or BYTE). For each access regardless of sizethe counter is incremented by one. An overflow will occur at the boundary of 32 Bit.



Table 3-566: WRITE_CNT0 Register


[31:0] WRITE_CNT0 R 0x0 Counter for every write from the FIFO. The counter can be reset by writing "1" to Bit 1 of reset register "SWReset0".



INT_READ_ADDR0

Description: Readback register for the read address pointer to the FIFO. NOTE: This is an internaladdress. It is derived from the lower bound address but translated internally (left shift by three'0'). The value is the next address that will be read from. For an example refer to the chapter'Readback address pointers'.



Table 3-567: INT_READ_ADDR0 Register



[11:0] INT_READ_PNT0 R 0x0 Read address pointer to the FIFO.



INT_WRITE_ADDR0

Description: Readback register for the current write address pointers to the FIFO. NOTE: These areinternal addresses. They are derived from the lower bound address but translated internally(left shift by three '0'). The value is the last address that has been written to. For an examplerefer to the chapter 'Readback address pointers'.



Table 3-568: INT_WRITE_ADDR0 Register



[27:16] INT_WRITE_PNT0_1 R 0x0 Write address pointer to the FIFO. This reg-ister is updated to the current value of write address pointer "INT_WRITE_PNT0_0" after the last write of the current transaction has happened. The last transaction is indi-cated by data written to register "FFDataInL0" and "FFDataInU0".


[11:0] INT_WRITE_PNT0_0 R 0x0 Current write address pointer to the FIFO.



FFEDataInL0

Description: Last FIFO Data In Lower



Table 3-569: FFEDataInL0 Register

Bit Position Bit Field Name

Type Reset Bit Description

[31:0] EDataInL0 W 0x0 Last Lower Data Input for FIFO channel 0.

In non double buffer mode data is only written to this register.

-FFTempEN=0 (temporary latch mode off)

If the temporary latch mode is turned off data written to this regis-ter will be stored and validated in the FIFO immediately. There-fore data written in this mode can be read out of the FIFO at once.

Input Size is Byte : 140h -> FIFO Write and Validate! -> 140h -> FIFO Write and Validate! -> ... (Databits 7-0 are used)

Input Size is HWORD: 140h -> FIFO Write and Validate! -> 140h -> FIFO Write and Validate! -> ... (Databits 15-0 are used)

Input Size is WORD : 140h -> FIFO Write and Validate! -> 140h -> FIFO Write and Validate! -> ... (Databits 31-0 are used)

-FFTempEN=1 (temporary latch mode on)

In temporary latch mode writing data to this register signals the end of a transmission. Data words written to registers DataInL0 and DataInU0 in the ongoing transmission will be validated after writing this registers and internal threshold and fill counters are updated.

Input Size is Byte : 148h -> 149h -> 14Ah -> ... 14Eh -> 14Fh -> FIFO Write! -> 148h -> 149h ... -> FIFO Write! -> ... -> 140h -> 141h -> 142h -> ... 146h -> 147h -> FIFO Write and Validate!

Input Size is HWORD: 148h -> 14Ah -> 14Ch -> 14Eh -> FIFO Write! -> 148h ... -> FIFO Write! -> ... -> 140h -> 142h -> 144h -> 146h ->FIFO Write and Validate!

Input Size is WORD : 148h -> 14Ch -> FIFO Write! -> 148h -> 14Ch -> FIFO Write! -> 148h ...... -> FIFO Write! -> ... -> 140h -> 144h ->FIFO Write and Validate!

Register "FFDataSize0" == 0

If the value in the register "FFDataSize0" equals 0 an acknowl-edge interrupt (Register: CFF_CTRL_STS Field: CFF_DW0_STS) will be asserted every time data is written to registers EDataInL0 or EDataInU0.

Register "FFDataSize0" > 0

If the value in the register "FFDataSize0" is greater 0 the internal logic will also compare if the bytes written to the FIFO match the number in this register. If they match an acknowledge interrupt (Register: CFF_CTRL_STS Field: CFF_DW0_STS) will be asserted. If no interrupt is observed after writing the last data word to this registers something went wrong during the transmis-sion (e.g. data lost).



FFEDataInU0

Description: Last FIFO Data In Upper



Table 3-570: FFEDataInU0 Register


[31:0] EDataInU0 W 0x0 -FFTempEN=0 (temporary latch mode off)

If the temporary latch mode is turned off this register has no function. A read deliv-ers always 0.


Writing to this register indicates that the transmission is complete and this is the last data word. All previous data words of a transmission have to be written to the regis-ters "FFDataInL0" and "FFDataInU0". Writ-ing to this registers will also update internal threshold and fill counters and mark the data as valid so it can be read from the FIFO. A read to this register delivers always 0.



FFDataInL0

Description: FIFO Data In Lower



Table 3-571: FFDataInL0 Register


[31:0] DataInL0 W 0x0 -FFTempEN=0 (temporary latch mode off)



Lower Data Input for FIFO channel 0. A read delivers always 0.

Only if 2 data words(8byte) are written to registers FFDataInL0 and FFDataInU0 the FIFO will be updated. Otherwise the inter-nal FIFO memory remains unchanged.

The last two words of a data transmission to the FIFO have to be written to registers EDataInL0 and EDataInU0. Only then the internal address pointers are updated and the data to the FIFO is validated. Prior to this it is not possible to read data from the FIFO.




Writing to FFDataInL is held in a Lower Temporary Latch register. The Temporary Latch register of Upper and Lower will be written into the FIFO if all the byte lanes (8bytes) are updated.

By reading the fields LBLV and UBLV of the FFStatus Register it can be checked which byte lane has been updated. However, the Temporary Latch Byte Lane Valid regis-ter(LBLV) is not updated when it writes into FFDataIn and the FIFO is full.



FFDataInU0

Description: FIFO Data In Upper



Table 3-572: FFDataInU0 Register


[31:0] DataInU0 W 0x0 -FFTempEN=0 (temporary latch mode off)



Upper Data Input for FIFO channel 0. A read delivers always 0.




FFDataSize0

Description: Number of bytes that will be written to the FIFO



Table 3-573: FFDataSize0 Register


[31:0] NumberOfBytes0 RW 0x0 Before a transmission the number of bytes will be written can be stored in this register. When writing the last data of a transmission to registers "FFEDataInL0" and "FFEDataInU0" this register will be com-pared with the actual data written to the FIFO. if they match an acknowledge inter-rupt will be asserted. If the value of the reg-ister is "0" no comparison will be done.



MetaDestAddress0

Description: Local AHB-master transfer Destination address for Meta Command operation. NOTEs: Thefirst and the last command to in a transmission sequence cannot be a meta command! TheMeta address register has to be always written prior to the Meta Config register! Fortransmissions sequences that contain meta command only indefinite length bursts can beconfigured (for both fields 'MetaTransferINCR' and 'TransferINCR')!



Table 3-574: MetaDestAddress0 Register


[31:0] MetaAHBMDA0 W 0x0 Destination address to start AHB-master transfer. A value does not change during transmission.



MetaCfg0

Description: Local AHB master transfer and address generation Configuration for Meta Commandoperation. NOTEs: The first and the last command to in a transmission sequence cannot bea meta command! The Meta address register has to be always written prior to the Meta Configregister! For transmissions sequences that contain meta command only indefinite lengthbursts can be configured (for both fields 'MetaTransferINCR' and 'TransferINCR')!



Table 3-575: MetaCfg0 Register



[20] MetaTransferINCR0 W 0x0 0b = INCR transmission is disabled











[17:16] MetaTransferWidth0 W 0x0 HSIZE set. A value does not change during transmission.








[1] MetaAdrMode10 W 0x0 Address start



[0] MetaAdrMode00 W 0x0 Write the lock or unlock key to this register field







SW_RT1












1: Reset active -

0: Reset inactive -



FFCfg1













1: FIFO output ON -




FFB1












FFT1












DestAddress1









AdrCfg1















TransferCfg1


























FFStatus1











0: Idle -

1: Active -



0: Not Full -

1: Full -


0: Not Empty -

1: Empty -



FFISTS_TH1



Instance no 0: 0x0002E1A0




[8] IStsUT1 RW1C


0: No Interrupt -

1: Interrupt -


[0] IStsLT1 RW1C


0: No Interrupt -

1: Interrupt -



FFIEN_TH1








0: Disabled -

1: Enabled -



0: Disabled -

1: Enabled -



FFIEN_DW1



Instance no 0: 0x0002E1AC





0: Disabled -

1: Enabled -



READ_CNT1



Instance no 0: 0x0002E1B0






WRITE_CNT1









INT_READ_ADDR1










INT_WRITE_ADDR1



Instance no 0: 0x0002E1BC




[27:16] INT_WRITE_PNT1_1 R 0x0 Write address pointer to the FIFO. This reg-ister is updated to the current value of write address pointer "INT_WRITE_PNT1_0" after the last write of the current transaction has happened. The last transaction is indi-cated by data written to register "FFDataInL1" and "FFDataInU1"





FFEDataInL1



Instance no 0: 0x0002E1C0








Input Size is Byte : 1C0h -> FIFO Write and Validate! -> 1C0h -> FIFO Write and Validate! -> ... (Databits 7-0 are used)

Input Size is HWORD: 1C0h -> FIFO Write and Validate! -> 1C0h -> FIFO Write and Validate! -> ... (Databits 15-0 are used)

Input Size is WORD : 1C0h -> FIFO Write and Validate! -> 1C0h -> FIFO Write and Validate! -> ... (Databits 31-0 are used)



Input Size is Byte : 1C8h -> 1C9h -> 1CAh -> ... 1CEh -> 1CFh -> FIFO Write! -> 1C8h -> 1C9h ... -> FIFO Write! -> ... -> 1C0h -> 1C1h -> 1C2h -> ... 1C6h -> 1C7h -> FIFO Write and Validate!

Input Size is HWORD: 1C8h -> 1CAh -> 1CCh -> 1CEh -> FIFO Write! -> 1C8h ... -> FIFO Write! -> ... -> 1C0h -> 1C2h -> 1C4h -> 1C6h ->FIFO Write and Validate!

Input Size is WORD : 1C8h -> 1CCh -> FIFO Write! -> 1C8h -> 1CCh -> FIFO Write! -> 1C8h ...... -> FIFO Write! -> ... -> 1C0h -> 1C4h ->FIFO Write and Validate!







FFEDataInU1












FFDataInL1



















FFDataInU1



Instance no 0: 0x0002E1CC










FFDataSize1



Instance no 0: 0x0002E1D0






MetaDestAddress1









MetaCfg1


























SW_RT2












1: Reset active -

0: Reset inactive -



FFCfg2













1: FIFO output ON -




FFB2












FFT2












DestAddress2









AdrCfg2















TransferCfg2


























FFStatus2











0: Idle -

1: Active -



0: Not Full -

1: Full -


0: Not Empty -

1: Empty -



FFISTS_TH2







[8] IStsUT2 RW1C


0: No Interrupt -

1: Interrupt -


[0] IStsLT2 RW1C


0: No Interrupt -

1: Interrupt -



FFIEN_TH2








0: Disabled -

1: Enabled -



0: Disabled -

1: Enabled -



FFIEN_DW2








0: Disabled -

1: Enabled -



READ_CNT2









WRITE_CNT2









INT_READ_ADDR2










INT_WRITE_ADDR2












FFEDataInL2

























FFEDataInU2












FFDataInL2



















FFDataInU2













FFDataSize2









MetaDestAddress2









MetaCfg2


























SW_RT3












1: Reset active -

0: Reset inactive -



FFCfg3













1: FIFO output ON -




FFB3












FFT3












DestAddress3









AdrCfg3















TransferCfg3


























FFStatus3











0: Idle -

1: Active -



0: Not Full -

1: Full -


0: Not Empty -

1: Empty -



FFISTS_TH3







[8] IStsUT3 RW1C


0: No Interrupt -

1: Interrupt -


[0] IStsLT3 RW1C


0: No Interrupt -

1: Interrupt -



FFIEN_TH3








0: Disabled -

1: Enabled -



0: Disabled -

1: Enabled -



FFIEN_DW3








0: Disabled -

1: Enabled -



READ_CNT3









WRITE_CNT3









INT_READ_ADDR3










INT_WRITE_ADDR3












FFEDataInL3

























FFEDataInU3












FFDataInL3



















FFDataInU3













FFDataSize3









MetaDestAddress3









MetaCfg3


























SW_RT4












1: Reset active -

0: Reset inactive -



FFCfg4













1: FIFO output ON -




FFB4












FFT4












DestAddress4









AdrCfg4















TransferCfg4


























FFStatus4











0: Idle -

1: Active -



0: Not Full -

1: Full -


0: Not Empty -

1: Empty -



FFISTS_TH4







[8] IStsUT4 RW1C


0: No Interrupt -

1: Interrupt -


[0] IStsLT4 RW1C


0: No Interrupt -

1: Interrupt -



FFIEN_TH4








0: Disabled -

1: Enabled -



0: Disabled -

1: Enabled -



FFIEN_DW4








0: Disabled -

1: Enabled -



READ_CNT4









WRITE_CNT4









INT_READ_ADDR4










INT_WRITE_ADDR4












FFEDataInL4

























FFEDataInU4












FFDataInL4



















FFDataInU4






[31:0] DataInU4 RW 0x0 -FFTempEN=0 (temporary latch mode off)







FFDataSize4






[31:0] NumberOfBytes4 W 0x0 Before a transmission the number of bytes will be written can be stored in this register. When writing the last data of a transmission to registers "FFEDataInL4" and "FFEDataInU4" this register will be com-pared with the actual data written to the FIFO. if they match an acknowledge inter-rupt will be asserted. If the value of the reg-ister is "0" no comparison will be done.



MetaDestAddress4









MetaCfg4


























SW_RT5












1: Reset active -

0: Reset inactive -



FFCfg5













1: FIFO output ON -




FFB5












FFT5












DestAddress5









AdrCfg5















TransferCfg5


























FFStatus5











0: Idle -

1: Active -



0: Not Full -

1: Full -


0: Not Empty -

1: Empty -



FFISTS_TH5







[8] IStsUT5 RW1C


0: No Interrupt -

1: Interrupt -


[0] IStsLT5 RW1C


0: No Interrupt -

1: Interrupt -



FFIEN_TH5








0: Disabled -

1: Enabled -



0: Disabled -

1: Enabled -



FFIEN_DW5








0: Disabled -

1: Enabled -



READ_CNT5









WRITE_CNT5









INT_READ_ADDR5










INT_WRITE_ADDR5












FFEDataInL5

























FFEDataInU5












FFDataInL5



















FFDataInU5













FFDataSize5









MetaDestAddress5









MetaCfg5


























SW_RT6












1: Reset active -

0: Reset inactive -



FFCfg6













1: FIFO output ON -




FFB6












FFT6












DestAddress6









AdrCfg6















TransferCfg6


























FFStatus6











0: Idle -

1: Active -



0: Not Full -

1: Full -


0: Not Empty -

1: Empty -



FFISTS_TH6







[8] IStsUT6 RW1C


0: No Interrupt -

1: Interrupt -


[0] IStsLT6 RW1C


0: No Interrupt -

1: Interrupt -



FFIEN_TH6








0: Disabled -

1: Enabled -



0: Disabled -

1: Enabled -



FFIEN_DW6








0: Disabled -

1: Enabled -



READ_CNT6









WRITE_CNT6









INT_READ_ADDR6










INT_WRITE_ADDR6












FFEDataInL6

























FFEDataInU6












FFDataInL6



















FFDataInU6













FFDataSize6









MetaDestAddress6









MetaCfg6


























SW_RT7












1: Reset active -

0: Reset inactive -



FFCfg7













1: FIFO output ON -




FFB7












FFT7












DestAddress7









AdrCfg7















TransferCfg7


























FFStatus7











0: Idle -

1: Active -



0: Not Full -

1: Full -


0: Not Empty -

1: Empty -



FFISTS_TH7







[8] IStsUT7 RW1C


0: No Interrupt -

1: Interrupt -


[0] IStsLT7 RW1C


0: No Interrupt -

1: Interrupt -



FFIEN_TH7








0: Disabled -

1: Enabled -



0: Disabled -

1: Enabled -



FFIEN_DW7








0: Disabled -

1: Enabled -



READ_CNT7









WRITE_CNT7









INT_READ_ADDR7










INT_WRITE_ADDR7







[27:16] INT_WRITE_PNT7_1 R 0x0 Write address pointer to the FIFO. This reg-ister is updated to the current value of write address pointer "INT_WRITE_PNT7_0" after the last write of the current transaction has happened. The last transaction is indi-cated by data written to register "FFDataInL7" and "FFDataInU7".





FFEDataInL7

























FFEDataInU7












FFDataInL7



















FFDataInU7













FFDataSize7









MetaDestAddress7









MetaCfg7



























3.9 Iris MVL Registers

In this section, the ‘Register Overview’ table summarizes all Iris MVL registers, including base addressof the module and name, description, and the absolute address of each register, which are thendescribed separately in the following tables.


3.9.1 Iris-MVL Register Overview

3.9.1.1 Iris-MVL - Global Control

3.9.1.2 Iris-MVL - Pixelbus






BASEADDR + 0x0008 IPIdentifier IP Identifier for this IRIS derivate, needs to be unlocked.

BASEADDR + 0x0010 InterruptEnable Interrupt Enable register

BASEADDR + 0x0014 InterruptPreset Interrupt Preset register

BASEADDR + 0x0018 InterruptClear Interrupt Clear register

BASEADDR + 0x001C InterruptStatus Interrupt Status register




BASEADDR + 0x0000 fetch0_cfg pixelbus configuration for unit fetch0

BASEADDR + 0x0004 fetch1_cfg pixelbus configuration for unit fetch1

BASEADDR + 0x0008 extsrc0_cfg pixelbus configuration for unit extsrc0

BASEADDR + 0x000C extdst0_cfg pixelbus configuration for unit extdst0

BASEADDR + 0x0010 extdst1_cfg pixelbus configuration for unit extdst1

BASEADDR + 0x0014 clut0_cfg pixelbus configuration for unit clut0

BASEADDR + 0x0018 layerblend0_cfg pixelbus configuration for unit layerblend0

BASEADDR + 0x001C layerblend1_cfg pixelbus configuration for unit layerblend1

BASEADDR + 0x0020 Request_Sequence_Complete Pixel Engine request sequence complete register

BASEADDR + 0x0024 Synchronization_Mode Pixel Engine synchronizer mode register

BASEADDR + 0x0028 Synchronization_Status Pixel Engine synchronizer status register

BASEADDR + 0x002C Synchronization_Trigger Pixel Engine synchronizer trigger register

BASEADDR + 0x0030 extdst0_clkextdst0 clock throttling, this value is used if the _clken of a module is configured for automatic mode

BASEADDR + 0x0034 extdst1_clkextdst1 clock throttling, this value is used if the _clken of a module is configured for automatic mode



3.9.1.3 Iris-MVL - Display Configuration

3.9.1.4 Iris-MVL - FetchRLD




BASEADDR + 0x0000 PolarityCtrl Modification of pixel output and its synchronization signals

BASEADDR + 0x0004 SigSrcSelect Select to observe data stream of submodules of display engine

BASEADDR + 0x0008 SigPanicColorPixel component, that will be displayed in case of signature violation and sig0_control.sig0_ObjectPanic = 0x0

BASEADDR + 0x000C ClockCtrl Controls generation of display clock signals.




BASEADDR + 0x0000 StaticControl Fetch unit static control register

BASEADDR + 0x0004 BurstBufferManagement AXI interface buffer management register

BASEADDR + 0x0008 BaseAddress Source buffer base address

BASEADDR + 0x000C SourceBufferStride Source buffer stride

BASEADDR + 0x0010 SourceBufferAttributes Source buffer attributes

BASEADDR + 0x0014 SourceBufferLength Source Buffer Length for Run Length Decoding

BASEADDR + 0x0018 FrameXOffset Frame X offset

BASEADDR + 0x001C FrameYOffset Frame Y offset

BASEADDR + 0x0020 FrameDimensions Defines frame rectangle

BASEADDR + 0x0024 DeltaXX DeltaXX stepsize

BASEADDR + 0x0028 DeltaYY DeltaYY stepsize

BASEADDR + 0x002C SkipWindowOffset Skip window offset

BASEADDR + 0x0030 SkipWindowDimensions

Defines skip window rectangle, set to (0,0) when SkipInvert is set to Normal to not skip any pixels at all (disable of skip window) or set to (0,0) when SkipInvert is set to Inverted to skip all pixels inside the sourcebuffer (useful to create a constant color background).

BASEADDR + 0x0034 ColorComponentBits Color component size of source buffer

BASEADDR + 0x0038 ColorComponentShift Color component offset of source buffer

BASEADDR + 0x003C ConstantColor

Constant color settings. These constant color values are required for tiling mode TILE_FILL_CONSTANT, skip mode CONSTANTCOLOR, fetchsprite background and if a color component bit width is set to 0.

BASEADDR + 0x0040 TransparentColor

Transparent color settings. These transparent color values are required for the transparent color feature. When the TransparentColorEnable is set to ENABLE then every pixel matching these transparent color components will get an alpha value of 0 and 255 otherwise. Please give each color component right aligned. Only the ColorComponentBits LSBs are evaluated, all others are ignored.

BASEADDR + 0x0044 Control Fetch unit main control register

BASEADDR + 0x0048 ControlTrigger Fetch unit trigger register

BASEADDR + 0x004C Start Fetch unit start register

BASEADDR + 0x0050 FetchType Fetch unit type register

BASEADDR + 0x0054 BurstBufferProperties Burst Buffer Property register




3.9.1.5 Iris-MVL - FetchSprite




BASEADDR + 0x0000 StaticControl Fetch unit static control register

BASEADDR + 0x0004 BitsPerPixel Sets bits per pixel for all sprite source buffers.

BASEADDR + 0x0008 ColorComponentBits Color component size of all source buffers of sprites

BASEADDR + 0x000C ColorComponentShift Color component offset of all source buffers of sprites

BASEADDR + 0x0010 Sprite00Address BaseAddress of Sprite0

BASEADDR + 0x0014 Sprite00Dimension Dimensions of Sprite0


BASEADDR + 0x001C Sprite01Dimension Dimensions of Sprite1





























BASEADDR + 0x0090 BurstBufferManagement AXI interface buffer management register

BASEADDR + 0x0094 SpriteEnable Enables for each sprite

BASEADDR + 0x0098 Sprite00Offset Offset of Sprite0 relative to output frame origin

BASEADDR + 0x009C Sprite01Offset Offset of Sprite1 relative to output frame origin

BASEADDR + 0x00A0 Sprite02Offset Offset of Sprite2 relative to output frame origin



BASEADDR + 0x00AC Sprite05Offset Offset of Sprite5 relative to output frame origin

BASEADDR + 0x00B0 Sprite06Offset Offset of Sprite6 relative to output frame origin



BASEADDR + 0x00BC Sprite09Offset Offset of Sprite9 relative to output frame origin

BASEADDR + 0x00C0 Sprite10Offset Offset of Sprite10 relative to output frame origin





BASEADDR + 0x00CC Sprite13Offset Offset of Sprite13 relative to output frame origin

BASEADDR + 0x00D0 Sprite14Offset Offset of Sprite14 relative to output frame origin

BASEADDR + 0x00D4 Sprite15Offset Offset of Sprite15 relative to output frame origin

BASEADDR + 0x00D8 FrameDimensions Defines frame rectangle

BASEADDR + 0x00DC ConstantColor

Constant color settings. These constant color values are required for tiling mode TILE_FILL_CONSTANT, skip mode CONSTANTCOLOR, fetchsprite background and if a color component bit width is set to 0.

BASEADDR + 0x00E0 TransparentColor


BASEADDR + 0x00E4 Control Fetch unit main control register

BASEADDR + 0x00E8 ControlTrigger Fetch unit trigger register

BASEADDR + 0x00EC Start Fetch unit start register

BASEADDR + 0x00F0 FetchType Fetch unit type register

BASEADDR + 0x00F4 BurstBufferProperties Burst Buffer Property register

BASEADDR + 0x00F8 Reserved Do not modify






3.9.1.6 Iris-MVL - ExtSrc

3.9.1.7 Iris-MVL - CLuT




BASEADDR + 0x0000 StaticControl ExtSrc static control register

BASEADDR + 0x0004 ClipWindowOffsetClip window offset, to generate a clipping of the frame. It has to be within the input frame.

BASEADDR + 0x0008 ClipWindowDimension

Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimen-sion. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame.

BASEADDR + 0x000C ColorComponentBitsColor component size of raw input data. Please note that the width must be equal or lower than the output width.

BASEADDR + 0x0010 ColorComponentShift Color component offset of raw input data.

BASEADDR + 0x0014 ConstantColorRedGreenConstant color settings for Red and Green channel. These constant color values are required if a color component bit width is set to 0.

BASEADDR + 0x0018 ConstantColorBlueAlphaConstant color settings for Blue and Alpha channel. These constant color values are required if a color component bit width is set to 0.

BASEADDR + 0x001C TransparentColor


BASEADDR + 0x0020 Control ExtSrc unit main control register

BASEADDR + 0x0024 ControlTrigger ExtSrc unit trigger token generation

BASEADDR + 0x0028 Start ExtSrc unit start register




Base Address(es)Instance no 0: BASEADDR0="00032000"Instance no 1: BASEADDR1="00033C00"


BASEADDRx + 0x0000 StaticControl CLUT static control register

BASEADDRx + 0x0004 UnshadowedControl CLUT unshadowed control register

BASEADDRx + 0x0008 Control CLUT control register

BASEADDRx + 0x000C Status CLUT status register

BASEADDRx + 0x0010 LastControlWord Value of last received control word, for debugging

BASEADDRx + 0x0400 LUT Look Up Table



3.9.1.8 Iris-MVL - Matrix

3.9.1.9 Iris-MVL - LayerBlend

3.9.1.10 Iris-MVL - ExtDst




BASEADDR + 0x0000 StaticControl Color Matrix static control register

BASEADDR + 0x0004 Control Color Matrix control register

BASEADDR + 0x0008 Red0 Matrix values for calculation of the red output value

BASEADDR + 0x000C Red1 Matrix values for calculation of the red output value

BASEADDR + 0x0010 Green0 Matrix values for calculation of the green output value

BASEADDR + 0x0014 Green1 Matrix values for calculation of the green output value

BASEADDR + 0x0018 Blue0 Matrix values for calculation of the blue output value

BASEADDR + 0x001C Blue1 Matrix values for calculation of the blue output value

BASEADDR + 0x0020 LastControlWord Value of last received control word, for debugging




BASEADDRx + 0x0000 StaticControl Layer Blend static control register

BASEADDRx + 0x0004 Control Layer Blend control register

BASEADDRx + 0x0008 Position Position of secondary (overlay) input frame

BASEADDRx + 0x000C PrimControlWordValue of last received primary (background) control word, for debugging

BASEADDRx + 0x0010 SecControlWordValue of last received secondary (overlay) control word, for debugging




BASEADDRx + 0x0000 StaticControl External Destination output control

BASEADDRx + 0x0004 SoftwareKick External Destination software kick

BASEADDRx + 0x0008 Status External Destination Unit current status

BASEADDRx + 0x000C ControlWord Value of last received control word

BASEADDRx + 0x0010 CurPixelCnt pixel count of currently running frame

BASEADDRx + 0x0014 LastPixelCnt pixel count between last two control words

BASEADDRx + 0x0018 PerfCounter Performance counter result



3.9.1.11 FrameCap

3.9.1.12 Iris-MVL - FrameGen_PS




BASEADDR + 0x0000 Ctr FrameCap Control Register

BASEADDR + 0x0004 Spr FrameCap Sync Polarity Register

BASEADDR + 0x0008 Fdr FrameCap Frame Dimension Register

BASEADDR + 0x000C Kcr FrameCap Kick Config Register

BASEADDR + 0x0010 Scr FrameCap Sync Config Register

BASEADDR + 0x0014 StsFrameCap Status Register. Shows current status of the Fra-meCap module.

BASEADDR + 0x0018 StsClrFrameCap Status Clear Register. Clears the locked status bits in Sts register.

BASEADDR + 0x001C FRCnt FrameCap Frame Rate Count Register.






BASEADDR + 0x0008 FgStCtrl FrameGen Static Control Register

BASEADDR + 0x000C HtCfg1 FrameGen Horizontal Timing Config Register 1

BASEADDR + 0x0010 HtCfg2 FrameGen Horizontal Timing Config Register 2

BASEADDR + 0x0014 VtCfg1 FrameGen Vertical Timing Config Register 1

BASEADDR + 0x0018 VtCfg2 FrameGen Vertical Timing Config Register 2

BASEADDR + 0x001C Int0ConfigCoordinates of the trigger point for generation of the Int0 interrupt signal

BASEADDR + 0x0020 Int1ConfigCoordinates of the trigger point for generation of the Int1 interrupt signal



BASEADDR + 0x002C PKickConfigCoordinates of the trigger point for generation of the primary kick signal

BASEADDR + 0x0030 SKickConfigCoordinates of the trigger point for generation of the sec-ondary kick signal

BASEADDR + 0x0034 SecStatConfigConfiguration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register.

BASEADDR + 0x0038 FgSRCR1 FrameGen Skew Regulation Control Register 1.

BASEADDR + 0x003C FgSRCR2 FrameGen Skew Regulation Control Register 2

BASEADDR + 0x0040 FgSRCR3 FrameGen Skew Regulation Control Register 3



BASEADDR + 0x004C FgSRCR6 FrameGen Skew Regulation Control Register 6

BASEADDR + 0x0050 FgKSDR FrameGen Kick System Debug Register

BASEADDR + 0x0054 PaCfg FrameGen Primary Area Config Register 1 (shadowed)

BASEADDR + 0x0058 SaCfg FrameGen Secondary Area Config Register 1 (shadowed)



BASEADDR + 0x005C FgInCtrl FrameGen Input Control Register (shadowed)

BASEADDR + 0x0060 FgInCtrlPanic Ï FrameGen Input Control Panic Register (shadowed)

BASEADDR + 0x0064 FgCCR FrameGen Constant Color Register (shadowed)

BASEADDR + 0x0068 FgEnable FrameGen Enable Register

BASEADDR + 0x006C FgSlr FrameGen Shadow Load Register

BASEADDR + 0x0070 FgEnSts FrameGen Enable Status Register

BASEADDR + 0x0074 FgChStat FrameGen Channel Status Register

BASEADDR + 0x0078 FgChStatClr FrameGen Channel Status Clear Register

BASEADDR + 0x007C FgSkewMonFrameGen Skew Monitor Register for Secondary Channel Skew Control

BASEADDR + 0x0080 FgSFifoMin FrameGen Secondary FIFO Min Fill Register

BASEADDR + 0x0084 FgSFifoMax FrameGen Secondary FIFO Max Fill Register

BASEADDR + 0x0088 FgSFifoFillClr FrameGen Secondary FIFO Fill Clear Register

BASEADDR + 0x008C FgSrEpD FrameGen Skew Regulation ExtraPolation Debug Register

BASEADDR + 0x0090 FgSrFtD FrameGen Skew Regulation Frame Total Debug Register






3.9.1.13 Iris-MVL - Dither

3.9.1.14 Iris-MVL - TCon




BASEADDR + 0x0000 Control Dither Unit common control.

BASEADDR + 0x0004 DitherControl Dither Unit processing control.

BASEADDR + 0x0008 Release Dither Unit release.




BASEADDR + 0x0000 SSqCntsThe 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field

BASEADDR + 0x0400 SSqCycleThis bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles

BASEADDR + 0x0404 SWresetTCON Software Reset - Reset all tcon registers except con-figuration registers. Detailed description in specification document

BASEADDR + 0x0408 TCON_CTRL TCON Control register

BASEADDR + 0x040C RSDSInvCtrlControls inversion of output polarity when connected IO cells operate in RSDS mode

BASEADDR + 0x0410 MapBit3_0 Mapping of 24 bit RGB or Timing Generator TSig[5:0] to bit 0 .. 3



BASEADDR + 0x041C MapBit15_12 Mapping of 24 bit RGB or Timing Generator TSig[5:0] to bit 12 .. 15




BASEADDR + 0x042C MapBit3_0_Dual Same as MapBit3_0 for 2nd channel

BASEADDR + 0x0430 MapBit7_4_Dual Same as MapBit7_4 for 2nd channel



BASEADDR + 0x043C MapBit19_16_Dual Same as MapBit19_16 for 2nd channel



BASEADDR + 0x0448 SPG0PosOn Sync pulse generator 0, 'Switch on' position

BASEADDR + 0x044C SPG0MaskOnThe Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0

BASEADDR + 0x0450 SPG0PosOff Sync pulse generator 0, 'Switch off' position

BASEADDR + 0x0454 SPG0MaskOffThe Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0





















BASEADDR + 0x04A0 SPG5PosOff Sync pulse generator 5, 'Switch off' position

BASEADDR + 0x04A4 SPG5MaskOffThe Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5

BASEADDR + 0x04A8 SPG6PosOn Sync pulse generator 6, 'Switch on' position

BASEADDR + 0x04AC SPG6MaskOnThe Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6

BASEADDR + 0x04B0 SPG6PosOff Sync pulse generator 6, 'Switch off' position

BASEADDR + 0x04B4 SPG6MaskOffThe Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6

BASEADDR + 0x04B8 SPG7PosOn Sync pulse generator 7, 'Switch on' position

BASEADDR + 0x04BC SPG7MaskOnThe Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7

BASEADDR + 0x04C0 SPG7PosOff Sync pulse generator 7, 'Switch off' position

BASEADDR + 0x04C4 SPG7MaskOffThe Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7

BASEADDR + 0x04C8 SPG8PosOn Sync pulse generator 8, 'Switch on' position

BASEADDR + 0x04CC SPG8MaskOnThe Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8

BASEADDR + 0x04D0 SPG8PosOff Sync pulse generator 8, 'Switch off' position

BASEADDR + 0x04D4 SPG8MaskOffThe Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8

BASEADDR + 0x04D8 SPG9PosOn Sync pulse generator 9, 'Switch on' position

BASEADDR + 0x04DC SPG9MaskOnThe Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9

BASEADDR + 0x04E0 SPG9PosOff Sync pulse generator 9, 'Switch off' position

BASEADDR + 0x04E4 SPG9MaskOffThe Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9






BASEADDR + 0x04E8 SPG10PosOn Sync pulse generator 10, 'Switch on' position

BASEADDR + 0x04EC SPG10MaskOnThe Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10

BASEADDR + 0x04F0 SPG10PosOff Sync pulse generator 10, 'Switch off' position

BASEADDR + 0x04F4 SPG10MaskOffThe Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10

BASEADDR + 0x04F8 SPG11PosOn Sync pulse generator 11, 'Switch on' position

BASEADDR + 0x04FC SPG11MaskOnThe Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11



BASEADDR + 0x0508 SMx0Sigs Selection of input signals of sync mixer

BASEADDR + 0x050C SMx0FctTableThe sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection


BASEADDR + 0x0514 SMx1FctTableThe sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection


BASEADDR + 0x051C SMx2FctTableThe sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection





















3.9.1.15 Iris-MVL - Sig







Base Address(es)

Instance no 0: BASEADDR0="00035000"Instance no 1: BASEADDR1="00035400"Instance no 2: BASEADDR2="00035800"Instance no 3: BASEADDR3="00035C00"


BASEADDRx + 0x0000 SigLockUnlockRegister to lock or unlock write access to registers of this unit with lock property

BASEADDRx + 0x0004 SigLockStatusLock Status for write access to registers of this unit with lock property

BASEADDRx + 0x0008 SigEnable Ï Turn on and stop the signature unit.

BASEADDRx + 0x000C StaticControl Ï Signature configuration and Static control register

BASEADDRx + 0x0010 ThrSumRed Ï Threshold on Red channel for Summation Signature

BASEADDRx + 0x0014 ThrSumGreen Ï Threshold on Green channel for Summation Signature

BASEADDRx + 0x0018 ThrSumBlue Ï Threshold on Blue channel for Summation Signature

BASEADDRx + 0x001C ErrorThreshold Ï Number of tolerated signature violation before activating interrupt and setting Status

BASEADDRx + 0x0020 EvalUpperLeft Ï UpperLeft coordinate of Evaluation Window

BASEADDRx + 0x0024 EvalLowerRight Ï LowerRight coordinate of Evaluation Window

BASEADDRx + 0x0028 SkipUpperLeft Ï UpperLeft coordinate of Skip Window

BASEADDRx + 0x002C SkipLowerRight Ï LowerRight coordinate of Skip Window

BASEADDRx + 0x0030 SigCRCRefRed Ï Reference Signature of Type CRC on channel Red

BASEADDRx + 0x0034 SigCRCRefGreen Ï Reference Signature of Type CRC on channel Green

BASEADDRx + 0x0038 SigCRCRefBlue Ï Reference Signature of Type CRC on channel Blue

BASEADDRx + 0x003C SigSumRefRed ÏReference Signature of Type Summation (color summation) on channel Red

BASEADDRx + 0x0040 SigSumRefGreen ÏReference Signature of Type Summation (color summation) on channel Green

BASEADDRx + 0x0044 SigSumRefBlue ÏReference Signature of Type Summation (color summation) on channel Blue

BASEADDRx + 0x0048 Load_Shadow Ï trigger to load from shadowed registers

BASEADDRx + 0x004C SoftwareKick Ï Kick to start signature generation

BASEADDRx + 0x0050 PanicFlag Ï

Monitor the signature violation. Once this Flag is set, it remains 1'active until it's written with '1'. Pls note, the setting of PanicFlag depends on ErrorThreshold and StaticCon-trol.EnPanic = ENABLE

BASEADDRx + 0x0054 Status Ï Signature Status (update after every signature generation)

BASEADDRx + 0x0058 SigErrCount Ï Number of frames with signature errors






BASEADDRx + 0x005C SigCRCRed ÏResult of CRC Signature for channel Red (update after every signature generation)

BASEADDRx + 0x0060 SigCRCGreen ÏResult of CRC Signature for channel Green (update after every signature generation)

BASEADDRx + 0x0064 SigCRCBlue ÏResult of CRC Signature for channel Blue (update after every signature generation)

BASEADDRx + 0x0068 SigSumRed ÏResult of Summation Signature for channel Red (update after every signature generation)

BASEADDRx + 0x006C SigSumGreen ÏResult of Summation Signature for channel Green (update after every signature generation)

BASEADDRx + 0x0070 SigSumBlue ÏResult of Summation Signature for channel Blue (update after every signature generation)


Base Address(es)

Instance no 0: BASEADDR0="00035000"Instance no 1: BASEADDR1="00035400"Instance no 2: BASEADDR2="00035800"Instance no 3: BASEADDR3="00035C00"




Iris-MVL - Global Control

LockUnlock






[31:0] LockUnlock W 0x0 Write lock or unlock key to this field in order to change lock status.




LockStatus








0: Unlocked -

1: Locked -



IPIdentifier

Description: IP Identifier for this IRIS derivate, needs to be unlocked.



Table 3-747: IPIdentifier Register


[31:28] IPFamily RW 0x1 IP family

1: Iris -

[27:24] IPConfiguration RW 0x1 Ip configuration

1: Module - Iris-M*

2: System - Iris-S*

[23:20] IPApplication RW 0x3 IP application

1: Blit - Iris-?B*

2: BlitDisplay - Iris-?D*

3: BlitDisplayVideo - Iris-?V*

4: BlitDisplayVideoDrawing - Iris-?G*

[19:16] IPFeatureSet RW 0x2 IP feature set (complexity of implemented features, e.g. availability of re-sampling fil-ter etc)

1: ECO - Iris-??E

2: LIGHT - Iris-??L

3: STANDARD - Iris-??

4: PLUS - Iris-??P

5: EXTENSIVE - Iris-??X

[15:12] IPEvolution RW 0x1 IP evolution (increased for functional spec changes only when feature set keeps the same)

[11:8] DesignMaturityLevel RW 0x4 Design maturity level (corresponds to sta-tus at time of IP delivery, Fujitsu internal development stages)

1: PreFS - Pre feasibility study

2: FS - Feasibility study

3: R0 - Functionality complete

4: R1 - Verification complete

[7:4] DesignDeliveryID RW 0x2 Design delivery ID (increased with each official delivery when maturity keeps the same, e.g. bugfixes)

[3:0] Reserved RW 0x0 Reserved bits



InterruptEnable

Description: Interrupt Enable register



Table 3-748: InterruptEnable Register



[25:0] InterruptEnable RW 0x0 Enable for interrupts. Interrupt n is mapped to InterruptEnable[n] (1=enable, 0=dis-able).



InterruptPreset

Description: Interrupt Preset register



Table 3-749: InterruptPreset Register



[25:0] InterruptPreset R0W1

X Preset for interrupts. Interrupt n is mapped to InterruptPreset[n] (write 1 to bit [n] to set interrupt n).



InterruptClear

Description: Interrupt Clear register



Table 3-750: InterruptClear Register



[25:0] InterruptClear R0W1

X Clear for interrupts. Interrupt n is mapped to InterruptClear[n] (write 1 to bit [n] to clear interrupt n).



InterruptStatus

Description: Interrupt Status register



Table 3-751: InterruptStatus Register



[25:0] InterruptStatus R X Status of interrupts. Interrupt n is mapped to InterruptStatus[n] (1=set, 0=not set).



Iris MVL - Pixelbus

fetch0_cfg

Description: pixelbus configuration for unit fetch0



Table 3-752: fetch0_cfg Register



[28:27] fetch0_sel R X status of the connection of the fetch0 mod-ule

1: extdst0 - fetch0 module is used from extdst0 processing path


0: disable - fetch0 module is not used

[26] fetch0_shdw RW 0x0 control for shadow reload flag generation of fetch0 module

0x0: WRITETHROUGH - Register will not be shadowed

0x1: SHADOWED - Register will be shad-owed




fetch1_cfg

Description: pixelbus configuration for unit fetch1



Table 3-753: fetch1_cfg Register



[28:27] fetch1_sel R X status of the connection of the fetch1 mod-ule



0: disable - fetch1 module is not used

[26] fetch1_shdw RW 0x0 control for shadow reload flag generation of fetch1 module






extsrc0_cfg

Description: pixelbus configuration for unit extsrc0



Table 3-754: extsrc0_cfg Register



[28:27] extsrc0_sel R X status of the connection of the extsrc0 module

1: extdst0 - extsrc0 module is used from extdst0 processing path

2: extdst1 - extsrc0 module is used from extdst1 processing path

0: disable - extsrc0 module is not used

[26] extsrc0_shdw RW 0x0 control for shadow reload flag generation of extsrc0 module






extdst0_cfg

Description: pixelbus configuration for unit extdst0



Table 3-755: extdst0_cfg Register



[28:27] extdst0_sel R X status of the connection of the extdst0 module

1: extdst0 - extdst0 module is used from extdst0 processing path


0: disable - extdst0 module is not used

[26] extdst0_shdw RW 0x0 shadow control for this ( = extdst0_cfg ) register




[3:0] extdst0_src_sel RWS 0x0 Selection of the source for the src input of the extdst0 module

0: disable - Unit extdst0 input port src is disabled

1: fetch0 - Unit extdst0 input port src is con-nected to output of unit fetch0

8: layerblend1 - Unit extdst0 input port src is connected to output of unit layerblend1

6: clut0 - Unit extdst0 input port src is con-nected to output of unit clut0



extdst1_cfg

Description: pixelbus configuration for unit extdst1



Table 3-756: extdst1_cfg Register



[28:27] extdst1_sel R X status of the connection of the extdst1 module



0: disable - extdst1 module is not used

[26] extdst1_shdw RW 0x0 shadow control for this ( = extdst1_cfg ) register




[3:0] extdst1_src_sel RWS 0x0 Selection of the source for the src input of the extdst1 module

0: disable - Unit extdst1 input port src is disabled





clut0_cfg

Description: pixelbus configuration for unit clut0



Table 3-757: clut0_cfg Register



[28:27] clut0_sel R X status of the connection of the clut0 module

1: extdst0 - clut0 module is used from extdst0 processing path

2: extdst1 - clut0 module is used from extdst1 processing path

0: disable - clut0 module is not used

[26] clut0_shdw RW 0x0 shadow control for this ( = clut0_cfg ) regis-ter




[3:0] clut0_src_sel RWS 0x0 Selection of the source for the src input of the clut0 module

0: disable - Unit clut0 input port src is dis-abled

1: fetch0 - Unit clut0 input port src is con-nected to output of unit fetch0

2: fetch1 - Unit clut0 input port src is con-nected to output of unit fetch1



layerblend0_cfg

Description: pixelbus configuration for unit layerblend0



Table 3-758: layerblend0_cfg Register



[28:27] layerblend0_sel R X status of the connection of the layerblend0 module

1: extdst0 - layerblend0 module is used from extdst0 processing path


0: disable - layerblend0 module is not used

[26] layerblend0_shdw RW 0x0 shadow control for this ( = layerblend0_cfg ) register



[25:24] layerblend0_clken RWS 0x1 Enable of layerblend0 clock (this setting has to be the same for all modules of one processing pipeline). If a submodule is enabled and FULL is used, then the regis-ter [endpoint_name]_clk must be set to 0x80.

0: DISABLE - Clock for layerblend0 is dis-abled

1: AUTOMATIC - Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_clk register)

3: FULL - Clock for layerblend0 is without gating


[11:8] layerblend0_sec_sel RWS 0x0 Selection of the source for the sec input of the layerblend0 module

0: disable - Unit layerblend0 input port sec is disabled

1: fetch0 - Unit layerblend0 input port sec is connected to output of unit fetch0

6: clut0 - Unit layerblend0 input port sec is connected to output of unit clut0




[3:0] layerblend0_prim_sel RWS 0x0 Selection of the source for the prim input of the layerblend0 module

0: disable - Unit layerblend0 input port prim is disabled

3: extsrc0 - Unit layerblend0 input port prim is connected to output of unit extsrc0





layerblend1_cfg

Description: pixelbus configuration for unit layerblend1






[28:27] layerblend1_sel R X status of the connection of the layerblend1 module



0: disable - layerblend1 module is not used

[26] layerblend1_shdw RW 0x0 shadow control for this ( = layerblend1_cfg ) register



[25:24] layerblend1_clken RWS 0x1 Enable of layerblend1 clock (this setting has to be the same for all modules of one processing pipeline). If a submodule is enabled and FULL is used, then the regis-ter [endpoint_name]_clk must be set to 0x80.

0: DISABLE - Clock for layerblend1 is dis-abled

1: AUTOMATIC - Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_clk register)

3: FULL - Clock for layerblend1 is without gating


[11:8] layerblend1_sec_sel RWS 0x0 Selection of the source for the sec input of the layerblend1 module

0: disable - Unit layerblend1 input port sec is disabled

2: fetch1 - Unit layerblend1 input port sec is connected to output of unit fetch1

6: clut0 - Unit layerblend1 input port sec is connected to output of unit clut0




[3:0] layerblend1_prim_sel RWS 0x0 Selection of the source for the prim input of the layerblend1 module

0: disable - Unit layerblend1 input port prim is disabled

1: fetch0 - Unit layerblend1 input port prim is connected to output of unit fetch0

6: clut0 - Unit layerblend1 input port prim is connected to output of unit clut0

7: layerblend0 - Unit layerblend1 input port prim is connected to output of unit layerblend0





Request_Sequence_Complete

Description: Pixel Engine request sequence complete register



Table 3-760: Request_Sequence_Complete Register



[4] extdst1_trigger_sequence_complete

R0W1

X By writing a '1' to this register field, you can trigger the extdst1 sequence complete interrupt that will occur as soon as the pipe-line with the endpoint extdst1 is empty. This interrupt will also occur if the pipeline is already empty when this field is written. The interrupt will not occur when if this field is not written. The interrupt will occur exactly as often as this field is written, assuming that this field is not written again until the interrupt has occured after a previ-ous trigger.


[0] extdst0_trigger_sequence_complete

R0W1

X By writing a '1' to this register field, you can trigger the extdst0 sequence complete interrupt that will occur as soon as the pipe-line with the endpoint extdst0 is empty. This interrupt will also occur if the pipeline is already empty when this field is written. The interrupt will not occur when if this field is not written. The interrupt will occur exactly as often as this field is written, assuming that this field is not written again until the interrupt has occured after a previ-ous trigger.



Synchronization_Mode

Description: Pixel Engine synchronizer mode register



Table 3-761: Synchronization_Mode Register





[5:4] extdst1_Sync_Mode RW 0x0 Synchronization mode for extdst1 pipeline endpoint synchronizer

0x0: SINGLE - Reconfig own pipeline only

0x1: LOW_PRIO_SYNC - Empty pipeline before starting emptying SYNC mode pipe-lines, reconfig when they are empty too

0x2: SYNC - Reconfig when other SYNC pipelines are also empty

0x3: RESERVED - Reserved, don't use



[1:0] extdst0_Sync_Mode RW 0x0 Synchronization mode for extdst0 pipeline endpoint synchronizer

0x0: SINGLE - Reconfig own pipeline only

0x1: LOW_PRIO_SYNC - Empty pipeline before starting emptying SYNC mode pipe-lines, reconfig when they are empty too

0x2: SYNC - Reconfig when other SYNC pipelines are also empty

0x3: RESERVED - Reserved, don't use



Synchronization_Status

Description: Pixel Engine synchronizer status register



Table 3-762: Synchronization_Status Register



[7:6] extdst1_pipeline_status R 0x0 Status of pipeline with endpoint extdst1

0x0: EMPTY - Pipeline with endpoint extdst1 is empty

0x1: RUNNING - Pipeline with endpoint extdst1 is currently processing one opera-tion

0x2: RUNNING_RETRIGGERED - Pipe-line with endpoint extdst1 is currently pro-cessing one operation with a second one already kicked to be processed afterwards

0x3: RESERVED - reserved


[4] extdst1_Sync_busy R 0x0 Synchronization busy status of extdst1 endpoint

0x0: IDLE - extdst1 synchronizer is idle

0x1: BUSY - extdst1 synchronizer is busy

[3:2] extdst0_pipeline_status R 0x0 Status of pipeline with endpoint extdst0

0x0: EMPTY - Pipeline with endpoint extdst0 is empty

0x1: RUNNING - Pipeline with endpoint extdst0 is currently processing one opera-tion

0x2: RUNNING_RETRIGGERED - Pipe-line with endpoint extdst0 is currently pro-cessing one operation with a second one already kicked to be processed afterwards

0x3: RESERVED - reserved


[0] extdst0_Sync_busy R 0x0 Synchronization busy status of extdst0 endpoint

0x0: IDLE - extdst0 synchronizer is idle

0x1: BUSY - extdst0 synchronizer is busy



Synchronization_Trigger

Description: Pixel Engine synchronizer trigger register



Table 3-763: Synchronization_Trigger Register



[4] extdst1_Sync_Trigger R0W1

X Writing a '1' to this field triggers reconfigu-ration of the pipeline with endpoint extdst1


[0] extdst0_Sync_Trigger R0W1

X Writing a '1' to this field triggers reconfigu-ration of the pipeline with endpoint extdst0



extdst0_clk

Description: extdst0 clock throttling, this value is used if the _clken of a module is configured for automaticmode



Table 3-764: extdst0_clk Register



[7:0] extdst0_div RW 0x80 extdst0 clock dividing factor (ratio is register_value/128, values above 128 are reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets the clock at full speed.



extdst1_clk

Description: extdst1 clock throttling, this value is used if the _clken of a module is configured for automaticmode



Table 3-765: extdst1_clk Register



[7:0] extdst1_div RW 0x80 extdst1 clock dividing factor (ratio is register_value/128, values above 128 are reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets the clock at full speed.



Iris-MVL - Display Configuration Registers

PolarityCtrl

Description: Modification of pixel output and its synchronization signals



Table 3-766: PolarityCtrl Register



[3] PixInv RW 0x0 Inversion of pixel output.

0x0: NonInv - NON inversion of pixel data.

0x1: Inv - pixel data inverted (1. comple-ment).

[2] PolEn RW 0x1 Polarity of Data_Enable signal at Display Engine output. For dual channel operation set PolEn to HIGH.

0x0: LOW - Low active.

0x1: HIGH - High active.

[1] PolVs RW 0x1 Polarity of vsync signal at Display Engine output. In TCON H_VSync mode the sync polarity must be set to LOW.



[0] PolHs RW 0x1 Polarity of hsync signal at Display Engine output. In TCON H_VSync mode the sync polarity must be set to LOW.





SigSrcSelect

Description: Select to observe data stream of submodules of display engine



Table 3-767: SigSrcSelect Register



[1:0] src_select RW 0x0 Select source pixels to signature

0x0: FRAMEGEN - Output pixel stream of Frame Generator will be observed by sig-nature unit

0x1: MATRIX - Output pixel stream of MATRIX will be observed by signature unit

0x2: CLUT - Output pixel stream of CLUT will be observed by signature unit

0x3: DITHER - Output pixel stream of DITHERING will be observed by signature unit



SigPanicColor

Description: Pixel component, that will be displayed in case of signature violation andsig0_control.sig0_ObjectPanic = 0x0



Table 3-768: SigPanicColor Register



[23:16] PanicRed RW 0x0 Red component of pixel data, that will be blended to pixel data stream in case of sig-nature violation

[15:8] PanicGreen RW 0x0 Green component of pixel data, that will be blended to pixel data stream in case of sig-nature violation

[7:0] PanicBlue RW 0x0 Blue component of pixel data, that will be blended to pixel data stream in case of sig-nature violation



ClockCtrl

Description: Controls generation of display clock signals.



Table 3-769: ClockCtrl Register



[0] DspClkDivide RW 0x1 Controls generation of display clock sig-nals.

0x0: DIV1 - External display clock signal has pixel clock frequency.

0x1: DIV2 - External display clock signal has twice the pixel clock frequency.



Iris-MVL - FetchRLD Registers

StaticControl

Description: Fetch unit static control register



Table 3-770: StaticControl Register



[9] ToggleField RW 0x0 Enable toggling of the field property from frame to frame.

1: Enable -

0: Disable -

[8] SetField RW 0x0 The field property of the generated frame is set to this value. If field toggle is used, this is the start value.


[5] ClockDisable RW 0x1 Deactivates most internal clocks of fetch unit. Can only be activated if SWReset field is set to SW_RESET.

0x0: OPERATION - Normal Operation

0x1: POWERDOWN - Clocks are off

[4] SWReset RW 0x1 Puts the fetch unit in software reset. This software reset will not affect the shadow registers.


0x1: SW_RESET - Software Reset


[0] ShdEn RW 0x0 Enables shadowing of all RWS type regis-ters (0=write_through, 1=shadowed).



BurstBufferManagement

Description: AXI interface buffer management register



Table 3-771: BurstBufferManagement Register



[12:8] SetBurstLength RWS 0x4 Set this to the burst length that should be used on the AXI interface. Please note that SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length.

[7:0] SetNumBuffers RWS 0x4 Set this to the number of bursts that should be buffered. Please note that SetNumBuf-fers has to be smaller or equal to Managed-BurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthFor-MaxBuffers. Must be a power of 2. The minimum allowed settings for fetch deri-vates ROT and WARP is 4, and the mini-mum allowed setting for the others is 2. But please note, that for 24 bit per pixel opera-tions the minimum recommended setting is always 4, otherwise performance will suffer.



BaseAddress

Description: Source buffer base address



Table 3-772: BaseAddress Register


[31:0] BaseAddress RWS 0x0 Byte aligned start address of the source buffer. For a pixel width of 32 bits or RLD operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit BaseAd-dress[0] has to be 0.



SourceBufferStride

Description: Source buffer stride


Instance no 0: 0x00030C0C

Table 3-773: SourceBufferStride Register



[15:0] Stride RWS 0x3 Source buffer stride in bytes minus one, used for address generation. For a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of 16 bit Stride has to be dividable by two and given minus one.



SourceBufferAttributes

Description: Source buffer attributes



Table 3-774: SourceBufferAttributes Register



[29:16] LineCount RWS 0x0 Number of lines of the source buffer minus one, needed for tiling.


[13:0] LineWidth RWS 0x0 Width of the source buffer in pixels minus one, needed for tiling.



SourceBufferLength

Description: Source Buffer Length for Run Length Decoding



Table 3-775: SourceBufferLength Register



[28:0] RLEWords RWS 0x0 Number of 32-bit words minus one that are required to decode the run length encoded source buffer. This field is only available in RLD type fetch units.



FrameXOffset

Description: Frame X offset



Table 3-776: FrameXOffset Register


[31:16] FrameXOffset RWS 0x0 Frame X origin offset relative to the source buffer origin, given in signed 16 bit two's complement integer format.

[15:14] FrameXOffsetTwoDeci-malPlaces

RWS 0x0 Fractional bits of the X Offset. This field is only available in non rotation type fetch units.




FrameYOffset

Description: Frame Y offset



Table 3-777: FrameYOffset Register


[31:16] FrameYOffset RWS 0x0 Frame Y origin offset relative to the source buffer origin, given in signed 16 bit two's complement integer format.

[15:14] FrameYOffsetTwoDeci-malPlaces

RWS 0x0 Fractional bits of the Y Offset. This field is only available in non rotation type fetch units.




FrameDimensions

Description: Defines frame rectangle



Table 3-778: FrameDimensions Register


[31] FrameSwapDirections RWS 0x0 Swaps X and Y directions, causes the ras-terizer to first progress in DeltaX stepsizes in Y direction and once it reaches the end of the column increment X by DeltaY and reset Y to FrameYOffset if set to one. This field must not be set to 1 for RLD opera-tions. This field is not available in ROT type fetch units.


[29:16] FrameHeight RWS 0x0 Frame height minus one


[13:0] FrameWidth RWS 0x0 Frame width minus one



DeltaXX

Description: DeltaXX stepsize



Table 3-779: DeltaXX Register



[21:16] DeltaX RWS 0x4 DeltaX stepsize for repetition operation, given in signed fixed-point 4.2 two's com-plement notation. This field must be set to 1 for RLD operations. This field is not avail-able in ROT type fetch units.




DeltaYY

Description: DeltaYY stepsize



Table 3-780: DeltaYY Register



[21:16] DeltaY RWS 0x4 DeltaY stepsize for repetition operation, given in signed fixed-point 4.2 two's com-plement notation. This field must be set to 1 for RLD operations. This field is not avail-able in ROT type fetch units.




SkipWindowOffset

Description: Skip window offset



Table 3-781: SkipWindowOffset Register



[29:16] SkipWindowYOffset RWS 0x0 Skip window Y offset relative to the source buffer origin. Please note that the skip win-dow has to be completely inside the source buffer.


[13:0] SkipWindowXOffset RWS 0x0 Skip window X offset relative to the source buffer origin. Please note that the skip win-dow has to be completely inside the source buffer.



SkipWindowDimensions

Description: Defines skip window rectangle, set to (0,0) when SkipInvert is set to Normal to not skip anypixels at all (disable of skip window) or set to (0,0) when SkipInvert is set to Inverted to skipall pixels inside the sourcebuffer (useful to create a constant color background).



Table 3-782: SkipWindowDimensions Register



[29:16] SkipWindowHeight RWS 0x0 Skip window height. Please note that the skip window has to be completely inside the source buffer.


[13:0] SkipWindowWidth RWS 0x0 Skip window width. Please note that the skip window has to be completely inside the source buffer.



ColorComponentBits

Description: Color component size of source buffer



Table 3-783: ColorComponentBits Register



[27:24] ComponentBitsRed RWS 0x8 Red component bits


[19:16] ComponentBitsGreen RWS 0x8 Green component bits


[11:8] ComponentBitsBlue RWS 0x8 Blue component bits


[3:0] ComponentBitsAlpha RWS 0x8 Alpha component bits



ColorComponentShift

Description: Color component offset of source buffer



Table 3-784: ColorComponentShift Register



[28:24] ComponentShiftRed RWS 0x18 Red component shift


[20:16] ComponentShiftGreen RWS 0x10 Green component shift


[12:8] ComponentShiftBlue RWS 0x8 Blue component shift


[4:0] ComponentShiftAlpha RWS 0x0 Alpha component shift



ConstantColor

Description: Constant color settings. These constant color values are required for tiling modeTILE_FILL_CONSTANT, skip mode CONSTANTCOLOR, fetchsprite background and if acolor component bit width is set to 0.



Table 3-785: ConstantColor Register


[31:24] ConstantColorRed RWS 0x0 Constant red component

[23:16] ConstantColorGreen RWS 0x0 Constant green component

[15:8] ConstantColorBlue RWS 0x0 Constant blue component

[7:0] ConstantColorAlpha RWS 0x0 Constant alpha component



TransparentColor

Description: Transparent color settings. These transparent color values are required for the transparentcolor feature. When the TransparentColorEnable is set to ENABLE then every pixel matchingthese transparent color components will get an alpha value of 0 and 255 otherwise. Pleasegive each color component right aligned. Only the ColorComponentBits LSBs are evaluated,all others are ignored.



Table 3-786: TransparentColor Register



[29:20] TransparentColorRed RWS 0x0 Red transparent color component

[19:10] TransparentColorGreen RWS 0x0 Green transparent color component

[9:0] TransparentColorBlue RWS 0x0 Blue transparent color component



Control

Description: Fetch unit main control register






[25] TransparentColorEnable RWS 0x0 Enable bit for the transparent color feature. If this is enabled every pixel matching to color components in the TransparentColor register will have its alpha value set to 0 and 255 otherwise. If this is disabled the pixel output is not affected by the Transpar-entColor register.

1: ENABLE -

0: DISABLE -


[19:18] EndianSwap RWS 0x0 Configure the endian swap on the 64 bit word. This field is only available in RLD type fetch units. This stage is located before the RLD stage.

0: Disable - Disables any byte swap (default).

1: word_16bit - Perform byte swap on each 16 bit word of the full 64 bit word.

2: word_32bit - Perform byte swap on both 32 bit words of the full 64 bit word.

3: word_64bit - Perform byte swap on the whole 64 bit word.

[17] RLDCmdComp RWS 0x0 Enables use of the Command Compatibility Mode with the Run Length Decompression feature. Use if the length encoded in the header is between 1 and 127. This field is only available in RLD type fetch units.

1: Enable -

0: Disable -

[16] RLDEnable RWS 0x0 Enables use of the Run Length Decom-pression feature. Use if the source buffer is run length encoded. This field is only avail-able in RLD type fetch units.

1: Enable -

0: Disable -

[15] SkipInvert RWS 0x0 Select whether to use a normal or an inverted skip window (outside of skip win-dow is subject to skip instead of inside).

0: Normal -

1: Inverted -



[14] DummySkipSelect RWS 0x0 Select which values to use for skipped pix-els inside the skip rectangle.

0: CONSTANTCOLOR -

1: ZERO -

[13:12] TileMode RWS 0x0 Select the tile mode for pixels outside the source buffer. Please note that the Dum-mySkipSelect register setting takes prece-dence if a pixel becomes subject to both tiling and skip window.

0: TILE_PAD - Use closest pixel from source buffer, this must not be set for RLD operations

1: TILE_FILL_CONSTANT - Use constant color register value

2: TILE_FILL_ZERO - Use zero value

3: reserved - reserved, don't use


[10] ColorMultiplySelect RWS 0x0 Select which multiplicator to use for color multiply. This field is only available if the fetch unit has color multiplication capabili-ties.

0: ALPHA -

1: CONSTANTCOLOR -

[9] ColorMultiplyEnable RWS 0x0 Enable multiplication of color values after constant alpha multiplication stage. This field is only available if the fetch unit has color multiplication capabilities.

1: Enable -

0: Disable -

[8] AlphaMultiply RWS 0x0 Enable multiplication of pixel alpha with constant alpha.

1: Enable -

0: Disable -





[7] RawPixel RWS 0x0 Enable raw pixel mode. If enabled, this will make the fetch unit output a raw pixel engine format instead of the usual 10bit for-mat. The read data from axi will then be directly mapped to the LSBs of the raw pixel engine data word in the specified BitsPerPixel width. The multiply stages and the transparent color feature will automati-cally be deactived when RawPixel is enabled and the corresponding settings will then not have an effect. The ColorCompo-nent registers will not have any effect if this is enabled. Skip and Tile pixels will not be affected by this setting. This field can be used for coordinate layer input to fetchwarp derivate, for example.

1: Enable -

0: Disable -


[5:0] BitsPerPixel RWS 0x20 Pixel size in bits, has to be a power of two or 24. 24 bit per pixel is not supported by the fetch eco derivate.

0x1: TOTALBITS_1 - 1 bit per pixel











ControlTrigger

Description: Fetch unit trigger register



Table 3-788: ControlTrigger Register



[1] EmptyFrame R0W1

X Write a 1 to this field if you want the fetch unit to send an empty frame down the pixel engine pipeline instead of performing a real operation (only shadow load will be per-formed and shadow token be sent if Shd-TokGen has been set or pixel engine synchronizer has requested it) for the next operation.

[0] ShdTokGen R0W1

X Write a 1 to this field if you want the fetch unit to perform a shadow load with the next start of operation and send a shadow token with the next frame.



Start

Description: Fetch unit start register



Table 3-789: Start Register



[0] Start R0W1

X Writing a one starts processing, it is recom-mended to use this for debug purposes only.



FetchType

Description: Fetch unit type register



Table 3-790: FetchType Register



[2:0] FetchType R X This field can be used to determine what kind of fetch unit this is. Values not listed here are reserved.

0: STANDARD - Standard fetch unit with-out rld or rotation capabilities

1: RLD - Fetch unit with RLD capabilities

2: ROT - Fetch unit with rotation capabili-ties

3: LIGHT - Like STANDARD, but without color multiplication capabilities

4: SPRITE - Fetch unit with sprite drawing capabilities

5: WARP - Fetch unit with arbitrary warping capabilities

6: ECO - Fetch unit with most features removed, no 24bpp support



BurstBufferProperties

Description: Burst Buffer Property register



Table 3-791: BurstBufferProperties Register



[12:8] BurstLengthForMaxBuf-fers

R X Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used

[7:0] ManagedBurstBuffers R X Maximum number of burst buffers that can be administrated in the AXI interface



Iris-MVL - FetchSprite Registers

StaticControl

Description: Fetch unit static control register






[9] ToggleField RW 0x0 Enable toggling of the field property from frame to frame.

1: Enable -

0: Disable -

[8] SetField RW 0x0 The field property of the generated frame is set to this value. If field toggle is used, this is the start value.


[5] ClockDisable RW 0x1 Deactivates most internal clocks of fetch unit. Can only be activated if SWReset field is set to SW_RESET.


0x1: POWERDOWN - Clocks are off

[4] SWReset RW 0x1 Puts the fetch unit in software reset. This software reset will not affect the shadow registers.


0x1: SW_RESET - Software Reset





BitsPerPixel

Description: Sets bits per pixel for all sprite source buffers.



Table 3-793: BitsPerPixel Register



[5:0] SpriteBitsPerPixel RW 0x20 Pixel size in bits, has to be a power of two or 24.










ColorComponentBits

Description: Color component size of all source buffers of sprites






[27:24] SpriteComponentBitsRed RW 0x8 Red component bits


[19:16] SpriteComponentBits-Green

RW 0x8 Green component bits


[11:8] SpriteComponentBitsBlue RW 0x8 Blue component bits


[3:0] SpriteComponentBitsAl-pha

RW 0x8 Alpha component bits



ColorComponentShift

Description: Color component offset of all source buffers of sprites






[28:24] SpriteComponent-ShiftRed

RW 0x18 Red component shift


[20:16] SpriteComponentShift-Green

RW 0x10 Green component shift


[12:8] SpriteComponentShift-Blue

RW 0x8 Blue component shift


[4:0] SpriteComponentShiftAl-pha

RW 0x0 Alpha component shift



Sprite00Address

Description: BaseAddress of Sprite0



Table 3-796: Sprite00Address Register


[31:3] Sprite00Address RW 0x0 64bit aligned start address of the sprite0 buffer.




Sprite00Dimension

Description: Dimensions of Sprite0



Table 3-797: Sprite00Dimension Register



[26:16] Sprite00YHeight RW 0x0 Sprite0 height minus one


[10:0] Sprite00XWidth RW 0x0 Sprite0 width minus one



Sprite01Address










Sprite01Dimension












Sprite02Address










Sprite02Dimension












Sprite03Address










Sprite03Dimension












Sprite04Address










Sprite04Dimension












Sprite05Address










Sprite05Dimension












Sprite06Address










Sprite06Dimension












Sprite07Address










Sprite07Dimension












Sprite08Address










Sprite08Dimension












Sprite09Address










Sprite09Dimension












Sprite10Address










Sprite10Dimension












Sprite11Address










Sprite11Dimension












Sprite12Address










Sprite12Dimension












Sprite13Address










Sprite13Dimension












Sprite14Address










Sprite14Dimension












Sprite15Address










Sprite15Dimension












BurstBufferManagement

Description: AXI interface buffer management register



Table 3-828: BurstBufferManagement Register



[12:8] SetBurstLength RWS 0x4 Set this to the burst length that should be used on the AXI interface. Please note that SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of two may be specified as burst length.

[7:0] SetNumBuffers RWS 0x4 Set this to the number of bursts that should be buffered. Please note that SetNumBuf-fers has to be smaller or equal to Managed-BurstBuffers and SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * BurstLengthFor-MaxBuffers. Must be a power of 2. The minimum allowed settings for fetch deri-vates ROT and WARP is 4, and the mini-mum allowed setting for the others is 2. But please note, that for 24 bit per pixel opera-tions the minimum recommended setting is always 4, otherwise performance will suffer.



SpriteEnable

Description: Enables for each sprite



Table 3-829: SpriteEnable Register



[15] Sprite15Enable RWS 0x0 Enables or disables sprite15 (0=disable, 1=enable)


















Sprite00Offset

Description: Offset of Sprite0 relative to output frame origin



Table 3-830: Sprite00Offset Register


[31:16] Sprite00YOffset RWS 0x0 Sprite0 Y origin offset relative to the output frame origin, given in signed 16 bit two's complement integer format.

[15:0] Sprite00XOffset RWS 0x0 Sprite0 X origin offset relative to the output frame origin, given in signed 16 bit two's complement integer format.



Sprite01Offset










Sprite02Offset










Sprite03Offset










Sprite04Offset










Sprite05Offset










Sprite06Offset










Sprite07Offset










Sprite08Offset










Sprite09Offset










Sprite10Offset






[31:16] Sprite10YOffset RWS 0x0 Sprite10 Y origin offset relative to the out-put frame origin, given in signed 16 bit two's complement integer format.

[15:0] Sprite10XOffset RWS 0x0 Sprite10 X origin offset relative to the out-put frame origin, given in signed 16 bit two's complement integer format.



Sprite11Offset










Sprite12Offset










Sprite13Offset










Sprite14Offset










Sprite15Offset










FrameDimensions

Description: Defines frame rectangle



Table 3-846: FrameDimensions Register



[29:16] FrameHeight RWS 0x0 Frame height minus one


[13:0] FrameWidth RWS 0x0 Frame width minus one



ConstantColor

Description: Constant color settings. These constant color values are required for tiling modeTILE_FILL_CONSTANT, skip mode CONSTANTCOLOR, fetchsprite background and if acolor component bit width is set to 0.



Table 3-847: ConstantColor Register


[31:24] ConstantColorRed RWS 0x0 Constant red component

[23:16] ConstantColorGreen RWS 0x0 Constant green component

[15:8] ConstantColorBlue RWS 0x0 Constant blue component

[7:0] ConstantColorAlpha RWS 0x0 Constant alpha component



TransparentColor







[29:20] TransparentColorRed RWS 0x0 Red transparent color component

[19:10] TransparentColorGreen RWS 0x0 Green transparent color component

[9:0] TransparentColorBlue RWS 0x0 Blue transparent color component



Control

Description: Fetch unit main control register





[31] SpriteBackgroundSelect RWS 0x0 What color to choose when displaying a pixel which is not inside a sprite

0: CONSTANTCOLOR -

1: ZERO -

[30:28] SpriteIndexBits RWS 0x0 Number of MSBs of each sprite number that are inserted as MSBs for the red color component, useful for having different color index palettes in the CLUT for different sprites. This field is only available in fetch units with type SPRITE.


[25] TransparentColorEnable RWS 0x0 Enable bit for the transparent color feature. If this is enabled every pixel matching to color components in the TransparentColor register will have its alpha value set to 0 and 255 otherwise. If this is disabled the pixel output is not affected by the Transpar-entColor register.

1: ENABLE -

0: DISABLE -




ControlTrigger

Description: Fetch unit trigger register






[1] EmptyFrame R0W1

X Write a 1 to this field if you want the fetch unit to send an empty frame down the pixel engine pipeline instead of performing a real operation (only shadow load will be per-formed and shadow token be sent if Shd-TokGen has been set or pixel engine synchronizer has requested it) for the next operation.

[0] ShdTokGen R0W1

X Write a 1 to this field if you want the fetch unit to perform a shadow load with the next start of operation and send a shadow token with the next frame.



Start

Description: Fetch unit start register






[0] Start R0W1

X Writing a one starts processing, it is recom-mended to use this for debug purposes only.



FetchType

Description: Fetch unit type register



Table 3-852: FetchType Register



[2:0] FetchType R X This field can be used to determine what kind of fetch unit this is. Values not listed here are reserved.

0: STANDARD - Standard fetch unit with-out rld or rotation capabilities

1: RLD - Fetch unit with RLD capabilities

2: ROT - Fetch unit with rotation capabili-ties

3: LIGHT - Like STANDARD, but without color multiplication capabilities

4: SPRITE - Fetch unit with sprite drawing capabilities

5: WARP - Fetch unit with arbitrary warping capabilities

6: ECO - Fetch unit with most features removed, no 24bpp support



BurstBufferProperties

Description: Burst Buffer Property register



Table 3-853: BurstBufferProperties Register



[12:8] BurstLengthForMaxBuf-fers

R X Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used

[7:0] ManagedBurstBuffers R X Maximum number of burst buffers that can be administrated in the AXI interface



Iris-MVL - ExtSrc Registers

StaticControl

Description: ExtSrc static control register






[8] StartSel RW 0x0 Start select selects the mode to start pro-cessing operations.

0: INPUT - Free running mode, use the incoming command word as trigger to start processing.

1: LOCAL - Keep to local start configura-tion, use external kick or SW trigger to start processing. The behavior is similar to fetch units.





ClipWindowOffset

Description: Clip window offset, to generate a clipping of the frame. It has to be within the input frame.



Table 3-855: ClipWindowOffset Register



[29:16] ClipWindowYOffset RWS 0x0 Clip window offset in Y direction, relative to the frame origin.


[13:0] ClipWindowXOffset RWS 0x0 Clip window offset in X direction, relative to the frame origin.



ClipWindowDimension

Description: Define the clip window dimension. If the clip window feature is enabled this dimension is usedfor the new frame dimension. Note that the clip window has to be smaller or equal to theoriginal frame dimensions. The new frame has to be within the active area of the originalframe.



Table 3-856: ClipWindowDimension Register



[29:16] ClipWindowHeight RWS 0x0 Clip window height minus one


[13:0] ClipWindowWidth RWS 0x0 Clip window width minus one



ColorComponentBits

Description: Color component size of raw input data. Please note that the width must be equal or lowerthan the output width.






[27:24] ComponentBitsRed RWS 0xA Component size of red channel [0-10].


[19:16] ComponentBitsGreen RWS 0xA Component size of green channel [0-10].


[11:8] ComponentBitsBlue RWS 0xA Component size of blue channel [0-10].


[3:0] ComponentBitsAlpha RWS 0x0 Component size of alpha channel [0-10].



ColorComponentShift

Description: Color component offset of raw input data.






[29:24] ComponentShiftRed RWS 0x14 Offset for red component.


[21:16] ComponentShiftGreen RWS 0xA Offset for green component.


[13:8] ComponentShiftBlue RWS 0x0 Offset for blue component.


[5:0] ComponentShiftAlpha RWS 0x0 Offset for alpha component.



ConstantColorRedGreen

Description: Constant color settings for Red and Green channel. These constant color values are requiredif a color component bit width is set to 0.



Table 3-859: ConstantColorRedGreen Register



[25:16] ConstantColorRed RWS 0x0 Constant color red


[9:0] ConstantColorGreen RWS 0x0 Constant color green



ConstantColorBlueAlpha

Description: Constant color settings for Blue and Alpha channel. These constant color values are requiredif a color component bit width is set to 0.



Table 3-860: ConstantColorBlueAlpha Register



[25:16] ConstantColorBlue RWS 0x0 Constant color blue


[7:0] ConstantColorAlpha RWS 0x0 Constant alpha



TransparentColor







[29:20] TransparentColorRed RWS 0x0 Transparent color red component

[19:10] TransparentColorGreen RWS 0x0 Transparent color green component

[9:0] TransparentColorBlue RWS 0x0 Transparent color blue component



Control

Description: ExtSrc unit main control register






[4] ClipWindowEnable RWS 0x0 Enable the clip window feature.

1: ENABLE - Enable the clip window

0: DISABLE - Disable the clip window


[0] TransparentColorEnable RWS 0x0 Enable bit for the transparent color feature. If this is enabled, then every pixel matching to color components in the Transparent-Color register will have its alpha value set to 0 and 255 otherwise. If this is disabled the pixel output is not affected by the TransparentColor register.

1: ENABLE - Enable the transparent color feature

0: DISABLE - Disable the transparent color feature



ControlTrigger

Description: ExtSrc unit trigger token generation






[0] ShdTokGen R0W1

X Write a 1 to this field for the extsrc unit to perform a shadow load with the next start of operation and set the rld bit in the start of frame control word (generate shadow load token for subsequent units).



Start

Description: ExtSrc unit start register






[0] Start R0W1

0x0 Writing a one starts processing, it is recom-mended to use this only for debug pur-poses.



Iris-MVL - CLuT Registers

StaticControl

Description: CLUT static control register


Instance no 0: 0x00032000Instance no 1: 0x00033C00







UnshadowedControl

Description: CLUT unshadowed control register



Table 3-866: UnshadowedControl Register



[2] R_EN RW 0x0 Write enable for writing the red color LUT entry from the host (allows writing a single color entry without a read-modify-write cycle)

0x0: DISABLE - disable

0x1: ENABLE - enable

[1] G_EN RW 0x0 Write enable for writing the green color LUT entry from the host (allows writing a single color entry without a read-modify-write cycle)



[0] B_EN RW 0x0 Write enable for writing the blue color LUT entry from the host (allows writing a single color entry without a read-modify-write cycle)





Control

Description: CLUT control register






[11:8] IDX_BITS RWS 0x8 Number of msb bits of the red color input used for the LUT index input


[6] AlphaInvert RWS 0x0 Chooses whether to disable lookup for alpha components smaller or greater/equal than 128. For this field to have an effect AlphaMask must be set to ENABLE.

0x0: NORMAL - Disable computation for alpha smaller than 128

0x1: INVERT - Disable computation for alpha greater than or equal to 128

[5] AlphaMask RWS 0x0 Enables the alpha mask mode. This mode disables lookup for all pixels with an alpha component smaller or greater/equal than 128. They are bypassed unchanged.

0x0: DISABLE - Alpha mask mode dis-abled

0x1: ENABLE - Alpha mask mode enabled

[4] COL_8BIT RWS 0x0 Color (red, green, blue) output bitwidth select

0x0: DISABLE - color is 10bit output

0x1: ENABLE - color is 8bit output (dither-ing of internal 10bit value)


[1:0] MODE RWS 0x0 Operation mode for color lookup table

0x0: NEUTRAL - module in neutral mode, input data is bypassed to the output

0x1: LUT - module in color lookup mode (LUT holds a 10bit color value lookup value for each input color)

0x2: INDEX_10BIT - module in 10bit color index table mode (LUT holds a 3x10bit color value, indexed with the red input color)

0x3: INDEX_RGBA - module in RGBA color index table mode (LUT holds a 3x8bit color value and a 6bit alpha value, indexed with the red input color)



Status

Description: CLUT status register


Instance no 0: 0x0003200CInstance no 1: 0x00033C0C




[4] READ_TIMEOUT RW1C

0x0 Timeout detected when reading from the LUT


[0] WRITE_TIMEOUT RW1C

0x0 Timeout detected when writing to the LUT



LastControlWord

Description: Value of last received control word, for debugging



Table 3-869: LastControlWord Register


[31:0] L_VAL R X Value of last received control word. For debug purposes only, read when stable only, otherwise read data might be cor-rupted.



LUT

Description: Look Up Table



Table 3-870: LUT Register



[29:20] RED RW X Red component

[19:10] GREEN RW X Green component

[9:0] BLUE RW X Blue component



Iris-MVL - Matrix Registers

StaticControl

Description: Color Matrix static control register









Control

Description: Color Matrix control register






[5] AlphaInvert RWS 0x0 Chooses whether to disable matrix compu-tation for alpha components smaller or greater/equal than 128. For this field to have an effect AlphaMask must be set to ENABLE.

0x0: NORMAL - Disable computation for alpha smaller than 128

0x1: INVERT - Disable computation for alpha greater than or equal to 128

[4] AlphaMask RWS 0x0 Enables the alpha mask mode. This mode disables matrix computation for all pixels with an alpha component smaller or greater/equal than 128.

0x0: DISABLE - Alpha mask mode dis-abled

0x1: ENABLE - Alpha mask mode enabled


[1:0] MODE RWS 0x0 Operation mode for color matrix

0x0: NEUTRAL - Module in neutral mode, input data is bypassed

0x1: MATRIX - Module in matrix mode, input data is multiplied with matrix values

0x2: PREMUL - Module in alpha pre-multi-plication mode, input color is multiplied with input alpha

0x3: RSVD - Reserved, do not use



Red0

Description: Matrix values for calculation of the red output value



Table 3-873: Red0 Register



[26:16] A12 RWS 0x0 Value for Green input in signed fixed-point 3.8 two's complement notation


[10:0] A11 RWS 0x100 Value for Red input in signed fixed-point 3.8 two's complement notation



Red1

Description: Matrix values for calculation of the red output value



Table 3-874: Red1 Register



[26:16] C1 RWS 0x0 Red output offset in signed two's comple-ment integer notation


[10:0] A13 RWS 0x0 Value for Blue input in signed fixed-point 3.8 two's complement notation



Green0

Description: Matrix values for calculation of the green output value



Table 3-875: Green0 Register








Green1

Description: Matrix values for calculation of the green output value



Table 3-876: Green1 Register



[26:16] C2 RWS 0x0 Green output offset in signed two's comple-ment integer notation





Blue0

Description: Matrix values for calculation of the blue output value



Table 3-877: Blue0 Register








Blue1

Description: Matrix values for calculation of the blue output value



Table 3-878: Blue1 Register



[26:16] C3 RWS 0x0 Blue output offset in signed two's comple-ment integer notation





LastControlWord

Description: Value of last received control word, for debugging



Table 3-879: LastControlWord Register


[31:0] L_VAL R X Value of last received control word. For debug purposes only, read when stable only, otherwise read data might be cor-rupted.



Iris-MVL - LayerBlend Registers

StaticControl

Description: Layer Blend static control register






[2] ShdLdSel RW 0x0 Only effective if ShdTokEpSrc is set to 1. If set to PRIMARY, the layerblend unit will load its shadows with every shadow load token received on the primary input, if set to SECONDARY, the layerblend unit will load its shadows with every shadow load token received on the secondary input.

0: PRIMARY - Load shadows with primary input shadow load token

1: SECONDARY - Load shadows with sec-ondary input shadow load token

[1] ShdTokEpSec RW 0x0 Enables Shadow Token Endpoint of the layerblend units secondary input. If enabled, a shadow load interrupt is gener-ated if a command word with rld flag set (shadow token) is received on the second-ary input. Otherwise the token is passed to subsequent units. (1=enable, 0=disable)




Control

Description: Layer Blend control register





[31:24] ALPHA RWS 0x0 Constant alpha value, used for constant alpha blending


[22:20] AlphaMaskMode RWS 0x0 AlphaMaskMode determines how the out-put alpha is generated when AlphaMaskE-nable is set to ENABLE

0x0: PRIM - Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0

0x1: SEC - The area of the secondary input will get an alpha value of 255 and the rest will be 0

0x2: PRIM_OR_SEC - Behaves as if the output of modes PRIM and SEC would be ORed together

0x3: PRIM_AND_SEC - Behaves as if the output of modes PRIM and SEC would be ANDed together

0x4: PRIM_INV - Behaves as if the output of mode PRIM would be inverted

0x5: SEC_INV - Behaves as if the output of mode SEC would be inverted

0x6: PRIM_OR_SEC_INV - Behaves as if the output of modes PRIM and SEC_INV would be ORed together

0x7: PRIM_AND_SEC_INV - Behaves as if the output of modes PRIM and SEC_INV would be ANDed together




[18:16] SEC_A_BLD_FUNC RWS 0x0 Secondary (overlay) input color blending function

0x0: ZERO - Aout = Ain * 0

0x1: ONE - Aout = Ain * 1

0x2: PRIM_ALPHA - Aout = Ain * ALPHA_pim

0x3: ONE_MINUS_PRIM_ALPHA - Aout = Ain * (1 - ALPHA_pim)

0x4: SEC_ALPHA - Aout = Ain * ALPHA_sec

0x5: ONE_MINUS_SEC_ALPHA - Aout = Ain * (1 - ALPHA_sec)

0x6: CONST_ALPHA - Aout = Ain * ALPHA_const

0x7: ONE_MINUS_CONST_ALPHA - Aout = Ain * (1 - ALPHA_const)


[14:12] PRIM_A_BLD_FUNC RWS 0x0 Primary (background) input color blending function

0x0: ZERO - Aout = Ain * 0

0x1: ONE - Aout = Ain * 1

0x2: PRIM_ALPHA - Aout = Ain * ALPHA_pim

0x3: ONE_MINUS_PRIM_ALPHA - Aout = Ain * (1 - ALPHA_pim)

0x4: SEC_ALPHA - Aout = Ain * ALPHA_sec

0x5: ONE_MINUS_SEC_ALPHA - Aout = Ain * (1 - ALPHA_sec)

0x6: CONST_ALPHA - Aout = Ain * ALPHA_const

0x7: ONE_MINUS_CONST_ALPHA - Aout = Ain * (1 - ALPHA_const)






[10:8] SEC_C_BLD_FUNC RWS 0x0 Secondary (overlay) input color blending function

0x0: ZERO - Cout = Cin * 0

0x1: ONE - Cout = Cin * 1

0x2: PRIM_ALPHA - Cout = Cin * ALPHA_pim

0x3: ONE_MINUS_PRIM_ALPHA - Cout = Cin * (1 - ALPHA_pim)

0x4: SEC_ALPHA - Cout = Cin * ALPHA_sec

0x5: ONE_MINUS_SEC_ALPHA - Cout = Cin * (1 - ALPHA_sec)

0x6: CONST_ALPHA - Cout = Cin * ALPHA_const

0x7: ONE_MINUS_CONST_ALPHA - Cout = Cin * (1 - ALPHA_const)


[6:4] PRIM_C_BLD_FUNC RWS 0x0 Primary (background) input color blending function

0x0: ZERO - Cout = Cin * 0

0x1: ONE - Cout = Cin * 1

0x2: PRIM_ALPHA - Cout = Cin * ALPHA_pim

0x3: ONE_MINUS_PRIM_ALPHA - Cout = Cin * (1 - ALPHA_pim)

0x4: SEC_ALPHA - Cout = Cin * ALPHA_sec

0x5: ONE_MINUS_SEC_ALPHA - Cout = Cin * (1 - ALPHA_sec)

0x6: CONST_ALPHA - Cout = Cin * ALPHA_const

0x7: ONE_MINUS_CONST_ALPHA - Cout = Cin * (1 - ALPHA_const)


[2] AlphaMaskEnable RWS 0x0 Enables Alpha Mask feature. This will limit possible output alpha values to 0 and 255. Generation of this alpha value will depend on the AlphaMaskMode field.

0x0: DISABLE - AlphaMask feature dis-abled

0x1: ENABLE - AlphaMask feature enabled






[0] MODE RWS 0x0 LayerBlend operation mode

0x0: NEUTRAL - module in neutral mode, output is primary (background) input

0x1: BLEND - module in blending mode





Position

Description: Position of secondary (overlay) input frame



Table 3-882: Position Register


[31:16] YPOS RWS 0x0 vertical position, first pixel is at 0, format s15 (twos complement)

[15:0] XPOS RWS 0x0 horizontal position, first pixel is at 0, format s15 (twos complement)



PrimControlWord

Description: Value of last received primary (background) control word, for debugging



Table 3-883: PrimControlWord Register


[31:0] P_VAL R X Value of last received control word



SecControlWord

Description: Value of last received secondary (overlay) control word, for debugging



Table 3-884: SecControlWord Register


[31:0] S_VAL R X Value of last received control word



Iris-MVL - ExtDst Registers

StaticControl

Description: External Destination output control






[4] PerfCountMode RW 0x0 Performance Counter Mode enable. When in performance counter mode, the extdst unit will not forward any data from its input to its output while not stalling the input. This mode can be used to determine the theo-retic performance of the path up to this point without influence from display control-ler stalls. Use for debug purposes only.

0x1: ENABLE - Performance counter mode

0x0: DISABLE - Normal operation mode


[0] KICK_MODE RW 0x0 Operation mode of generated kick signal

0x0: SOFTWARE - kick generation by KICK field only

0x1: EXTERNAL - kick signal from exter-nal allowed



SoftwareKick

Description: External Destination software kick



Table 3-886: SoftwareKick Register



[0] KICK R0W1

0x0 Software kick, forces a kick signal indepen-dent of KICK_MODE. Write 1 to send kick.



Status

Description: External Destination Unit current status






[0] CNT_ERR_STS RW1C

0x0 Pixel count error



ControlWord

Description: Value of last received control word



Table 3-888: ControlWord Register


[31:0] CW_VAL R X Value of last received control word



CurPixelCnt

Description: pixel count of currently running frame



Table 3-889: CurPixelCnt Register


[31:16] C_YVAL R X value of vertical line counter, internal coun-ter counting from max-1 to 0

[15:0] C_XVAL R X value of horizontal pixel counter, internal counter counting from max-1 to 0



LastPixelCnt

Description: pixel count between last two control words



Table 3-890: LastPixelCnt Register


[31:16] L_YVAL R X value of vertical line counter

[15:0] L_XVAL R X value of horizontal pixel counter



PerfCounter

Description: Performance counter result



Table 3-891: PerfCounter Register


[31:0] PerfResult R 0x0 Returns the performance counter value. Returns number of cycles of the last frame on the input. To calculate the performance divide the known number of pixels of the frame by this number. For debug purposes only, read when stable only, otherwise read data might be corrupted.



Iris-MVL - FrameCap Registers

Ctr

Description: FrameCap Control Register



Table 3-892: Ctr Register



[0] Cen RW 0x0 Enable bit for FrameCap unit (Cen=1). Capture starts with next frame sync signal.

When disabling FrameCap unit (Cen=0), current frame is completed before Frame-Cap is stopped.



Spr

Description: FrameCap Sync Polarity Register



Table 3-893: Spr Register



[2] PolVs RW 0x0 Change polarity of video signal vsync.

0x0: LowAct - Signal is active low (default).

0x1: HighAct - Signal is active high.

[1] PolHs RW 0x0 Change polarity of video signal hsync.

0x0: LowAct - Signal is active low (default).

0x1: HighAct - Signal is active high.

[0] PolEn RW 0x0 Change polarity of video signal enable.

0x0: HighAct - Signal is active high (default).

0x1: Lowact - Signal is active low.



Fdr

Description: FrameCap Frame Dimension Register



Table 3-894: Fdr Register



[29:16] Height RW 0xEF Expected frame heigth of video frame (value is Heigth - 1). Frames sent to pixel engine have always the programmed height.


[13:0] Width RW 0x13F Expected frame width of video frame (value is Width - 1). Frames sent to pixel engine have always the programmed width.



Kcr

Description: FrameCap Kick Config Register



Table 3-895: Kcr Register



[27:0] KickDel RW 0x0 Delay after receiving last active pixel in frame (in video clock cycles) until the kick pulse is generated.

In any case the kick pulse is generated with first active pixel of next frame latest.



Scr

Description: FrameCap Sync Config Register



Table 3-896: Scr Register



[3:0] Fus RW 0x2 Number of consecutive frames captured until synchronisation state is reached (value of 0 is not allowed).

indicated by sts signal and register field Str.SyncStat.



Sts

Description: FrameCap Status Register. Shows current status of the FrameCap module.



Table 3-897: Sts Register



[8] SyncStat R 0x0 Indicates the current state of synchroniza-tion (0 = out of sync, 1 = in sync; not locked).


[2] VsEarly R 0x0 VSYNC is detected too early. The received frame is too small (bit locked when 1, clear by writing ClrStat field).

[1] VsLate R 0x0 VSYNC is detected too late. The received frame is too big (bit locked when 1, clear by writing ClrStat field).

[0] FifoFull R 0x0 Write Access to the full pixel FIFO (bit locked when 1, clear by writing ClrStat field).



StsClr

Description: FrameCap Status Clear Register. Clears the locked status bits in Sts register.



Table 3-898: StsClr Register



[0] ClrStat R0W1

0x0 Clears locked status bits in Sts register.



FRCnt

Description: FrameCap Frame Rate Count Register.



Table 3-899: FRCnt Register


[31:0] FRCount R 0x0 Shows frame duration of video input counted in video clock cycles. Updated using vsync (for debugging purposes only).



Iris-MVL - FrameGen_PS Registers

LockUnlock






[31:0] LockUnlock W 0x0 Write lock or unlock key to this field in order to change lock status.




LockStatus








0: Unlocked - Locking Mechanism is unlocked.

1: Locked - Locking Mechanism is locked.



FgStCtrl

Description: FrameGen Static Control Register



Table 3-902: FgStCtrl Register



[4] ShdTokEpSec RW 0x1 Enable shadow load token end-point on secondary input.

If enabled, a shadow load interrupt is gen-erated when a shadow load token is received on that input.

Otherwise the token is passed to the sub-sequent unit.

[3] ShdTokEpPrim RW 0x1 Enable shadow load token end-point on pri-mary input.

If enabled, a shadow load interrupt is gen-erated when a shadow load token is received on that input.

Otherwise the token is passed to the sub-sequent unit.

[2:1] ShdLdSel RW 0x0 Shadow load event for RWS type configu-ration fields.

0x0: TRIGGER - ShdTokGen only (explicit SW trigger).

0x1: PRIM - ShdTokGen or shadow load token on primary input stream.

0x2: SEC - ShdTokGen or shadow load token on secondary input stream.

0x3: BOTH - ShdTokGen or shadow load token on either primary or secondary input stream.

[0] ShdEn RW 0x0 Enables shadowing for RWS type configu-ration fields.

Otherwise shadow registers are immedi-ately updated when written.



HtCfg1

Description: FrameGen Horizontal Timing Config Register 1



Table 3-903: HtCfg1 Register



[29:16] Htotal RW 0x18F Total horizontal size of frame in pixels.

(Set value +1 is the total horizontal size of frame)

Htotal shall be greater or equal than Hact + Hsbp.

Note1: Valid setup for horizontal video tim-ing contains parameters Hact, Htotal, Hsbp and, if enabled, Hsync.

Note2: If SRAdj==1 then Htotal[0] shall be equal the value of SREven (for sec. chan-nel only).


[13:0] Hact RW 0x140 Horizontal size of active display area in pix-els.

Hact shall be greater or equal than 4.

Note: Valid setup for horizontal video timing contains parameters Hact, Htotal, Hsbp and, if enabled, Hsync.



HtCfg2

Description: FrameGen Horizontal Timing Config Register 2



Table 3-904: HtCfg2 Register


[31] HsEn RW 0x1 Enables generation of HSYNC pulse.


[29:16] Hsbp RW 0x47 Width of HSYNC pulse plus width of hori-zontal back porch in pixels.

(Set value +1 is the width of HSYNC pulse plus width of horizontal back porch)

Hsbp shall be greater or equal than Hsync.



[13:0] Hsync RW 0x1F Width of HSYNC pulse in pixels.

(Set value +1 is the width of HSYNC pulse)

HSYNC is of zero width if HsEn==0.




VtCfg1

Description: FrameGen Vertical Timing Config Register 1



Table 3-905: VtCfg1 Register



[29:16] Vtotal RW 0xFC Total vertical size of frame in lines.

(Set value +1 is the total vertical size of frame)

Vtotal shall be greater or equal than Vact + Vsbp.

Note: Valid setup for vertical video timing contains parameters Vact, Vtotal, Vsbp and, if enabled, Vsync.


[13:0] Vact RW 0xF0 Vertical size of active display area in lines.

Vact shall be greater or equal than 4.




VtCfg2

Description: FrameGen Vertical Timing Config Register 2



Table 3-906: VtCfg2 Register


[31] VsEn RW 0x1 Enables generation of VSYNC pulse.


[29:16] Vsbp RW 0x9 Width of VSYNC pulse plus width of vertical back porch in lines.

(Set value +1 is the width of VSYNC pulse plus width of vertical back porch)

Vsbp shall be greater or equal than Vsync.



[13:0] Vsync RW 0x3 Width of VSYNC pulse in lines.

(Set value +1 is the width of VSYNC puls)

VSYNC is of zero width if VsEn==0.




Int0Config

Description: Coordinates of the trigger point for generation of the Int0 interrupt signal



Table 3-907: Int0Config Register


[31] Int0En RW 0x0 Enables Int0.


[29:16] Int0Row RW 0x0 Specifies on which row of the display raster the Int0 signal is triggered (1 .. Int0Row .. VTOTAL).

Adaptive display timing must be taken into account when defining Int0Row (1 .. Int0Row .. VTOTAL_MIN).

[15] Int0HsEn RW 0x0 When enabled, Int0Row setting is ignored so that the interrupt occurs every line at position given by Int0Col.


[13:0] Int0Col RW 0x0 Specifies on which column of the display raster the Int0 signal is triggered (1 .. Int0Col .. HTOTAL).

Adaptive display timing must be taken into account when defining Int0Col (1 .. Int0Col .. HTOTAL_MIN).



Int1Config






[31] Int1En RW 0x0 Enables Int1 (irq[1]).










Int2Config
















Int3Config
















PKickConfig

Description: Coordinates of the trigger point for generation of the primary kick signal



Table 3-911: PKickConfig Register


[31] PKickEn RW 0x0 Enables pkick signal.


[29:16] PKickRow RW 0x0 Specifies on which row of the display raster the pkick signal is triggered (1 .. PKickRow .. VTOTAL).

Adaptive display timing must be taken into account when defining PKickRow (1 .. PKickRow .. VTOTAL_MIN).

[15] PKickInt0En RW 0x0 If enabled, maps the primary kick signal (pkick) on the interrupt pin int0. Overrides int0en.


[13:0] PKickCol RW 0x0 Specifies on which column of the display raster the pkick signal is triggered (1 .. PKickCol .. HTOTAL).

Adaptive display timing must be taken into account when defining PKickCol (1 .. PKickCol .. HTOTAL_MIN).



SKickConfig

Description: Coordinates of the trigger point for generation of the secondary kick signal



Table 3-912: SKickConfig Register


[31] SKickEn RW 0x0 Enables generation of internal skick signal.

[30] SKickTrig RW 0x0 Select source for skick generation.

0x0: INTERNAL - Use internal skick sig-nal, trigger point defined by SKickRow and SKickCol.

0x1: EXTERNAL - Use external skick input as trigger.

[29:16] SKickRow RW 0x0 Specifies on which row of the display raster the skick signal is triggered (1 .. SKickRow .. VTOTAL).

Adaptive display timing must be taken into account when defining SKickRow (1 .. SKickRow .. VTOTAL_MIN).

[15] SKickInt1En RW 0x0 If enabled, maps the secondary kick signal (skick) on the interrupt pin int1. Overrides int1en.


[13:0] SKickCol RW 0x0 Specifies on which column of the display raster the skick signal is triggered (1 .. SKickCol .. HTOTAL).

Adaptive display timing must be taken into account when defining SKickCol (1 .. SKickCol .. HTOTAL_MIN).



SecStatConfig

Description: Configuration register for controlling the behaviour of the SecSyncStat field in theFgSecChStat register.



Table 3-913: SecStatConfig Register



[11:8] LevSkewInRange RW 0x1 Number of continous frames the measured skew value shall be within the range defined by SyncRangeLow and Syn-cRangeHigh.

If this condition is true, additionally Lev-GoodFrames valid frames must be pro-cessed before the status line of the sec. channel

and the SecSyncStat status field goes to 1 indicating synchronized status.

Value of 0 is not allowed.

[7:4] LevBadFrames RW 0x1 Not used.

[3:0] LevGoodFrames RW 0x2 Number of continous correct frames that must be processed before SecSyncStat field goes 1 (in sync).

Value of 0 is not allowed.



FgSRCR1

Description: FrameGen Skew Regulation Control Register 1.



Table 3-914: FgSRCR1 Register



[17] SREpOff RW 0x0 Disables the skew Extrapolation in blank-ing.

[16] SRDbgDisp RW 0x0 If enabled, the pixels are displayed that are read from FIFO when secondary channel is not in sync yet.

Otherwise constant color is displayed in unsynchronized state.


[8:7] SRQVal RW 0x0 If SRQAlign is enabled, this field deter-mines the fixed value of the two LSB bits of HTOTAL.

Note: This has impact on the settings for Htotal, HtotalMin and HtotalMax.

0x0: ZERO - Fixed two LSB values of HTO-TAL are 0b00.

0x1: ONE - Fixed two LSB values of HTO-TAL are 0b01.

0x2: TWO - Fixed two LSB values of HTO-TAL are 0b10.

0x3: THREE - Fixed two LSB values of HTOTAL are 0b11.

[6] SRQAlign RW 0x0 Enables alignment of HTOTAL to be a mul-tiple of 4. Overrides SREven field.

Program field SRQVal for the desired value of the two LSB bits of HTOTAL.

[5] SRFastSync RW 0x0 Fast Synchronization Mode.

Frame Generator is started synchronized to frame timing on secondary channel when switching FgEn from 0 to 1.

This allows fast locking of skew regulation.

[4] SREven RW 0x0 Total line length HTOTAL is even when SRAdj is enabled.

Note: This has impact on the settings for Htotal, HtotalMin and HtotalMax.



[3] SRAdj RW 0x0 Enables line length adjustment for HTO-TAL.

If SRQAlign=0, SREven determines whether HTOTAL has odd (SREven=0) or even (SrEven=1) number of pixels.

If SRQAlign=1, SRQVal determines the value of the two LSB bits of HTOTAL.

[2:1] SRMode RW 0x0 Skew Control Operating Mode.

0x0: OFF - Skew Regulation is off.

0x1: HREG - Horizontal regulation enabled.

0x2: VREG - Vertical regulation enabled.

0x3: BOTH - Both regulation modes are enabled.

[0] SREn RW 0x0 If enabled, skew control for secondary channel is active.

If disabled, skew control for secondary channel is in fetch mode.

Fetch mode: secondary channel fetches frames and can intentionally produce a backstall via setting sbusy signal to active.

This mode is intended to fetch frames from memory via a stallable pipeline, like the pri-mary interface.

No timing adaption of frames takes place in this mode.





FgSRCR2

Description: FrameGen Skew Regulation Control Register 2






[29:16] HTotalMax RW 0x1B7 Maximum value of htotal when horizontal regulation is enabled.

(Set value +1 is the maximum value of hto-tal)

HTotalMax must be greater or equal Htotal.

Note: If SRAdj==1 then HtotalMax[0] shall be equal to the value of SREven.


[13:0] HTotalMin RW 0x188 Minimum value of htotal when horizontal regulation is enabled.

(Set value +1 is the minimum value of hto-tal,

must be greater or equal Hsbp + Hactive)

HTotalMin must be smaller or equal Htotal.

Note: If SRAdj==1 then HtotalMin[0] shall be equal to the value of SREven.



FgSRCR3







[29:16] VTotalMax RW 0x115 Maximum value of vtotal when vertical reg-ulation is enabled.

(Set value +1 is the maximum value of vto-tal)


[13:0] VTotalMin RW 0xFB Minimum value of vtotal when vertical regu-lation is enabled.

(Set value +1 is the minimum value of vto-tal,

must be greater or equal Vsbp + Vactive + 1)



FgSRCR4







[28:0] TargetSkew RW 0xC8 Horizontal target skew value for horizontal and vertical skew regulation (signed value).



FgSRCR5







[28:0] SyncRangeLow RW 0x0 Sync range of horizontal and vertical skew regulation. Lower value (signed value).

If skew stays within programmed sync range, frame status is assumed synchro-nized.



FgSRCR6







[28:0] SyncRangeHigh RW 0x190 Sync range of horizontal and vertical skew regulation. Upper value (signed value).

If skew stays within programmed sync range, frame status is assumed synchro-nized.



FgKSDR

Description: FrameGen Kick System Debug Register



Table 3-920: FgKSDR Register



[18:16] SCntCplMax RW 0x2 Maximum Value for spendcnt_cpl_s com-plementary secondary kick counter. Do not change!


[2:0] PCntCplMax RW 0x2 Maximum Value for ppendcnt_cpl_s com-plementary primary kick counter. Do not change!



PaCfg

Description: FrameGen Primary Area Config Register 1 (shadowed)



Table 3-921: PaCfg Register



[29:16] Pstarty RWS 0x1 Primary screen upper left corner, y compo-nent. Counts from 1. Pstarty = 0 is not allowed.

Primary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal.


[13:0] Pstartx RWS 0x1 Primary screen upper left corner, x compo-nent. Counts from 1. Pstartx = 0 is not allowed.

Primary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal.



SaCfg

Description: FrameGen Secondary Area Config Register 1 (shadowed)



Table 3-922: SaCfg Register



[29:16] Sstarty RWS 0x1 Secondary screen upper left corner, y com-ponent. Counts from 1 . Sstarty = 0 is not allowed.

Secondary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal.

When skew regulation feature is enabled, the secondary screen shall not overlap the active display area defined by Hact and Vact.


[13:0] Sstartx RWS 0x1 Secondary screen upper left corner, x com-ponent. Counts from 1 . Sstartx = 0 is not allowed.

Secondary screen shall not overlap the last column/ last row of the total frame defined by Htotal/ Vtotal.

When skew regulation feature is enabled, the secondary screen shall not overlap the active display area defined by Hact and Vact.



FgInCtrl

Description: FrameGen Input Control Register (shadowed)



Table 3-923: FgInCtrl Register



[2:0] FgDm RWS 0x6 Frame Generator Display Mode.

0x0: BLACK - Black Color Background is shown.

0x1: CONSTCOL - Constant Color Back-ground is shown.

0x2: PRIM - Primary input only is shown.

0x3: SEC - Secondary input only is shown.

0x4: PRIM_ON_TOP - Both inputs over-laid with primary on top.

0x5: SEC_ON_TOP - Both inputs overlaid with secondary on top.

0x6: TEST - White color background with test pattern is shown.



FgInCtrlPanic

Description: FrameGen Input Control Panic Register (shadowed)



Table 3-924: FgInCtrlPanic Register



[2:0] FgDmPanic RWS 0x0 Frame Generator Display Mode when Panic Switch active.

0x0: BLACK - Black Color Background is shown.

0x1: CONSTCOL - Constant Color Back-ground is shown.

0x2: PRIM - Primary input only is shown.

0x3: SEC - Secondary input only is shown.

0x4: PRIM_ON_TOP - Both inputs over-laid with primary on top.

0x5: SEC_ON_TOP - Both inputs overlaid with secondary on top.

0x6: TEST - White color background with test pattern is shown.



FgCCR

Description: FrameGen Constant Color Register (shadowed)



Table 3-925: FgCCR Register



[24] CcAlpha RWS 0x1 Constant color - alpha value.

[23:16] CcRed RWS 0xFF Constant color - red component.

[15:8] CcGreen RWS 0xFF Constant color - green component.

[7:0] CcBlue RWS 0xFF Constant color - blue component.



FgEnable

Description: FrameGen Enable Register



Table 3-926: FgEnable Register



[0] FgEn RW 0x0 Frame Generator Enable.

Note: For loading the shadow registers at start-up of FrameGen unit write

the FgSlr.ShdTokGen field immediately before writing this field.



FgSlr

Description: FrameGen Shadow Load Register



Table 3-927: FgSlr Register



[0] ShdTokGen R0W1

0x0 Generate shadow load token.

Can be used to load shadow register in this and/or all subsequent units up to the next token end point.



FgEnSts

Description: FrameGen Enable Status Register



Table 3-928: FgEnSts Register



[1] PanicStat R 0x0 Current status of panic mode (0=normal operation mode, 1=panic mode; not locked).

[0] EnSts R 0x0 Indicates the current operating mode of the frame generator.

EnSts = 0 means frame generator is dis-abled.

EnSts = 1 means frame generator is enabled.

In contrast to the FgEn field of the FgEn-able register this bit goes only 0

when all pending frames are processed.



FgChStat

Description: FrameGen Channel Status Register



Table 3-929: FgChStat Register



[24] SecSyncStat R 0x0 Current status secondary channel synchro-nization (0 = out of sync, 1 = in sync; not locked).


[17] SkewRangeErr R 0x0 The secondary channel skew value has run out of the limit defined by SyncRangeLow and SyncRangeHigh. (bit locked when 1, clear by using ClrSecStat).

[16] SFifoEmpty R 0x0 Read request to empty secondary pixel FIFO detected. (bit locked when 1, clear by using ClrSecStat).


[8] PrimSyncStat R 0x0 Current status primary channel synchroni-zation (0 = out of sync (frame tearing), 1 = in sync (normal operation); not locked).


[0] PFifoEmpty R 0x0 Read request to empty primary pixel FIFO detected. (Bit locked when 1, clear by using ClrPrimStat).



FgChStatClr

Description: FrameGen Channel Status Clear Register



Table 3-930: FgChStatClr Register



[16] ClrSecStat R0W1

0x0 Clears SFifoEmpty and SkewRangeErr in FgChStat register.


[0] ClrPrimStat R0W1

0x0 Clears PFifoEmpty in FgChStat register.



FgSkewMon

Description: FrameGen Skew Monitor Register for Secondary Channel Skew Control



Table 3-931: FgSkewMon Register



[28:0] SkewMon R 0x0 Current skew value monitor for secondary channel skew control. Updated with hlast.

(For debugging purposes only).



FgSFifoMin

Description: FrameGen Secondary FIFO Min Fill Register



Table 3-932: FgSFifoMin Register



[10:0] SFifoMin R 0x0 Shows the minimal fill level of the second-ary channel pixel FIFO.




FgSFifoMax

Description: FrameGen Secondary FIFO Max Fill Register



Table 3-933: FgSFifoMax Register



[10:0] SFifoMax R 0x0 Shows the maximal fill level of the second-ary channel pixel FIFO.




FgSFifoFillClr

Description: FrameGen Secondary FIFO Fill Clear Register



Table 3-934: FgSFifoFillClr Register



[0] SFifoFillClr R0W1

0x0 Write for clearing register FgSFifoMin and FgSFifoMax.




FgSrEpD

Description: FrameGen Skew Regulation ExtraPolation Debug Register



Table 3-935: FgSrEpD Register



[28:0] EpVal R 0x0 Calculated value for line skew extrapolation in blanking.

Updated with condition "hlast AND vlast".

(For debugging purposes only)



FgSrFtD

Description: FrameGen Skew Regulation Frame Total Debug Register



Table 3-936: FgSrFtD Register



[27:0] FrTot R 0x0 Measured value for frame total measured in display clock cycles.

Updated with condition "hlast AND vlast" when first FrTot value is valid.

(For debugging purposes only)



Iris-MVL - Dither Registers

Control

Description: Dither Unit common control.






[0] mode RW 0x0 Mode which switches Dither Unit on/off.

0x0: NEUTRAL - Neutral mode. Pixels by-pass the Dither Unit, all other settings are ignored.

0x1: ACTIVE - Dither Unit is active.



DitherControl

Description: Dither Unit processing control.



Table 3-938: DitherControl Register



[25:24] alpha_mode RW 0x0 Enables/disables that dithering can be switched by alpha bit.

0x0: DISABLE - The alpha bit is not consid-ered.

0x1: ENABLE_BY1 - Red, green and blue components are only dithered, if the alpha bit is 1.

0x2: ENABLE_BY0 - Red, green and blue components are only dithered, if the alpha bit is 0.


[21:20] algo_select RW 0x3 The number of output colors that can virtu-ally be displayed by dithering is slightly lower than the number of physical input col-ors. This field selects how the mapping is done.

0x1: NO_CORRECTION - Best possible resolution for most dark colors. Adds a diminutive offset to overall image bright-ness.

0x2: BRIGHTNESS_CORRECTION - Pre-serves overall image brightness. Cannot resolve most dark and most bright colors. All codes in-between are distributed per-fectly smooth.

0x3: CONTRAST_CORRECTION - Pre-serves overall image brightness. Best pos-sible distribution of color codes over complete range.


[16] offset_select RW 0x0 Selects the method how the dither offset is calculated.

0x0: OFFS_SPATIAL - Offset is a bayer matrix value, which is selected according to pixel frame position.

0x1: OFFS_TEMPORAL - Offset is the sum from a bayer matrix value, which is selected according to pixel frame position, and a value from a regular sequence, which changes each frame.




[10:8] red_range_select RW 0x2 Mode which sets the reduction of compo-nent widths.

0x2: RED_10TO8 - Reduces red compo-nent width from 10 bit to 8bit.





[6:4] green_range_select RW 0x2 Mode which sets the reduction of compo-nent widths.

0x2: GREEN_10TO8 - Reduces green component width from 10 bit to 8bit.





[2:0] blue_range_select RW 0x2 Mode which sets the reduction of compo-nent widths.

0x2: BLUE_10TO8 - Reduces blue compo-nent width from 10 bit to 8bit.




Table 3-938: DitherControl Register




Release

Description: Dither Unit release.



Table 3-939: Release Register



[15:8] version R 0x0 Dither Unit version.

[7:0] subversion R 0x0 Dither Unit subversion.



Iris-MVL - TCon Registers

SSqCnts

Description: The 64 Sequencer Position Definitions registers define the X/Y scan positions of thesequencers, hold their output value and assign the sequencer to an odd/even field



Table 3-940: SSqCnts Register


[31] SSQCNTS_OUT RW X This bit holds the value (0,1) to be output when the X/Y scan position is reached.

[30:16] SSQCNTS_SEQX RW X X scan position

[15] Reserved RW X -

[14:0] SSQCNTS_SEQY RW X Y scan position



SSqCycle

Description: This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencercycles



Table 3-941: SSqCycle Register



[5:0] SSQCYCLE RW 0x0 Sequencer cycle length (number -1) of sequencer cycles



SWreset

Description: TCON Software Reset - Reset all tcon registers except configuration registers. Detaileddescription in specification document



Table 3-942: SWreset Register



[0] SWReset RW 0x0 Software reset

0x0: INACTIVE - operation mode

0x1: ACTIVE - So long SWReset = 0x1 tcon is in 'SW reset state' and it is released by internal logic (SWReset is released and end of frame arrived), read: 0b: reset not active 1b: reset active (that means NO pixel of video frame is excepted until 'SW reset state' is released)



TCON_CTRL

Description: TCON Control register



Table 3-943: TCON_CTRL Register



[29:16] SplitPosition RW 0x140 Index of first column of right display half when ChannelMode is DUAL_SPLIT.

- SplitPosition must be less or equal 1280

- (Hact - SplitPosition) must be less or equal 1280

- If (SplitPosition greater than (Hact - Split-Position)) Htotal greather 2*SplitPosition

else Htotal greather (Hact - SplitPosition)



[11] LVDS_CLOCK_INV RW 0x0 Inversion the polatity of lvds clock in Open-LDI Mode

0x01: INV - Invert LVDS Clock

0x0: NON_INV - NON-Invert LVDS Clock

[10] LVDS_Balance RW 0x1 Operation mode of LVDS-OpenLDI

0x1: BALANCED - LVDS operates in 24 bits Balanced Mode

0x0: UNBALANCED - LVDS operates in 24 bits Unbalanced Mode

[9] LVDSMode RW 0x0 Selection the LVDS Mode if EnLVDS = ENABLE_LVDS

0x0: LVDS - LVDS Mode, refered to Open-LDI

[8] EnLVDS RW 0x0 Enable LVDS Mode

0x1: ENABLE_LVDS - Enable LVDS , TTL and RSDS are disable

0x0: DISABLE_LVDS - Disable LVDS, Enable TTL and RSDS



[7:4] Inv_Ctrl RW 0x0 Minimize the toggle rate of tcon output for display panel, that supports data inversion control. Otherwise set Inv_Ctrl = 0.

Valid for all channels .

Inv_Ctrl does not effect any function on LVDS-Output.

0x0: DISABLE - Disable inversion control

0x1: RGB_2_BITS - Enable inversion con-trol for number of RGB-Bits = 2




0x5: RGB_10_BITS - Enable inversion control for number of RGB-Bits = 10





0xA: RGB_20_BITS - Enable inversion control for number of RGB-Bits = 20

0xB: RGB_22_BITS - Enable inversion control for number of RGB-Bits = 22

0xC: RGB_24_BITS - Enable inversion control for number of RGB-Bits = 24

0xD: RESERVED1 - RESERVED1

0xE: RESERVED2 - RESERVED2

0xF: RESERVED3 - RESERVED3

[3] Bypass RW 0x1 Bypassing synchronization

0x0: TCON_MODE - tcon operation mode

0x1: BYPASS_MODE - tcon in Bypass mode. input pixel and its sync-signals are bypassed to tcon-output

[2] tcon_sync RW 0x0 Select synchronization between hsync/vsync and hlast/vlast

0x0: H_VLast - tcon timing generator syn-chronized to hlast, vlast

0x1: H_VSync - tcon timing generator syn-chronized to hsync, vsync where horizontal synchronization is synchronized at the fall-ing edge of hsync





[1:0] ChannelMode RW 0x0 Selects one of tcon operation modes, SIN-GLE, DUAL_INTERLEAVED or DUAL_SPLIT.

in DUAL_INTERLEAVED or DUAL_SPLIT mode, the horizontal parameter of signal generator have to set twice as they are specified in the panel-specification

(panel: 320, tsig_start 0, tsig_stop 320 on DUAL-Mode : tsig_start 0, tsig_stop 640 ... (SplitPosition is automatically adjusted) )

0x0: SINGLE - Single pixel mode. Both channels channel are active at full pixel clock. If bitmap of both panels are the same, both panels are identical

0x1: DUAL_INTERLEAVED - Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives display col-umns with even and 2nd one with odd index.

0x2: DUAL_SPLIT - Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives the left and 2nd one the righ half of the display.





RSDSInvCtrl

Description: Controls inversion of output polarity when connected IO cells operate in RSDS mode



Table 3-944: RSDSInvCtrl Register



[27:16] RSDS_Inv_Dual RW 0x0 Same as RSDS_inv for 2nd channel


[11:0] RSDS_Inv RW 0x0 Inversion vector for 1st channel. For i in [ 0 .. 11 ]; if RSDS_Inv [ i ] == 0 => NON-Inver-sion of RSDS [ i ] else Inversion of RSDS [ i ]



MapBit3_0

Description: Mapping of 24 bit RGB or Timing Generator TSig[5:0] to bit 0 .. 3



Table 3-945: MapBit3_0 Register



[28:24] MapBit3 RW 0x3 map bit[ 3 ] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit3 in [ 0..23 ] => bit[ 3 ] = [ Blue, Green, Red ] [ MapBit3 ]; if MapBit3 in [24 .. 29] bit[ 3 ] in { TSig[0] .. TSig[5] }; If MapBit3 = 31 => bit[ 3 ] = 0 ; if MapBit3= 30 => bit[ 3 ] = 1









MapBit7_4
















MapBit11_8







[28:24] MapBit11 RW 0xB map bit[ 11 ] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit11 in [ 0..23 ] => bit[ 11 ] = [ Blue, Green, Red ] [ MapBit11 ]; if MapBit11 in [24 .. 29] bit[ 11 ] in { TSig[0] .. TSig[5] } ; If MapBit11 = 31 => bit[ 11 ] = 0 ; if MapBit11= 30 => bit[ 11 ] = 1


[20:16] MapBit10 RW 0xA map bit[ 10 ] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit10 in [ 0..23 ] => bit[ 10 ] = [ Blue, Green, Red ] [ MapBit10 ]; if MapBit10 in [24 .. 29] bit[ 10 ] in { TSig[0] .. TSig[5] } ; If MapBit10 = 31 => bit[ 10 ] = 0 ; if MapBit10= 30 => bit[ 10 ] = 1


[12:8] MapBit9 RW 0x9 map bit[ 9 ] from [ Blue, Green, Red ] or TSig[5:0]. if MapBit9 in [ 0..23 ] => bit[ 9 ] = [ Blue, Green, Red ] [ MapBit9 ]; if MapBit9 in [24 .. 29] bit[ 9 ] in { TSig[0] .. TSig[5] }; If MapBit9 = 31 => bit[ 9 ] = 0 ; if MapBit9= 30 => bit[ 9 ] = 1


[4:0] MapBit8 RW 0x8 map bit[ 8 ] from [ Blue, Green, Red ] or TSig[5:0]. if MapBit8 in [ 0..23 ] => bit[ 8 ] = [ Blue, Green, Red ] [ MapBit8 ]; if MapBit8 in [24 .. 29] bit[ 8 ] in { TSig[0] .. TSig[5] }; If MapBit8 = 31 => bit[ 8 ] = 0 ; if MapBit8= 30 => bit[ 8 ] = 1



MapBit15_12







[28:24] MapBit15 RW 0xF map bit[ 15 ] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit15 in [ 0..23 ] => bit[ 15 ] = [ Blue, Green, Red ] [ MapBit15 ]; if MapBit15 in [24 .. 29] bit[ 15 ] in { TSig[0] .. TSig[5] } ; If MapBit15 = 31 => bit[ 15 ] = 0 ; if MapBit15= 30 => bit[ 15 ] = 1


[20:16] MapBit14 RW 0xE map bit[ 14 ] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit14 in [ 0..23 ] => bit[ 14 ] = [ Blue, Green, Red ] [ MapBit14 ]; if MapBit14 in [24 .. 29] bit[ 14 ] in { TSig[0] .. TSig[5] } ; If MapBit14 = 31 => bit[ 14 ] = 0 ; if MapBit14= 30 => bit[ 14 ] = 1


[12:8] MapBit13 RW 0xD map bit[ 13 ] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit13 in [ 0..23 ] => bit[ 13 ] = [ Blue, Green, Red ] [ MapBit13 ]; if MapBit13 in [24 .. 29] bit[ 13 ] in { TSig[0] .. TSig[5] } ; If MapBit13 = 31 => bit[ 13 ] = 0 ; if MapBit13= 30 => bit[ 13 ] = 1


[4:0] MapBit12 RW 0xC map bit[ 12 ] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit12 in [ 0..23 ] => bit[ 12 ] = [ Blue, Green, Red ] [ MapBit12 ]; if MapBit12 in [24 .. 29] bit[ 12 ] in { TSig[0] .. TSig[5] } ; If MapBit12 = 31 => bit[ 12 ] = 0 ; if MapBit12= 30 => bit[ 12 ] = 1



MapBit19_16







[28:24] MapBit19 RW 0x13 map bit[ 19 ] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit19 in [ 0..23 ] => bit[ 19 ] = [ Blue, Green, Red ] [ MapBit19 ]; if MapBit19 in [24 .. 29] bit[ 19 ] in { TSig[0] .. TSig[5] } ; If MapBit19 = 31 => bit[ 19 ] = 0 ; if MapBit19= 30 => bit[ 19 ] = 1









MapBit23_20
















MapBit27_24







[28:24] MapBit27 RW 0x1B map bit[27] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit27 in [ 0..23 ] => bit[27] = [ Blue, Green, Red ] [ MapBit27 ]; if MapBit27 in [24 .. 29] bit[27] in { TSig[0] .. TSig[5] } ; If MapBit27 = 31 => bit[27] = 0 ; if MapBit27= 30 => bit[27] = 1


[20:16] MapBit26 RW 0x1A map bit[26] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit26 in [ 0..23 ] => bit[26] = [ Blue, Green, Red ] [ MapBit26 ]; if MapBit26 in [24 .. 29] bit[26] in { TSig[0] .. TSig[5] } ; If MapBit26 = 31 => bit[26] = 0 ; if MapBit26= 30 => bit[26] = 1


[12:8] MapBit25 RW 0x19 map bit[25] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit25 in [ 0..23 ] => bit[25] = [ Blue, Green, Red ] [ MapBit25 ]; if MapBit25 in [24 .. 29] bit[25] in { TSig[0] .. TSig[5] } ; If MapBit25 = 31 => bit[25] = 0 ; if MapBit25= 30 => bit[25] = 1


[4:0] MapBit24 RW 0x18 map bit[24] from [ Blue, Green, Red ] or TSig[5:0]. If MapBit24 in [ 0..23 ] => bit[24] = [ Blue, Green, Red ] [ MapBit24 ]; if MapBit24 in [24 .. 29] bit[24] in { TSig[0] .. TSig[5] } ; If MapBit24 = 31 => bit[24] = 0 ; if MapBit24= 30 => bit[24] = 1



MapBit3_0_Dual

Description: Same as MapBit3_0 for 2nd channel



Table 3-952: MapBit3_0_Dual Register



[28:24] MapBit3_Dual RW 0x3 Same as MapBit3 for 2nd channel









MapBit7_4_Dual
















MapBit11_8_Dual







[28:24] MapBit11_Dual RW 0xB Same as MapBit11 for 2nd channel


[20:16] MapBit10_Dual RW 0xA Same as MapBit10 for 2nd channel







MapBit15_12_Dual







[28:24] MapBit15_Dual RW 0xF Same as MapBit15 for 2nd channel


[20:16] MapBit14_Dual RW 0xE Same as MapBit14 for 2nd channel


[12:8] MapBit13_Dual RW 0xD Same as MapBit13 for 2nd channel


[4:0] MapBit12_Dual RW 0xC Same as MapBit12 for 2nd channel



MapBit19_16_Dual
















MapBit23_20_Dual
















MapBit27_24_Dual







[28:24] MapBit27_Dual RW 0x1B Same as MapBit27 for 2nd channel


[20:16] MapBit26_Dual RW 0x1A Same as MapBit26 for 2nd channel







SPG0PosOn

Description: Sync pulse generator 0, 'Switch on' position



Table 3-959: SPG0PosOn Register


[31] SPGPSON_TOGGLE0 RW 0x0 Toggle enable: 0b=disable, 1b=enable

[30:16] SPGPSON_X0 RW 0x148 X scan position


[14:0] SPGPSON_Y0 RW 0x0 Y scan position



SPG0MaskOn

Description: The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0



Table 3-960: SPG0MaskOn Register



[30:0] SPGMKON0 RW 0xFFFF Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching



SPG0PosOff

Description: Sync pulse generator 0, 'Switch off' position



Table 3-961: SPG0PosOff Register


[31] SPGPSOFF_TOGGLE0 RW 0x0 Toggle enable: 0b=disable, 1b=enable

[30:16] SPGPSOFF_X0 RW 0x168 X scan position


[14:0] SPGPSOFF_Y0 RW 0x0 Y scan position



SPG0MaskOff

Description: The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0



Table 3-962: SPG0MaskOff Register



[30:0] SPGMKOFF0 RW 0xFFFF Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching



SPG1PosOn









[14:0] SPGPSON_Y1 RW 0xF3 Y scan position



SPG1MaskOn







[30:0] SPGMKON1 RW 0x7FFF0000

mask bits (1= do not include this bit into position matching)



SPG1PosOff









[14:0] SPGPSOFF_Y1 RW 0xF7 Y scan position



SPG1MaskOff







[30:0] SPGMKOFF1 RW 0x7FFF0000

Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching



SPG2PosOn












SPG2MaskOn







[30:0] SPGMKON2 RW 0xFFFF Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching



SPG2PosOff












SPG2MaskOff







[30:0] SPGMKOFF2 RW 0xFFFF Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching



SPG3PosOn












SPG3MaskOn







[30:0] SPGMKON3 RW 0x7FFF0000




SPG3PosOff









[14:0] SPGPSOFF_Y3 RW 0xF0 Y scan position



SPG3MaskOff







[30:0] SPGMKOFF3 RW 0x7FFF0000




SPG4PosOn












SPG4MaskOn







[30:0] SPGMKON4 RW 0x0 Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching



SPG4PosOff












SPG4MaskOff







[30:0] SPGMKOFF4 RW 0x0 Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching



SPG5PosOn












SPG5MaskOn










SPG5PosOff



Instance no 0: 0x00034CA0









SPG5MaskOff










SPG6PosOn












SPG6MaskOn



Instance no 0: 0x00034CAC







SPG6PosOff



Instance no 0: 0x00034CB0









SPG6MaskOff










SPG7PosOn












SPG7MaskOn



Instance no 0: 0x00034CBC







SPG7PosOff



Instance no 0: 0x00034CC0









SPG7MaskOff










SPG8PosOn












SPG8MaskOn



Instance no 0: 0x00034CCC







SPG8PosOff



Instance no 0: 0x00034CD0









SPG8MaskOff










SPG9PosOn












SPG9MaskOn



Instance no 0: 0x00034CDC







SPG9PosOff



Instance no 0: 0x00034CE0









SPG9MaskOff










SPG10PosOn






[31] SPGPSON_TOGGLE10 RW 0x0 toggle enable: 0b=disable, 1b=enable






SPG10MaskOn

Description: The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG10


Instance no 0: 0x00034CEC







SPG10PosOff



Instance no 0: 0x00034CF0



[31] SPGPSOFF_TOGGLE10 RW 0x0 toggle enable: 0b=disable, 1b=enable






SPG10MaskOff

Description: The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG10









SPG11PosOn






[31] SPGPSON_TOGGLE11 RW 0x0 toggle enable: 0b=disable, 1b=enable






SPG11MaskOn

Description: The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG11


Instance no 0: 0x00034CFC







SPG11PosOff






[31] SPGPSOFF_TOGGLE11 RW 0x0 toggle enable: 0b=disable, 1b=enable






SPG11MaskOff

Description: The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG11









SMx0Sigs

Description: Selection of input signals of sync mixer



Table 3-1007: SMx0Sigs Register



[14:12] SMX0SIGS_S4 RW 0x0 select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5







SMx0FctTable

Description: The sync mixer output is the result of the function tablea=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of syncmixer input selection


Instance no 0: 0x00034D0C

Table 3-1008: SMx0FctTable Register


[31:0] SMXFCT0 RW 0x2 Sync mixer 0 function table



SMx1Sigs














SMx1FctTable









SMx2Sigs














SMx2FctTable

Description: The sync mixer output is the result of the function tablea=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of syncmixer input selection








SMx3Sigs














SMx3FctTable









SMx4Sigs














SMx4FctTable









SMx5Sigs














SMx5FctTable









SMx6Sigs














SMx6FctTable









SMx7Sigs














SMx7FctTable









SMx8Sigs














SMx8FctTable









SMx9Sigs














SMx9FctTable









SMx10Sigs














SMx10FctTable









SMx11Sigs














SMx11FctTable









Iris-MVL - Sig Registers

SigLockUnlock

Description: Register to lock or unlock write access to registers of this unit with lock property


Instance no 0: 0x00035000Instance no 1: 0x00035400Instance no 2: 0x00035800Instance no 3: 0x00035C00

Table 3-1031: SigLockUnlock Register


[31:0] LockUnlock W 0x0 Write lock or unlock key to this field in order to change lock status

Writing the lock key when unit is locked or the unlock key when the unit is unlocked or an invalid key value generates an error respond



SigLockStatus

Description: Lock Status for write access to registers of this unit with lock property



Table 3-1032: SigLockStatus Register



[0] LockStatus R 0x1 Current lock status

0: Unlocked -

1: Locked -



SigEnable

Description: Turn on and stop the signature unit.



Table 3-1033: SigEnable Register



[0] SigEN RW 0x0 Turn Signature on/off

0x0: DISABLE - No signature generation or Stop the signature unit whilst measurement (signatures will have, except configuration setting, the reset values. No interrupts will be generated)

0x1: ENABLE - Enable Signature unit



StaticControl

Description: Signature configuration and Static control register Start meassurement by writing '1' to SoftwareKick.Kick


Instance no 0: 0x0003500CInstance no 1: 0x0003540CInstance no 2: 0x0003580CInstance no 3: 0x00035C0C




[29] ShdLdSel RW 0x0 selection of shadow load token

0x0: SW_Token - ShdTokGen only, update with Load_Shadow.ShdTokGen

0x1: Command - ShdTokGen or shadow load token on input stream

[28] ShdEn RW 0x0 Enable to load shadow register

0: write through; 1: shadowed

Load shadow by Load_Shadow.ShdTok-Gen or by token on input stream (see ShdLdSel)


[19] EnSkipWin RW 0x0 ENABLE/DISABLE the skip window, where the pixels are masked

0x0: DISABLE - ignore skip window

0x1: ENABLE - exclude all pixels within skip window for signature computation

[18] EnEvalWin RW 0x0 the signatures are only computed for all pixels within Evaluation window. If DIS-ABLE, no signature generation

0x0: DISABLE - ignore all pixels. No signa-ture generation

0x1: ENABLE - include all pixels within evaluation window for signature computa-tion

[17] EnSUM RW 0x0 Enable/Disable the generation of Summa-tion of color values

0x0: DISABLE - No generation of signa-ture type Summation (Summation of color values)

0x1: ENABLE - Enable for Summation-sig-nature generation (Summation of color val-ues)



[16] EnCRC RW 0x0 Enable/Disable the generation of CRC-sig-nature

0x0: DISABLE - No generation of CRC-sig-nature

0x1: ENABLE - Enable for CRC-signature generation


[9] AlphaInv RW 0x0 Inversion of alpha of Input Pixel

0x0: NON_INV - Non-Inverting corre-sponding Alpha

0x1: INV - Inverting corresponding Alpha

[8] AlphaMask RW 0x0 Enable/Disable for masking of alpha of Input Pixel

0x0: DISABLE - ignore alpha of rgb into signature calculation

0x1: ENABLE - include alpha of rgb into signature calculation


[5] ObjectPanic RW 0x0 Influence on the panic output

0x0: OBJECT - On signature violation, panic_object is active within programmed Evaluation Window

0x1: DISPLAY - On signature violation, Panic_frame is active for the whole frame (Frame based)

[4] EnPanic RW 0x0 Enable/Disable panic function

0x0: DISABLE - DISABLE panic function

0x1: ENABLE - ENABLE panic function


[0] SigMode RW 0x0 Signature operational mode

0x0: ONE_TIME - Generation of signature for one frame only. ErrorThresh-old.ErrThres has no effect to signature evaluation. Changing CYCLIC to ONE_TIME , a single generation is exe-cuted with the next coming frame. Signa-ture generation is then stopped afterwards

0x1: CYCLIC - Generation of signature on every frame





ThrSumRed

Description: Threshold on Red channel for Summation Signature



Table 3-1035: ThrSumRed Register


[31:0] ThrSumR RW 0x0 Threshold on Red channel for Summation Signature (maximal tolerance value on the difference of Summation Signature to Ref-erence)



ThrSumGreen

Description: Threshold on Green channel for Summation Signature



Table 3-1036: ThrSumGreen Register


[31:0] ThrSumG RW 0x0 Threshold on Green channel for Summa-tion Signature (maximal tolerance value on the difference of Summation Signature to Reference)



ThrSumBlue

Description: Threshold on Blue channel for Summation Signature



Table 3-1037: ThrSumBlue Register


[31:0] ThrSumB RW 0x0 Threshold on Blue channel for Summation Signature (maximal tolerance value on the difference of Summation Signature to Ref-erence)



ErrorThreshold

Description: Number of tolerated signature violation before activating interrupt and setting Status



Table 3-1038: ErrorThreshold Register



[23:16] ErrThresReset RW 0x8 Number of consecutive "no violation" frames causes to reset the violation coun-ter

0h=no reset, 1h=1 .., 5h : reset the violation counter if no violation detected during the 5 consecutive measurements , ..., FFh=255


[7:0] ErrThres RW 0x0 Number of tolerating frames in case of sig-nature violation before setting the Panic-Flag, stastus and generating error interrupt

0h = non tolerate violation (interrupt_error generated on every signature violation)

1h = tolerates 1 violation; 2h = tolerates 2 violations, ..., FFh=255



EvalUpperLeft

Description: UpperLeft coordinate of Evaluation Window



Table 3-1039: EvalUpperLeft Register



[29:16] YEvalUpperLeft RWS 0x0 Vertical UpperLeft corner coordinate of evaluation window


[13:0] XEvalUpperLeft RWS 0x0 Horizontal UpperLeft corner coordinate of evaluation window



EvalLowerRight

Description: LowerRight coordinate of Evaluation Window



Table 3-1040: EvalLowerRight Register



[29:16] YEvalLowerRight RWS 0x0 Vertical LowerRight corner coordinate of evaluation window


[13:0] XEvalLowerRight RWS 0x0 Horizontal LowerRight corner coordinate of evaluation window



SkipUpperLeft

Description: UpperLeft coordinate of Skip Window



Table 3-1041: SkipUpperLeft Register



[29:16] YSkipUpperLeft RWS 0x0 Vertical UpperLeft corner coordinate of Skip window


[13:0] XSkipUpperLeft RWS 0x0 Horizontal UpperLeft corner coordinate of Skip window



SkipLowerRight

Description: LowerRight coordinate of Skip Window



Table 3-1042: SkipLowerRight Register



[29:16] YSkipLowerRight RWS 0x0 Vertical LowerRight corner coordinate of Skip window


[13:0] XSkipLowerRight RWS 0x0 Horizontal LowerRight corner coordinate of Skip window



SigCRCRefRed

Description: Reference Signature of Type CRC on channel Red



Table 3-1043: SigCRCRefRed Register


[31:0] SigCRCRefR RWS 0x0 Reference Signature of Type CRC on channel Red



SigCRCRefGreen

Description: Reference Signature of Type CRC on channel Green



Table 3-1044: SigCRCRefGreen Register


[31:0] SigCRCRefG RWS 0x0 Reference Signature of Type CRC on channel Green



SigCRCRefBlue

Description: Reference Signature of Type CRC on channel Blue



Table 3-1045: SigCRCRefBlue Register


[31:0] SigCRCRefB RWS 0x0 Reference Signature of Type CRC on channel Blue



SigSumRefRed

Description: Reference Signature of Type Summation (color summation) on channel Red



Table 3-1046: SigSumRefRed Register


[31:0] SigSumRefR RWS 0x0 Reference Signature of Type Summation (color summation) on channel Red



SigSumRefGreen

Description: Reference Signature of Type Summation (color summation) on channel Green



Table 3-1047: SigSumRefGreen Register


[31:0] SigSumRefG RWS 0x0 Reference Signature of Type Summation (color summation) on channel Green



SigSumRefBlue

Description: Reference Signature of Type Summation (color summation) on channel Blue



Table 3-1048: SigSumRefBlue Register


[31:0] SigSumRefB RWS 0x0 Reference Signature of Type Summation (color summation) on channel Blue



Load_Shadow

Description: trigger to load from shadowed registers



Table 3-1049: Load_Shadow Register



[0] ShdTokGen R0W1

0x0 write a '1' to load the configuration from shadowed registers



SoftwareKick

Description: Kick to start signature generation



Table 3-1050: SoftwareKick Register



[0] Kick R0W1

0x0 write a '1' to start signature generation



PanicFlag

Description: Monitor the signature violation. Once this Flag is set, it remains 1'active until it's written with'1'. Pls note, the setting of PanicFlag depends on ErrorThreshold and StaticControl.EnPanic= ENABLE



Table 3-1051: PanicFlag Register



[0] PanicFlag RW1C

0x0 PanicFlag is set in case of "signature viola-tion and StaticControl.EnPanic = ENABLE".

0x0: NORMAL - No signature violation

0x1: PANIC - signature violation



Status

Description: Signature Status (update after every signature generation)






[18] StsSumB R 0x0 Status on Evaluation of Summation on blue channel

0x0: NO_VIOLATION - measurement val-ues and references are equal.

0x1: VIOLATION - measurement values and references are not equal .

[17] StsSumG R 0x0 Status on Evaluation of Summation on green channel



[16] StsSumR R 0x0 Status on Evaluation of Summation on red channel




[10] StsCRCB R 0x0 Status on Evaluation of CRC on blue chan-nel



[9] StsCRCG R 0x0 Status on Evaluation of CRC on green channel



[8] StsCRCR R 0x0 Status on Evaluation of CRC on red chan-nel






[5] SigError R 0x0 status of the signature evaluation (evalua-tion of StsCRCR, StsCRCG, StsCRCB, StsSumR, StsSumG, StsSumB and ErrorThreshold.ErrThres)

0x0: NO_VIOLATION - no violation.

0x1: VIOLATION - violation (the amount of signature violation is greater than ErrorThreshold.ErrThres)

[4] Valid R 0x0 qualifying the availability of status

0x0: NOT_VALID - started signature gen-eration is not finished

0x1: VALID - result of newest computed signature is available


[1] Active R 0x0 Status flag of signature unit

0x0: IDLE - No signature generation

0x1: ACTIVE - Signature generation in progress

[0] Pending R 0x0 indicate shadow update

0x0: LOADED - shadows are loaded into working registers (in correlation to Soft-wareKick.Kick or shadow load by com-mand)

0x1: PENDING - Once asserting Software-Kick.Kick or shadow load by command, PENDING is set until shadowed registers are loaded into working registers





SigErrCount

Description: Number of frames with signature errors



Table 3-1053: SigErrCount Register



[11:0] Sig_err_count R 0x0 Number of frames that cause signature vio-lation. Each SoftwareKick.Kick or SigEN=0 set Sig_err_count to 0



SigCRCRed

Description: Result of CRC Signature for channel Red (update after every signature generation)



Table 3-1054: SigCRCRed Register


[31:0] SigCRCRed R 0x0 newest calculated CRC Signature for chan-nel red



SigCRCGreen

Description: Result of CRC Signature for channel Green (update after every signature generation)



Table 3-1055: SigCRCGreen Register


[31:0] SigCRCGreen R 0x0 newest calculated CRC Signature for chan-nel green



SigCRCBlue

Description: Result of CRC Signature for channel Blue (update after every signature generation)



Table 3-1056: SigCRCBlue Register


[31:0] SigCRCBlue R 0x0 newest calculated CRC Signature for chan-nel blue



SigSumRed

Description: Result of Summation Signature for channel Red (update after every signature generation)



Table 3-1057: SigSumRed Register


[31:0] SigSumRed R 0x0 newest calculated "summation of color val-ues" Signature for channel red



SigSumGreen

Description: Result of Summation Signature for channel Green (update after every signature generation)



Table 3-1058: SigSumGreen Register


[31:0] SigSumGreen R 0x0 newest calculated "summation of color val-ues" Signature for channel green



SigSumBlue

Description: Result of Summation Signature for channel Blue (update after every signature generation)



Table 3-1059: SigSumBlue Register


[31:0] SigSumBlue R 0x0 newest calculated "summation of color val-ues" Signature for channel blue




3.10 Stepper Motor Controller Registers

In this section, the ‘Register Overview’ table summarizes all Stepper Motor Controller registers,including base address of the module and name, description, and the absolute address of each register,which are then described separately in the following tables.



3.10.1 Stepper Motor Controller Core Register Overview


Base Address(es)

Instance no 0: BASEADDR0="00080000"Instance no 1: BASEADDR1="00080400"Instance no 2: BASEADDR2="00080800"Instance no 3: BASEADDR3="00080C00"Instance no 4: BASEADDR4="00081000"Instance no 5: BASEADDR5="00081400"


BASEADDRx + 0x0000 SMCn_PWC PWM Control Register


BASEADDRx + 0x0002 SMCn_PWCS PWM Control Set Register


BASEADDRx + 0x0004 SMCn_PWCC PWM Control Clear Register


BASEADDRx + 0x0006 SMCn_PWC1 PWM1 Compare Registers

BASEADDRx + 0x0008 SMCn_PWC2 PWM2 Compare Registers

BASEADDRx + 0x000A SMCn_PWS PWM Selection Register

BASEADDRx + 0x000C SMCn_PWSS PWM Selection Set Register

BASEADDRx + 0x000E SMCn_PTRGDL SMC-Trigger Delay Register

BASEADDRx + 0x000F Reserved Do not modify




SMCn_PWC

Description: PWM Control Register


Instance no 0: 0x00080000Instance no 1: 0x00080400Instance no 2: 0x00080800Instance no 3: 0x00080C00Instance no 4: 0x00081000Instance no 5: 0x00081400

Table 3-1061: SMCn_PWC Register



[6:4] P RW 0x0 Clock Prescalar bits

The Clock Prescaler (P[2:0]) bits are used to set the clock prescaler value for the SMC PWM Pulse Generator.

Note: Configuring the Clock Prescaler should be done while the counting opera-tion is disabled (SMCn_PWC:CE = `0').

[3] CE RW 0x0 Count Enable bit

The Count Enable (CE) bit enables opera-tion of the SMC module (PWM Pulse Gen-eration and output control).

This bit can also set to '1' by SMCn_PWCS:CES bit and cleared by SMCn_PWCC:CEC bit.

This bit can also be set to '1' by using the SMC PWM Pulse Generator. If theSMC PWM Pulse Generator is used, this bit must be set to '0' before.

0: When the CE bit is cleared to '0' during operation of the SMC PWM Pulse Genera-tor, the generator stops operation

1: The SMC PWM Pulse Generator starts operating. The PWM2 Pulse Generator starts one SMC clock cycle after the PWM1 Pulse Generator starts, in order to reduce the switching noise generated by the output driver.

[2] SC RW 0x0 Switching bit

The 8-/10- bits switching (SC) bit enables SMC PWM Pulse Generator to operate at 8-bit or 10-bit resolution.

0: The SMC PWM Pulse Generator oper-ates at 8-bit resolution

1: The SMC PWM Pulse Generator oper-ates at 10-bit resolution




SMCn_PWCS

Description: PWM Control Set Register



Table 3-1062: SMCn_PWCS Register



[3] CES R0W1

0x0 Set bit for Count Enable

The Set bit for Count Enable (CES) bit is used to set the value of SMCn_PWC:CE bit. Reading this bit returns to '0'.

0: No effect

1: Sets the SMCn_PWC:CE bit




SMCn_PWCC

Description: PWM Control Clear Register



Table 3-1063: SMCn_PWCC Register



[3] CEC R0W1

0x0 Clear bit for Count Enable

The Clear bit for Count Enable (CEC) bit is used to clear the value of SMCn_PWC:CE bit. Reading this bit returns to '0'.

0: No effect

1: Clears the SMCn_PWC:CE




SMCn_PWC1

Description: PWM1 Compare Registers



Table 3-1064: SMCn_PWC1 Register



[9:0] D RW X PWM Compare Value

The PWM Compare Value (D) bits are used to set the PWM duty cycle.

The PWM1 and PWM2 Compare Registers can always be accessed, but the changed value is reflected in the pulse width only at the end of the current PWM cycle after '1' is set to the SMCn_PWS:BS bit.

When '0' is set to SMCn_PWC:SC bit, PWM performs 8-bit operation and D[9:8] bits are undefined value.

PWM1and PWM2 Compare registers must be written 16-bit wide.



SMCn_PWC2

Description: PWM2 Compare Registers



Table 3-1065: SMCn_PWC2 Register










SMCn_PWS

Description: PWM Selection Register


Instance no 0: 0x0008000AInstance no 1: 0x0008040AInstance no 2: 0x0008080AInstance no 3: 0x00080C0AInstance no 4: 0x0008100AInstance no 5: 0x0008140A

Table 3-1066: SMCn_PWS Register



[14] BS RW 0x0 Output Update

The Output Update (BS) bit is used to transfer the current configured output selection and PWM compare values to the outputs synchronously. As long as SMCn_PWS:BS is '0', changes made to the two Compare Registers (SMCn_PWC1/2) and the PWM Selection Register (SMCn_PWS) are not reflected in the out-put signal. This bit can also be set by SMCn_PWSS:BSS bit. It is cleared to `0' automatically at the beginning of the next PWM cycle.

0: When `0' is set to the BS bit by software, at the same time of an automatic clear, the BS bit is set to `0'. Also the SMC PWM Pulse Generator and the selector do not load the values of the registers at the end of the current PWM cycle

1: When `1' is set to the BS bit, the SMC PWM Pulse Generator and the selector load the values of the registers at the end of the current PWM cycle

When `1' is set to the BS bit by software, at the same time of an automatic clear, the BS bit is set to `1' (no change is made to the BS bit) for this PWM cycle and is automati-cally cleared in the next PWM cycle.

[13:11] P2 RW 0x0 Plus Output 2 Selection bits

The Plus Output 2 selection bits (P2[2:0]) are used to select the output signal SMC2Pn

[10:8] M2 RW 0x0 Minus Output 2 Selection bits

The Minus Output 2 selection bits (M2[2:0]) are used to select the output signal SMC2Mn







The Minus Output 1 selection bits (M1[2:0]) bits are used to select the output signal SMC1Mn.

Table 3-1066: SMCn_PWS Register




SMCn_PWSS

Description: PWM Selection Set Register


Instance no 0: 0x0008000CInstance no 1: 0x0008040CInstance no 2: 0x0008080CInstance no 3: 0x00080C0CInstance no 4: 0x0008100CInstance no 5: 0x0008140C

Table 3-1067: SMCn_PWSS Register



[14] BSS R0W1

0x0 Set bit for the SMCn_PWS:BS

The Set bit for the SMCn_PWS:BS bit (BSS) bit is used to set the value of SMCn_PWS:BS bit. Reading this bit returns '0'.

0: Has no effect

1: Sets the SMCn_PWS:BS bit to '1'




SMCn_PTRGDL

Description: SMC-Trigger Delay Register


Instance no 0: 0x0008000EInstance no 1: 0x0008040EInstance no 2: 0x0008080EInstance no 3: 0x00080C0EInstance no 4: 0x0008100EInstance no 5: 0x0008140E

Table 3-1068: SMCn_PTRGDL Register


[7:0] D RW 0x0 Trigger Delay

The Trigger Delay (D) bits are used to con-figure a delay of the trigger input from 0 to 255 clock cycles of SMC clock to start the PWM operation.This trigger is generated by the PWM Trigger generator.

These bits delay the trigger input according to the following settings:

00000000: No delay

00000001 to 11111111: 1 to 255 clock cycles delay




3.10.2 Stepper Motor Controller Trigger Register Overview




BASEADDR + 0x0000 SMCTGg_PTRGS SMC-Trigger Select Register

BASEADDR + 0x0002 SMCTGg_PTRG SMC-Trigger Register


BASEADDR + 0x0004 SMCTGg_SHD1_SMC0 Shadow register access for Coil1 of SMC0



BASEADDR + 0x000A SMCTGg_SHD2_SMC1 Shadow register access for Coil2 of SMC1

BASEADDR + 0x000C SMCTGg_SHD1_SMC2 Shadow register access for Coil1 of SMC2

BASEADDR + 0x000E SMCTGg_SHD2_SMC2 Shadow register access for Coil2 of SMC2






BASEADDR + 0x001A SMCTGg_SHD2_SMC5 Shadow register access for Coil2 of SMC5


SMCTGg_PTRGS

Description: SMC-Trigger Select Register



Table 3-1070: SMCTGg_PTRGS Register



[13] S2[5] RW 0x0 Trigger Enable for operation of SMC5

The Trigger Enable for operation of SMC5 (S2[5]) bit selects SMC5 for trigger group 2 (triggered by SMCTGg_PTRG:TR2).

0: SMC5 is not triggered by SMCTGn_PTRG:TR2

1: SMC5 is triggered by SMCTGn_PTRG:TR2





















1 : SMC0 is triggered by SMCTGn_PTRG:TR2

0 : SMC0 is not triggered by SMCTGn_PTRG:TR2























The Trigger Enable for operation of SMC1 (S1[1]) bit selects SMC1 for trigger group 1 (triggered by SMCTGg_PTRG:TR1)











SMCTGg_PTRG

Description: SMC-Trigger Register



Table 3-1071: SMCTGg_PTRG Register



[1] TR2 R0W1

0x0 SMC Trigger 2

The SMC Trigger 2 bit triggers the second group of Stepper Motor Controllers. Which SMCn should be triggered must be config-ured in SMCTGg_PTRGS:S2n. The trigger signal will start the delay counters (if enabled in SMCn_PTRGDLn). If the delay is elapsed (or disabled), the Count Enable (CE) bit of the selected SMCn will be set and the operation will start (PWM genera-tion and output control).

0: No effect

1: Triggers SMCn via SMCn_PTRGDL reg-ister

This bit is reset to '0' after one clock cycle automatically

[0] TR1 R0W1

0x0 SMC Trigger 1

The SMC Trigger 1 bit triggers the first group of Stepper Motor Controllers. Which SMCn should be triggered must be config-ured in SMCTGg_PTRGS:S2n. The trigger signal will start the delay counters (if enabled in SMCn_PTRGDLn). If the delay is elapsed (or disabled), the Count Enable (CE) bit of the selected SMCn will be set and the operation will start (PWM genera-tion and output control).

0: No effect

1: Triggers SMCn via SMCn_PTRGDL reg-ister

This bit is reset to '0' after one clock cycle automatically



SMCTGg_SHD1_SMC0

Description: Shadow register access for Coil1 of SMC0



Table 3-1072: SMCTGg_SHD1_SMC0 Register













SMCTGg_SHD2_SMC0

Description: Shadow register access for Coil2 of SMC0Writing to this register sets the Output Update (BS) bit.
















SMCTGg_SHD1_SMC1

















SMCTGg_SHD2_SMC1



Instance no 0: 0x00081C0A














SMCTGg_SHD1_SMC2

















SMCTGg_SHD2_SMC2



Instance no 0: 0x00081C0E














SMCTGg_SHD1_SMC3

















SMCTGg_SHD2_SMC3

















SMCTGg_SHD1_SMC4

















SMCTGg_SHD2_SMC4

















SMCTGg_SHD1_SMC5

















SMCTGg_SHD2_SMC5



Instance no 0: 0x00081C1A















3.11 PWM-PPG Registers

In this section, the ‘Register Overview’ table summarizes all PWM-PPG registers, including baseaddress of the module and name, description, and the absolute address of each register, which are thendescribed separately in the following tables.



3.11.1 Programmable Pulse Generator Core Register Overview

Every individual PPG has one set of core unit register.


Base Address(es)

Instance no 0: BASEADDR0="00088000"Instance no 1: BASEADDR1="00088400"Instance no 2: BASEADDR2="00088800"Instance no 3: BASEADDR3="00088C00"Instance no 4: BASEADDR4="0008A000"Instance no 5: BASEADDR5="0008A400"Instance no 6: BASEADDR6="0008A800"Instance no 7: BASEADDR7="0008AC00"Instance no 8: BASEADDR8="0008C000"Instance no 9: BASEADDR9="0008C400"Instance no 10: BASEADDR10="0008C800"Instance no 11: BASEADDR11="0008CC00"Instance no 12: BASEADDR12="0008E000"Instance no 13: BASEADDR13="0008E400"Instance no 14: BASEADDR14="0008E800"Instance no 15: BASEADDR15="0008EC00"


BASEADDRx + 0x0000 PPGn_PCN PPG Control Status Register

BASEADDRx + 0x0002 PPGn_IRQCLR Interrupt Flag Clear Register

BASEADDRx + 0x0003 PPGn_SWTRIG Software Trigger Activation Register

BASEADDRx + 0x0004 PPGn_OE Output Enable Register

BASEADDRx + 0x0005 PPGn_CNTEN Timer Enable Operation Register

BASEADDRx + 0x0006 PPGn_OPTMSK Output Mask and Polarity Selection Register

BASEADDRx + 0x0007 PPGn_RMPCFG Ramp Configuration Register

BASEADDRx + 0x0008 PPGn_STRD Start Delay Mode Register

BASEADDRx + 0x0009 PPGn_TRIGCLR PPG Trigger Clear Flag Register

BASEADDRx + 0x000A PPGn_EPCN1 Extended PPG Control Status Register 1

BASEADDRx + 0x000C PPGn_EPCN2 Extended PPG Control Status Register 2

BASEADDRx + 0x000E PPGn_GCN1 General Control Register 1

BASEADDRx + 0x000F PPGn_GCN3 General Control Register 3

BASEADDRx + 0x0010 PPGn_GCN4 General Control Register 4

BASEADDRx + 0x0011 PPGn_GCN5 General Control Register 5

BASEADDRx + 0x0012 PPGn_PCSR PPG Cycle Setting Register

BASEADDRx + 0x0014 PPGn_PDUT PPG Duty Setting Register

BASEADDRx + 0x0016 PPGn_PTMR PPG Timer Register

BASEADDRx + 0x0018 PPGn_PSDR PPG Start Delay Register

BASEADDRx + 0x001A PPGn_PTPC PPG Timing Point Capture Register

BASEADDRx + 0x001C PPGn_PEDR PPG End Duty Register

BASEADDRx + 0x001E PPGn_DMACFG PPG DMA Configuration Register

BASEADDRx + 0x001F Reserved Do not modify


PPGn_PCN

Description: PPG Control Status Register


Instance no 0: 0x00088000Instance no 1: 0x00088400Instance no 2: 0x00088800Instance no 3: 0x00088C00Instance no 4: 0x0008A000Instance no 5: 0x0008A400Instance no 6: 0x0008A800Instance no 7: 0x0008AC00Instance no 8: 0x0008C000Instance no 9: 0x0008C400Instance no 10: 0x0008C800Instance no 11: 0x0008CC00Instance no 12: 0x0008E000Instance no 13: 0x0008E400Instance no 14: 0x0008E800Instance no 15: 0x0008EC00

Table 3-1085: PPGn_PCN Register



[13] MDSE RW 0x0 Mode Selection

0: PWM operation

1: One-shot operation

When the Mode Selection bit is set to '0', a PWM operation is enabled to generate pulses in sequence.

When the Mode Selection bit is set to '1', pulse output takes place only once.

[12] RTRG RW 0x0 Restart Enable

0: Disable restart

1: Enable restart

When the Restart Enable bit is set to '1', a trigger (software or internal or external) will restart the PPG operation (depending on the configuration of the triggers).

[11:10] CKS RW 0x0 Counter Clock Selection

CKS[1:0] Down Counter Count Clock Selection.

00: Clock selected by CKSEL

01: Clock selected by CKSEL divided by 4






[8] MOD RW 0x0 PPG 16-bit or 8-bit Operation Mode

0: 16-bit mode

1: 8-bit mode

When the MOD bit is set to '0', a PWM out-put signal is defined with 16-bit resolution.

When the MOD bit is set to '1', 8-bit resolu-tion is used for PWM output definition.

[7:6] EGS RW 0x0 Trigger input edge selection

EGS[1:0] Selected Edge

00: No edge selected, triggering of PPG only possible by PPGn_SWTRIG:STRG

01: Rising edge

10: Falling edge

11: Both edges (rising and falling edge)

[5] IREN RW 0x0 Interrupt Request Enable

IREN Operation

0: Disable interrupt requests

1: Enable interrupt requests

[4] IRQF R 0x0 Interrupt Request Flag

IRQF

0: No interrupt request

1: Interrupt request

[3:1] IRS RW 0x0 Interrupt cause selection

The bits IRS[2:0] select the operation in which to generate an interrupt request

IRS[2:0] selection

000: Software trigger or external trigger input

001: Counter borrow (16-bit or both 8-bit parts if PPGn_PCN:MOD = 1)

010: The counter matches the duty value (16-bit or both 8-bit parts if PPGn_PCN:MOD = 1)

011: Counter borrow or the counter equals the duty value (16-bit or both 8-bit parts if PPGn_PCN:MOD = 1)

100: Timing point capture (16-bit or both 8-bit parts if PPGn_PCN:MOD = 1)

101: End duty match (16-bit or both 8-bit parts if PPGn_PCN:MOD = 1)

Others: Reserved


Table 3-1085: PPGn_PCN Register




PPGn_IRQCLR

Description: Interrupt Flag Clear Register



Table 3-1086: PPGn_IRQCLR Register



[0] IRQCLR R0W1

0x0 Interrupt Request Flag clear bit

0: No effect

1: Clears PPGn_PCN:IRQF flag

Reading this bit always returns 0.



PPGn_SWTRIG

Description: Software Trigger Activation Register



Table 3-1087: PPGn_SWTRIG Register



[0] STGR R0W1

0x0 Software trigger

0: The operation is unaffected by writing '0' (The read value is always '0')

1: Software trigger activation

When the Software Trigger bit is set to '1', a software trigger is generated to activate the PPG separately from the generation of an internal or external trigger (EN bit, reload timer output, ETRG input).

This trigger is independent from setting of the edge selection bits PPGn_PCN:EGS1 and PPGn_PCN:EGS0.



PPGn_OE

Description: Output Enable Register



Table 3-1088: PPGn_OE Register



[1] OE2 RW 0x0 PPGB Output Enable

0: Output disabled

1: Output enabled

In 8-bit mode operation (PPGn_PCN:MOD = 1) the bit enables outputting of the PPGB signal (8-bit resolution PWM signal config-ured by higher 8-bit register parts).

In 16-bit operation mode (PPGn_PCN:MOD = 0) OE2 control bit can be set to '1', in order to generate 16-bit PPG signal also on PPGB output pin.

If additionally PPGn_OPTMSK:OSEL2 bit is set to '1' 16-bit PPG signal with inverted polarity is sent on PPGB output pin.

[0] OE RW 0x0 PPGA Output Enable

0: Output disabled

1: Output enabled

In 8-bit mode operation (PPGn_PCN:MOD = 1) the bit enables outputting of the PPGA signal (8-bit resolution PWM signal config-ured by lower 8-bit register parts).

In 16-bit operation mode (PPGn_PCN:MOD = 0) OE control bit is used to enable output of 16-bit PWMsignal on pin PPGA.



PPGn_CNTEN

Description: Timer Enable Operation Register



Table 3-1089: PPGn_CNTEN Register



[0] CNTE RW 0x0 Count Enable

0: Stop

1: Operation

This bit enables the operation of PPG.



PPGn_OPTMSK

Description: Output Mask and Polarity Selection Register



Table 3-1090: PPGn_OPTMSK Register



[2] PGMS RW 0x0 PPG Output Mask Selection

0: No output mask

1: Output mask

When the PPG Output Mask Selection bit is set to '1', the PPG output can be clamped at L or H regardless of the mode, cycle and duty settings.

The output level can be specified using the Output Polarity Specification bit (PPGn_OPTMSK:OSEL/OSEL2).

PPGn_OPTMSK:OSEL/OSEL2 = 0: output L level on PPGA/PPGB

PPGn_OPTMSK:OSEL/OSEL2 = 1: output H level on PPGA/PPGB

[1] OSEL2 RW 0x0 PPGB Output Polarity Specification (high 8-bit part)

0: PPGB output signal has normal polarity

1: PPGB output signal has inverted polarity

In 16-bit operation mode (PPGn_PCN:MOD = 0) if OE2 control bit is set to '1', the 16-bit PPG signal is also gen-erated on PPGB output pin.

If additionally OSEL2 bit is set to '1', 16-bit PPG signal with inverted polarity is sent on PPGB output pin.



[0] OSEL RW 0x0 PPGA Output Polarity Specification

0: PPGA output signal has normal polarity

1: PPGA output signal has inverted polarity

Table 3-1090: PPGn_OPTMSK Register




PPGn_RMPCFG

Description: Ramp Configuration Register



Table 3-1091: PPGn_RMPCFG Register



[3] RIDH RW 0x0 Duty Increment or Decrement in Ramp Mode (high 8-bit part)

0: Increment PWM duty of PPGB output in ramp mode until the end duty is reached

1: Decrement PWM duty of PPGB output in ramp mode until the end duty is reached

[2] RIDL RW 0x0 Duty Increment or Decrement in Ramp Mode (16-bit or low 8-bit part).

0: Increment PWM duty of PPGA output in ramp mode until the end duty is reached

1: Decrement PWM duty of PPGA output in ramp mode until the end duty is reached

In 16-bit operation mode (PPGn_PCN:MOD = 0) RIDL bit controls duty increment or decrement function of 16bit PWM signal and during 8-bit opera-tion (PPGn_PCN:MOD = 1) it is dedicated to low 8-bit PWM output.



[1] RAMPH RW 0x0 Ramp Mode Selection (high 8-bit part)

0: Disable ramp mode for PPGB output

1: Enable ramp mode for PPGB output

This bit enables ramp mode PWM opera-tion for higher 8-bit part if PPGn_PCN:MOD = 1. In this mode PWM duty is incremented (PPGn_RMPCFG:RIDH is '0') or decre-mented (PPGn_RMPCFG:RIDH is '1') with every external trigger signal (selected one of seven possible reload timer underflow signals).

PWM output waveform starts with the duty defined by PDUTH register and the duty value is incremented/decremented until the end duty value is reached defined by the register PEDRH.

Actual update of the PWM output duty takes place only at the end of PWM cycle.

[0] RAMPL RW 0x0 Ramp Mode Selection (16-bit or low 8-bit part)

0: Disable ramp mode for PPGA output

1: Enable ramp mode for PPGA output

This bit enables ramp mode PWM opera-tion for lower 8-bit part if PPGn_PCN:MOD = 1. During 16-bit, operation, the bit con-trols ramp mode of 16-bit PWM. In this mode PWM duty is incremented, (PPGn_RMPCFG:RIDL is '0') or decre-mented (PPGn_RMPCFG:RIDL is '1') with every external trigger signal (selected one of seven possible reload timer underflow signals).

PWM output waveform starts with the duty defined by PDUT/PDUTL register and the duty value is incremented/decremented until the end duty value is reached defined by the register PEDR/PEDRL.

Actual update of the PWM output duty takes place only at the end of PWM cycle.

Table 3-1091: PPGn_RMPCFG Register




PPGn_STRD

Description: Start Delay Mode Register



Table 3-1092: PPGn_STRD Register



[0] STRD RW 0x0 Start Delay Mode

0: Delayed start of PWM output generation is disabled

1: Delayed start of PWM output generation is enabled

When STRD bit is set to '1', the PWM out-put generation is delayed by PSDR + 1 cycles of the PPG counter clock. If the full range mode is activated (PPGn_EPCN1:FRMH/FRML = 1), start is delayed for PSDR cycles of the PPG coun-ter clock.



PPGn_TRIGCLR

Description: PPG Trigger Clear Flag Register



Table 3-1093: PPGn_TRIGCLR Register



[0] TRGCLR R0W1

0x0 PPG Start or Trigger Event Flag Clear bit

0: No effect

1: Clears PPGn_EPCN1:TRIG flag

Reading this bit always returns 0



PPGn_EPCN1

Description: Extended PPG Control Status Register 1


Instance no 0: 0x0008800AInstance no 1: 0x0008840AInstance no 2: 0x0008880AInstance no 3: 0x00088C0AInstance no 4: 0x0008A00AInstance no 5: 0x0008A40AInstance no 6: 0x0008A80AInstance no 7: 0x0008AC0AInstance no 8: 0x0008C00AInstance no 9: 0x0008C40AInstance no 10: 0x0008C80AInstance no 11: 0x0008CC0AInstance no 12: 0x0008E00AInstance no 13: 0x0008E40AInstance no 14: 0x0008E80AInstance no 15: 0x0008EC0A

Table 3-1094: PPGn_EPCN1 Register



[12] TRIG R 0x0 PPG Start or Trigger Event Flag

This is read only bit

0: No interrupt

1: Interrupt

TRIG flag is set to '1' when the PWM output generation is started. In start delay mode PPGn_STRD:STRD = 1 it happens at the end of defined start delay. For all other operation modes (PPGn_STRD:STRD = 0), the flag becomes '1' when PPG trigger event is detected.


[9] FRMH RW 0x0 Full Range Mode (high 8-bit part)

0: PPGB output signal has period of PCSR+1 and duty of PDUT+1 count clock cycles

1: PPGB output signal has period of PCSR and duty of PDUT count clock cycles

When the bit is set to '1', the limit case PDUT = PCSR generates H on the PPGB output and for PDUT = 0 L level is gener-ated all time.



[8] FRML RW 0x0 Full Range Mode (16-bit or low 8-bit part)

0: PPGA output signal has period of PCSR+1 and duty of PDUT+1 count clock cycles

1: PPGA output signal has period of PCSR and duty of PDUT count clock cycles

When the bit is set to '1', the limit case PDUT = PCSR generates H on the PPGA output and for PDUT = 0 L level is gener-ated all the time.


[2] TPCH RW 0x0 Timing Point Capture Selection (high 8-bit part).

0: Disable timing point capture mode for PPGB output

1: Enable timing point capture mode for PPGB output

If this bit is set to '1' and PPGn_PCN:MOD = 1, matching between PPG counter (higher 8-bit part) and PTPCH generates an ADTRG signal.

[1] TPCL RW 0x0 Timing Point Capture Selection (16-bit or low 8-bit part).

0: Disable timing point capture mode for PPGA output

1: Enable timing point capture mode for PPGA output

If this bit is set to '1' and PPGn_PCN:MOD = 1, matching between PPG counter (lower 8-bit part) and PTPCL bit description gen-erates an ADTRG signal.

Accordingly during 16-bit operation ADTRG signal is generated on the match between 16-bit PPG counter value and PTPC.






PPGn_EPCN2

Description: Extended PPG Control Status Register 2


Instance no 0: 0x0008800CInstance no 1: 0x0008840CInstance no 2: 0x0008880CInstance no 3: 0x00088C0CInstance no 4: 0x0008A00CInstance no 5: 0x0008A40CInstance no 6: 0x0008A80CInstance no 7: 0x0008AC0CInstance no 8: 0x0008C00CInstance no 9: 0x0008C40CInstance no 10: 0x0008C80CInstance no 11: 0x0008CC0CInstance no 12: 0x0008E00CInstance no 13: 0x0008E40CInstance no 14: 0x0008E80CInstance no 15: 0x0008EC0C



[15] TCHCLR R0W1

0x0 Timing Point Capture Flag (high 8-bit part) Clear bit

0: No effect

1: Clears PPGn_EPCN2:TCH flag


[14] TCLCLR R0W1

0x0 Timing Point Capture Flag (16-bit or low 8-bit part) Clear bit

0: No effect

1: Clears PPGn_EPCN2:TCL flag


[13] EDMHCLR R0W1

0x0 End Duty Match Flag in Ramp Mode (high 8-bit part) Clear bit

0: No effect

1: Clears PPGn_EPCN2:EDMH flag


[12] EDMLCLR R0W1

0x0 End Duty Match Flag in Ramp Mode (16-bit or low 8-bit part) Clear bit

0: No effect

1: Clears PPGn_EPCN2:EDML flag


[11] DTHCLR R0W1

0x0 Duty Match Flag (high 8-bit part) Clear bit

0: No effect

1: Clears PPGn_EPCN2:DTH flag




[10] DTLCLR R0W1

0x0 Duty Match Flag (16-bit or low 8-bit part) Clear bit

0: No effect

1: Clears PPGn_EPCN2:DTL flag


[9] PRDHCLR R0W1

0x0 Cycle Match Flag (high 8-bit part) Clear bit

0: No effect

1: Clears PPGn_EPCN2:PRDH flag


[8] PRDLCLR R0W1

0x0 Cycle Match Flag (16-bit or low 8-bit part) Clear bit

0: No effect

1: Clears PPGn_EPCN2:PRDL flag


[7] TCH R 0x0 Timing Point Capture Flag (high 8-bit part)

This is a read-only bit



The TCH flag is set to '1' when the PPG counter value PTMRH reaches the timing point defined by the PTPCH register.In 16-bit operation mode (PPGn_PCN:MOD = 0) TCH flag has no meaning.

This bit is cleared by writing '1' to PPGn_EPCN2:TCHCLR.

[6] TCL R 0x0 Timing Point Capture Flag (16-bit or low 8-bit part)




In 16-bit operation mode (PPGn_PCN:MOD = 0) TCL flag is set by matching of 16-bit registers PTMR and PTPC. If PPGn_PCN:MOD = 1, the flag is a result of comparing PTMRL and PTPCL.

This bit is cleared by writing '1' to PPGn_EPCN2:TCLCLR.





[5] EDMH R 0x0 End Duty Match Flag in Ramp Mode (high 8-bit part)




The EDMH flag is set to '1' when the cur-rent PWM duty has reached the duty value defined by the PEDRH register in ramp operation mode. If the control, bit PPGn_RMPCFG:RAMPH is '0' or in 16-bit operation mode (PPGn_PCN:MOD = 1) EDMH flag has no meaning.

This bit is cleared by writing '1' to PPGn_EPCN2:EDMHCLR.

[4] EDML R 0x0 End Duty Match Flag in Ramp Mode (16-bit or low 8-bit part)




In 16-bit operation mode (PPGn_PCN:MOD = 0) EDML flag is set by matching of the current duty value and PEDR. If PPGn_PCN:MOD = 1, the flag is a result of reaching the duty defined by PEDRL.

This bit is cleared by writing '1' to PPGn_EPCN2:EDMLCLR.

[3] DTH R 0x0 Duty Match Flag (high 8-bit part)




The DTH flag is set to '1' by matching of the registers PTMRH and PDUTH.In 16-bit operation mode (PPGn_PCN:MOD = 0) DTH flag has no meaning.

This bit is cleared by writing '1' to PPGn_EPCN2:DTHCLR.





[2] DTL R 0x0 Duty Match Flag (16-bit or low 8-bit part)




In 16-bit operation mode (PPGn_PCN:MOD = 0) DTL flag is set by matching of 16-bit registers PTMR and PDUT. If PPGn_PCN:MOD = 1, the flag is a result of comparing PTMRL and PDUTL.

This bit is cleared by writing '1' to PPGn_EPCN2:DTLCLR.

[1] PRDH R 0x0 Cycle Match Flag (high 8-bit part)




The PRDH flag is set to '1' in case of PTMRH counter underflow.In 16-bit opera-tion mode (PPGn_PCN:MOD = 0) PRDH flag has no meaning.

This bit is cleared by writing '1' to PPGn_EPCN2:PRDHCLR.

[0] PRDL R 0x0 Cycle Match Flag (16-bit or low 8-bit part)




In 16-bit operation mode (PPGn_PCN:MOD = 0) PRDL flag is set by 16-bit PTMR counter underflow. If PPGn_PCN:MOD = 1, the flag is a result of PTMRL underflow.

This bit is cleared by writing '1' to PPGn_EPCN2:PRDLCLR.





PPGn_GCN1

Description: General Control Register 1


Instance no 0: 0x0008800EInstance no 1: 0x0008840EInstance no 2: 0x0008880EInstance no 3: 0x00088C0EInstance no 4: 0x0008A00EInstance no 5: 0x0008A40EInstance no 6: 0x0008A80EInstance no 7: 0x0008AC0EInstance no 8: 0x0008C00EInstance no 9: 0x0008C40EInstance no 10: 0x0008C80EInstance no 11: 0x0008CC0EInstance no 12: 0x0008E00EInstance no 13: 0x0008E40EInstance no 14: 0x0008E80EInstance no 15: 0x0008EC0E

Table 3-1096: PPGn_GCN1 Register





[3:0] TSEL RW 0x0 General Control Register 1

The General Control Register 1 (GCN1) selects a trigger input to a PPG

TSEL[3:0] activation trigger specification

0000: EN0 bit (PPGGRPp_GCTRL regis-ter)




0100: 32-bit Reload Timer 0 output

0101: 32-bit Reload Timer 1 output

0110: CTG0 bit (PPGGCLg_GCNR regis-ter)

0111: CTG1 bit (PPGGCLg_GCNR regis-ter)

1000: Iris Frame IRQ 0

1001: Reload Timer 8

1010: nc.

1011: nc.

Others: Disabled

PPG0 to PPG3 as selected are activated when the edge specified by the Trigger Input Edge Selection bits (PPGn_PCN:EGS[1:0]) are detected by the specified activation trigger.





PPGn_GCN3



Instance no 0: 0x0008800FInstance no 1: 0x0008840FInstance no 2: 0x0008880FInstance no 3: 0x00088C0FInstance no 4: 0x0008A00FInstance no 5: 0x0008A40FInstance no 6: 0x0008A80FInstance no 7: 0x0008AC0FInstance no 8: 0x0008C00FInstance no 9: 0x0008C40FInstance no 10: 0x0008C80FInstance no 11: 0x0008CC0FInstance no 12: 0x0008E00FInstance no 13: 0x0008E40FInstance no 14: 0x0008E80FInstance no 15: 0x0008EC0F




[2:0] RTG RW 0x0 General Control Register 3

RTG[2:0] Trigger specification

000: Reload Timer 0 underflow







Others: Reload Timer 6 underflow



PPGn_GCN4







[3] CKSEL RW 0x0 Prescalar input selection

CKSEL

0: Use CLKP as prescaler input

1: Use RLT as prescaler input, selected by PPGn_GCN4:RCK from seven RLT under-flow signals

[2:0] RCK RW 0x6 General Control Register 4

The General Control Register 4 (GCN4) selects a reload timer input that can be used as PPG count clock to the PPG . One of seven reload timer underflow signals can be selected.

The chosen reload timer input becomes the PPG count clock (prescaler input) only if the bit PPGGRPp_GCTRL:CKSELi is set to '1'.

RCK[2:0] Reload Timer selected








Others: Reload Timer 6 underflow



PPGn_GCN5







[1:0] RSH RW 0x0 General Control Register 5

The General Control Register 5 (GCN5) introduces a fine delay (phase shift) of a reload timer input that can be used as PPG count clock.

The phase shift can be defined separately for every PPG module.

If this feature is used, the selected reload timer should be set to a reload cycle value of at least 13 peripheral clock cycles (13 CLKP).

RSH[1:0] fine delay

00: No delay

01: 4 CLKP cycles delay





PPGn_PCSR

Description: PPG Cycle Setting Register



Table 3-1100: PPGn_PCSR Register


[15:8] PCSRH RW X PPG Cycle Setting Register

The PPG Period Setting Registers come with buffers. Transfers from the buffers to the counter take place automatically upon counter borrow.

After the PPG Period Setting registers have been written, be sure to set PPG Duty Set-ting registers PDUT.When the register is read, the buffered value i.e. actual cycle setting is read.

[7:0] PCSRL RW X PPG Cycle Setting Register

The PPG Period Setting Registers come with buffers. Transfers from the buffers to the counter take place automatically upon counter borrow.

After the PPG Period Setting registers have been written, be sure to set PPG Duty Set-ting registers PDUT., When the register is read, the buffered value i.e. actual cycle setting is read.



PPGn_PDUT

Description: PPG Duty Setting Register



Table 3-1101: PPGn_PDUT Register


[15:8] PDUTH RW X PPG Duty Setting Register

The PPG Duty Setting Register (PDUT) sets the duty of the PPG output waveform. In 8-bit operation mode PDUTH defines the duty of the PPGB output.

The PPG Duty Setting Register are buff-ered.Transfers from the buffers to the counter take place automatically upon counter borrow. When the register is read, the buffered value i.e. actual duty setting is read.

Set a value smaller than the setting of PPG Period Setting Register PCSR in a PPG Duty Setting register.

If the same value is set in a PPG Duty Set-ting Register as is set in PPG Period Set-ting Register PCSR, then

H is always output at normal polarity (PPGn_OPTMSK:OSEL/OSEL2 = 0).

L is always output at inverted polarity (PPGn_OPTMSK:OSEL/OSEL2 = 1).



[7:0] PDUTL RW X PPG Duty Setting Register

The PPG Duty Setting Register (PDUT) sets the duty of the PPG output waveform. In 8-bit operation mode PDUTL sets the duty of the PPGA signal.

The PPG Duty Setting Registers are buff-ered. Transfers from the buffers to the counter take place, automatically upon counter borrow. When the register is read, the buffered value i.e. actual duty setting is read.

Set a value smaller than the setting of PPG Period Setting register PCSR in a PPG Duty Setting register.

If the same value is set in a PPG Duty Set-ting register as is set in PPG Period Setting register PCSR, then

H is always output at normal polarity (PPGn_OPTMSK:OSEL/OSEL2 = 0).

L is always output at inverted polarity (PPGn_OPTMSK:OSEL/OSEL2 = 1).

Table 3-1101: PPGn_PDUT Register




PPGn_PTMR

Description: PPG Timer Register



Table 3-1102: PPGn_PTMR Register


[15:8] PTMRH R 0xFF PPG Timer Register high 8-bit part

The PPG Timer Register (PTMR) reads the counts of PPGn. In 8-bit operation mode PTMRH defines the PPG counter dedi-cated to the PPGB signal .

[7:0] PTMRL R 0xFF PPG Timer Register 16-bit or low 8-bit part

The PPG Timer Register (PTMR) reads the counts of PPGn. In 8-bit operation mode PTMRL defines the PPG counter dedicated to the PPGA signal.



PPGn_PSDR

Description: PPG Start Delay Register



Table 3-1103: PPGn_PSDR Register


[15:8] PSDRH RW 0x0 PPG Start Delay Register

The PPG Start Delay Register (PSDR) con-trols delay of PWM output generation by PSDR+1 cycles of PPG counter clock, when the PPGn_STRD:STRD bit is set to '1'.

In 8-bit operation mode PSDRH defines the start delay of the PPGB output and PSDRL sets the start delay of the PPGA signal.

In the full range mode PWM output delay is PSDR PPG count cycles., PSDR value should be set when PPG module operation is disabled (PPGn_CNTEN:CNTE = 0).

[7:0] PSDRL RW 0x0 PPG Start Delay Register

The PPG Start Delay Register (PSDR) con-trols delay of PWM output generation by PSDR+1 cycles of PPG counter clock, when the PPGn_STRD:STRD bit is set to '1'.

In 8-bit operation mode PSDRH defines the start delay of the PPGB output and PSDRL sets the start delay of the PPGA signal.

In the full range mode PWM output delay is PSDR PPG count cycles., PSDR value should be set when PPG module operation is disabled (PPGn_CNTEN:CNTE = 0).



PPGn_PTPC

Description: PPG Timing Point Capture Register


Instance no 0: 0x0008801AInstance no 1: 0x0008841AInstance no 2: 0x0008881AInstance no 3: 0x00088C1AInstance no 4: 0x0008A01AInstance no 5: 0x0008A41AInstance no 6: 0x0008A81AInstance no 7: 0x0008AC1AInstance no 8: 0x0008C01AInstance no 9: 0x0008C41AInstance no 10: 0x0008C81AInstance no 11: 0x0008CC1AInstance no 12: 0x0008E01AInstance no 13: 0x0008E41AInstance no 14: 0x0008E81AInstance no 15: 0x0008EC1A

Table 3-1104: PPGn_PTPC Register


[15:8] PTPCH RW 0x0 PPG Timing Point Capture register

The PPG Timing Point Capture Register (PTPC) sets the timing point within PWM cycle that can be captured to generate an interrupt request or an ADTRG signal, if

In 8-bit operation mode PTPCH defines the timing point for the PPGB output and PTPCL sets the timing point for the PPGA signal.

[7:0] PTPCL RW 0x0 PPG Timing Point Capture register

The PPG Timing Point Capture Register (PTPC) sets the timing point within PWM cycle that can be captured to generate an interrupt request or an ADTRG signal if adequate control bits PPGn_EPCN1:TPCH/TPCL are set to '1'.

In 8-bit operation mode PTPCH defines the timing point for the PPGB output and PTPCL sets the timing point for the PPGA signal.



PPGn_PEDR

Description: PPG End Duty Register


Instance no 0: 0x0008801CInstance no 1: 0x0008841CInstance no 2: 0x0008881CInstance no 3: 0x00088C1CInstance no 4: 0x0008A01CInstance no 5: 0x0008A41CInstance no 6: 0x0008A81CInstance no 7: 0x0008AC1CInstance no 8: 0x0008C01CInstance no 9: 0x0008C41CInstance no 10: 0x0008C81CInstance no 11: 0x0008CC1CInstance no 12: 0x0008E01CInstance no 13: 0x0008E41CInstance no 14: 0x0008E81CInstance no 15: 0x0008EC1C

Table 3-1105: PPGn_PEDR Register


[15:8] PEDRH RW 0x0 PPG End Duty Register

The PPG End Duty Register (PEDRn) sets the end point of the PWM duty ramp in ramp operation mode PPGn_RMPCFG:RAMPH/RAMPL = 1.

In 8-bit operation mode PEDRH defines the end duty of the PPGB output and PEDRL sets the end duty of the PPGA signal.

In the ramp mode PWM duty is incre-mented (PPGn_RMPCFG:RIDH/RIDL = 0) or decremented (PPGn_RMPCFG:RIDH/RIDL = 1) with every selected reload timer underflow pulse.PWM output waveform starts with the duty defined by PDUT regis-ter and the duty value is incremented/dec-remented until the end duty is reached.



[7:0] PEDRL RW 0x0 PPG End Duty Register

The PPG End Duty Register (PEDRn) sets the end point of the PWM duty ramp in ramp operation mode, PPGn_RMPCFG:RAMPH/RAMPL = 1.

In 8-bit operation mode PEDRH defines the end duty of the PPGB output and PEDRL sets the end duty of the PPGA signal.

In the ramp mode PWM duty is incre-mented (PPGn_RMPCFG:RIDH/RIDL = 0) or decremented (PPGn_RMPCFG:RIDH/RIDL = 1) with every selected reload timer underflow pulse.PWM output waveform starts with the duty defined by PDUT regis-ter and the duty value is incremented/dec-remented until the end duty is reached.

Table 3-1105: PPGn_PEDR Register




PPGn_DMACFG

Description: PPG DMA Configuration Register


Instance no 0: 0x0008801EInstance no 1: 0x0008841EInstance no 2: 0x0008881EInstance no 3: 0x00088C1EInstance no 4: 0x0008A01EInstance no 5: 0x0008A41EInstance no 6: 0x0008A81EInstance no 7: 0x0008AC1EInstance no 8: 0x0008C01EInstance no 9: 0x0008C41EInstance no 10: 0x0008C81EInstance no 11: 0x0008CC1EInstance no 12: 0x0008E01EInstance no 13: 0x0008E41EInstance no 14: 0x0008E81EInstance no 15: 0x0008EC1E

Table 3-1106: PPGn_DMACFG Register



[0] EN_DMA_REQ RW 0x0 Enable DMA Request

0: No DMA request

1: Enable DMA request




3.11.2 Programmable Pulse Generators Control Register Overview

A group of 4 PPGs has a set of group control registers.

All 16 PPGs have one common control register unit.


Base Address(es)

Instance no 0: BASEADDR0="00089000"Instance no 1: BASEADDR1="0008B000"Instance no 2: BASEADDR2="0008D000"Instance no 3: BASEADDR3="0008F000"


BASEADDRx + 0x0000 PPGGRPp_GCTRL PPG Group Control Register





BASEADDR + 0x0000 PPGGLCg_GCNR PPG General Control Register




PPG - Group Control Unit Register

PPGGRPp_GCTRL

Description: PPG Group Control Register


Instance no 0: 0x00089000Instance no 1: 0x0008B000Instance no 2: 0x0008D000Instance no 3: 0x0008F00

Table 3-1109: PPGGRPp_GCTRL Register



[3:0] EN RW 0x0 Internal Triggers

0: Set the level to L

1: Set the level to H

Set the levels of internal triggers EN[3:0].

If any of the EN trigger inputs (EN[3:0]) is selected with the trigger specification bits (PPGn_GCN1:TSEL[3:0]) of PPG, then the selected EN serves as a PPG trigger input bit.

If the state selected with the trigger input edge selection bit (PPGn_PCN:EGS[1:0]) is generated by software using the trigger input bit (selected EN[0] EN[1] EN[2] or EN[3]), the choice serves as an activation trigger to activate the PPG.



PPG - Group Common Control Unit Register

PPGGLCg_GCNR

Description: PPG General Control Register



Table 3-1110: PPGGLCg_GCNR Register



[1:0] CTG RW 0x0 Common Trigger

CTG[0]/CTG[1]

'0': Set the level to L

'1': Set the level to H

Set the levels of common triggers CTG[0] and CTG[1]. If any of the CTG trigger inputs (CTG[0], CTG[1]) is selected with the trigger specification bits (PPGn_GCN1:TSEL[3:0]) of PPGn, then the selected CTG serves as a PPG trigger input bit. If the state selected with the trig-ger input edge selection bit (PPGn_PCN:EGS[1:0]) is generated by software using the common trigger bit (selected CTG[0] or CTG[1]), the choice serves as an activation trigger to activate the PPG.



3.12 I2C Registers

In this section, the ‘Register Overview’ table summarizes all I2C registers, including base address of themodule and name, description, and the absolute address of each register, which are then describedseparately in the following tables.



3.12.1 I2C Register Overview


Base Address(es)Instance no 0: BASEADDR0="00094000"Instance no 1: BASEADDR1="00095000"


BASEADDRx + 0x0000 I2Cn_IBCSR Bus Control and Status Register




BASEADDRx + 0x0008 I2Cn_IODAR Output Data Register


BASEADDRx + 0x000A I2Cn_ICCR Clock Control Register

BASEADDRx + 0x000B Reserved Do not modify

BASEADDRx + 0x000C I2Cn_ICDIDAR CPU and DMA Input Data Register

BASEADDRx + 0x000E I2Cn_IEICR Interface Enable and Interrupt Clear Register

BASEADDRx + 0x0010 I2Cn_DDMACFG DMA Configuration Register

BASEADDRx + 0x0012 I2Cn_IEIER Error Interrupt Enable Register



I2Cn_IBCSR

Description: Bus Control and Status Register



Table 3-1112: I2Cn_IBCSR Register


[15] BER R 0x0 Bus Error bit

This bit is the bus error interrupt flag. It is set by the hardware and cleared by the user. This bit is cleared by writing '1' to I2Cn_IEICR:BERCLR.

'0': No bus error detected

'1': One of the error conditions described below detected

When this bit is set, the I2Cn_IEICR:EN bit cleared, the I2C interface goes to pause status, data transfer is interrupted, and all bits in the I2Cn_IBCSR and the I2Cn_IBCSR registers except I2Cn_IBCSR:BER and I2Cn_IBCSR:BEIE are cleared. The I2Cn_IBCSR:BER bit must be cleared before the interface may be re-enabled.

This bit is set to '1' if:

1. Start or stop conditions are detected at wrong places: during an address data transfer or during the transfer of the bits two to nine (acknowledge bit).

2. A ten bit address header with read access is received before a ten bit write access.

[14] BEIE RW 0x0 Bus Error Interrupt Enable bit

This bit enables the bus error interrupt. It only can be changed by the user.

'0': Bus error interrupt disabled

'1': Bus error interrupt enabled

Setting this bit to '1' enables interrupt gen-eration (IRQ) when I2Cn_IBCSR:BER bit is set to '1'.



[13] SCC R0W1

0x0 Start Condition Continue bit

This bit is used to generate a repeated start condition. It is a write-only bit. It always reads '0'.

Write access:

'0': No effect

'1': Generate repeated start condition dur-ing master transfer

A repeated start condition is generated if a '1' is written to this bit while an interrupt in master mode (I2Cn_IBCSR:MSS = '1' and I2Cn_IBCSR:INT = '1') and the I2Cn_IBCSR:INT bit is cleared automati-cally.





[12] MSS RW 0x0 Master Slave Select bit

This is the master/slave mode selection bit. It can only be set by the user, but it can be cleared by the user and the hardware.

'0': Go to slave mode

'1': Go to master mode, generate start con-dition and send address data byte in I2Cn_IODAR:IODAR register. It is cleared if an arbitration loss event occurs during master sending

If a '0' is written to it during a master inter-rupt (I2Cn_IBCSR:MSS = '1' and I2Cn_IBCSR:INT = '1'), the I2Cn_IBCSR:INT bit is cleared automati-cally, a stop condition will be generated and the data transfer ends.

Note: The I2Cn_IBCSR:MSS bit is reset immediately, the generation of the stop condition can be checked by polling the I2Cn_IBCSR:BB bit.

If a '1' is written to it while the bus is idle (I2Cn_IBCSR:MSS = '0' and I2Cn_IBCSR:BB = '0'), a start condition is generated and the contents of the I2Cn_IODAR:IODAR register (which should be address data) is sent. If a '1' is written to the I2Cn_IBCSR:MSS bit while the bus is in use (I2Cn_IBCSR:BB = '1', I2Cn_IBCSR:TRX = '0', and I2Cn_IBCSR:MSS = '0'),the interface waits until the bus is free and then starts sending. If the interface is addressed as slave with write access (data reception) in the mean-time, it will start sending data if the bus is free again. If the interface is sending data as slave in the meantime (I2Cn_IBCSR:AAS = '1' and I2Cn_IBCSR:TRX = '1'), it will not start sending data if the bus is free again. It is important to check whether the interface was addressed as slave (I2Cn_IBCSR:AAS = '1'), sent the data byte successfully (I2Cn_IBCSR:MSS = '1') or failed to send the data byte (I2Cn_IBCSR:AL = '1') at the next interrupt.





[11] ACK RW 0x0 Acknowledge bit

This bit enables acknowledge generation on data byte reception. It only can be changed by the user.

'0': The interface will not acknowledge on data byte reception

'1': The interface will acknowledge on data byte reception

This bit is not valid when receiving address byte in slave mode if the interface detects its seven or ten bit slave address, it will acknowledge if the corresponding enable bit (I2Cn_ITMK:ENTB or I2Cn_ISBMA:ENSB) is set.

Write access to this bit should occur during an interrupt (I2Cn_IBCSR:INT = '1') or if the bus is idle (I2Cn_IBCSR:BB = '0'). In addi-tion the interface must be enabled (I2Cn_IEICR:EN = '1') and there has to be no bus error (I2Cn_IBCSR:BER = '0').

[10] GCAA RW 0x0 General Call Address Acknowledge bit

This bit enables acknowledge generation when a general call address is received. It only can be changed by the user.

'0': The interface will not acknowledge on general call address byte reception

'1': The interface will acknowledge on gen-eral call address byte reception

Write access to this bit should occur during an interrupt (I2Cn_IBCSR:INT = '1') or if the bus is idle (I2Cn_IBCSR:BB = '0' ).

Write access to this bit is only possible if the interface is enabled (I2Cn_IEICR:EN = '1') and if there is no bus error(I2Cn_IBCSR:BER = '0').

[9] INTE RW 0x0 Interrupt Enable bit

This bit enables the interrupt generation. It only can be changed by the user.

'0': Interrupt disabled

'1': Interrupt enabled

Setting this bit to '1' enables interrupt gen-eration (IRQ) when the I2Cn_IBCSR:INT bit is set to '1' (by the hardware).





[8] INT R 0x0 Interrupt Flag bit

This bit is the interrupt flag. It is set by the hardware and cleared by the user. This bit is cleared by writing '1' to I2Cn_IEICR:INTCLR.

'0': Transfer not ended or not involved in current transfer or bus is idle

'1': Set at the end of a 1 byte data transfer or reception including the acknowledge bit under the following conditions:

Device is bus master.

Device is addressed as slave.

General call address received.

Arbitration loss occurred.

Set at the end of an address data reception (after first byte if seven bit address received, after second byte if ten bit address received) including the acknowl-edge bit if the device is addressed as slave.

While this bit is '1' the SCL line will hold an 'L' level signal. Clearing this bit releases the SCL line, and executes transfer of the next byte or a repeated start or stop condition is generated. Additionally, this bit is cleared if a '1' is written to the I2Cn_IBCSR:SCC bit or the I2Cn_IBCSR:MSS bit is being cleared.

This bit is also cleared when I2Cn_DDMACFG:DMAMODE bit is set and read operation at I2Cn_ICDIDAR:IDIDAR or write operation at I2Cn_IODAR is per-formed.

[7] BB R 0x0 Bus Busy bit

This bit indicates the status of the I2C bus.

'0': Stop condition detected (bus idle)

'1': Start condition detected

This bit is set to '1' if a start condition is detected. It is reset upon a stop condition.

[6] RSC R 0x0 Repeated Start Condition bit

This bit indicates detection of a repeated start condition.

'0': Repeated start condition not detected

'1': Repeated start condition detected (bus in use)

This bit is cleared at the end of an address data transfer (I2Cn_IBCSR:ADT = '0') or detection of a stop condition.





[5] AL R 0x0 Arbitration Lost bit

This bit indicates an arbitration loss.

'0': No arbitration loss detected

'1': Arbitration loss occurred during master sending

This bit is cleared by writing '1' to the I2Cn_IEICR:INTCLR bit or by writing '1' to the I2Cn_IBCSR:MSS bit or by writing '1' to the I2Cn_IEICR:ALCLR.

An arbitration loss occurs if:

The data sent does not match the data read on the SDA line at the rising SCL edge.

A repeated start condition is generated by another master in the first bit of a data byte.

The interface could not generate a start or stop condition because signal transition caused from '1' to '0' by a certain external condition observed at the SCL line.

[4] LRB R 0x0 Last Received Bit

This bit is used to indicate the acknowledge from the receiving device.

'0': Receiver acknowledged

'1': Receiver not acknowledged

It is changed by the hardware upon recep-tion of bit 9 (acknowledge bit) and is also cleared by a start or stop condition.





[3] TRX R 0x0 Transferring Data bit

This bit is used to indicate the status of data transmission operation.

'0': Not transmitting data

'1': Transmitting data

It is set to '1':

If a start condition was generated in master mode.

If addressed as slave in read access.

It is set to '0':

If the bus is idle (I2Cn_IBCSR:BB = '0').

An arbitration loss occurred.

'1' is written to the I2Cn_IBCSR:SCC bit during master interrupt (I2Cn_IBCSR:MSS = '1' and I2Cn_IBCSR:INT = '1').

The I2Cn_IBCSR:MSS bit being cleared during master interrupt (I2Cn_IBCSR:MSS = '1' and I2Cn_IBCSR:INT = '1').

The interface is in slave mode and the last transferred byte was not acknowledged.

The interface is in slave mode and it is receiving data.

The interface is in master mode and is reading data from a slave.

[2] AAS R 0x0 Addressed As Slave bit

This bit indicates detection of a slave addressing.

'0': Not addressed as slave

'1': Addressed as slave

This bit is cleared by a (repeated) start or stop condition. It is set if the interface detects its seven and/or ten bit slave address.

[1] GCA R 0x0 General Call Address bit

This bit indicates detection of a general call address (0x00).

'0': General call address not received as slave

'1': General call address received as slave





[0] ADT R 0x0 Address Data Transfer bit

This bit indicates the detection of an address data transfer.

'0': Incoming data is not address data (or bus is not in use)

'1': Incoming data is address data

This bit is set to '1' by a start condition. It is cleared after the second byte if a ten bit slave address header with write access is detected, else it is cleared after the first byte.

This bit is also cleared when:

'0' is written to the I2Cn_IBCSR:MSS bit during a master interrupt (I2Cn_IBCSR:MSS = '1' and I2Cn_IBCSR:INT = '1').

'1' is written to the I2Cn_IBCSR:SCC bit during a master interrupt (I2Cn_IBCSR:MSS = '1' and I2Cn_IBCSR:INT = '1').

The I2Cn_IBCSR:INT bit is being cleared.

The beginning of every byte transfer if the interface is not involved in the current transfer as master or slave.





I2Cn_IODAR

Description: Output Data Register



Table 3-1113: I2Cn_IODAR Register


[7:0] IODAR RW 0x0 Output Data Register

The Output Data Register(IODAR) is used in serial data transfer and transfers MSB data first. This register is double buffered on the write side, so that when the bus is in use (I2Cn_IBCSR:BB = '1'), write data can be loaded to the register for serial transfer. The data byte is loaded into the internal transfer register if the I2Cn_IBCSR:INT bit in the I2Cn_IBCSR register is being cleared or the bus is idle (I2Cn_IBCSR:BB = '0'). Writing this register clears I2Cn_IBCSR:INT if I2Cn_DDMACFG:DMAMODE bit is set.



I2Cn_ICCR

Description: Clock Control Register


Instance no 0: 0x0009400AInstance no 1: 0x0009500A

Table 3-1114: I2Cn_ICCR Register



[5:0] CS RW 0x3F Clock Prescaler bits

These bits select the serial bit rate. They can only be changed if the interface is dis-abled (I2Cn_IEICR:EN = '0'). For more description refer to Section 'Clock prescaler settings'.



I2Cn_ICDIDAR

Description: CPU and DMA Input Data Register



Table 3-1115: I2Cn_ICDIDAR Register


[15:8] ICIDAR R 0x0 I2C CPU Input Data Register

By reading this register, the internal trans-fer register is read directly, therefore received data values in this register are valid only if I2Cn_IBCSR:INT = '1'.

[7:0] IDIDAR R 0x0 I2C DMA Input Data Register

By reading this register, the internal trans-fer register is read directly, received data values in this register are valid only, if I2Cn_IBCSR:INT = '1'. Reading this regis-ter clears I2Cn_IBCSR:INT if I2Cn_DDMACFG:DMAMODE bit is set.

This register can be read by enabling PPU access, else reading causes PPU error.



I2Cn_IEICR

Description: Interface Enable and Interrupt Clear Register


Instance no 0: 0x0009400EInstance no 1: 0x0009500E

Table 3-1116: I2Cn_IEICR Register



[12:10] NSF RW 0x0 IO Pad Noise Filter Configuration bits

The noise filter will suppress single spikes with a pulse width of 0 ns (minimum) and 4 cycles of the peripheral clock. The maxi-mum depends on the phase relationship between I2C signals (SDA, SCL) and peripheral clock.

These bits configure the noise filters built into the SDA and SCL IO pads.

'000': Suppress single spikes of pulse width between 0.5 and 1 cycles

'001': Suppress single spikes of pulse width between 1 and 1.5 cycles







I2Cn_IEICR:NSF configuration are applica-ble when I2Cn_IEICR:NSFEN is set.

[9] NSFEN RW 0x0 IO Pad Noise Filter Enable bit

'0': Noise filter disabled

'1': Noise filter enabled

This bit enable the noise filters built into the SDA and SCL IO pads.

The noise filter will suppress single spikes according to I2Cn_IEICR:NSF configura-tion.

It should be set to '1' if the interface is transmitting or receiving at data rates above 100 kbps.



[8] EN RW 0x0 Enable bit

This bit enables the I2C interface opera-tion. It can only be set by the user but may be cleared by the user and the hardware.

'0': Interface disabled

'1': Interface enabled

When this bit is set to '0' all bits in the I2Cn_IBCSR register (except the I2Cn_IBCSR:BER and I2Cn_IBCSR:BEIE bits) are cleared, the module is disabled, and the I2C lines are left open. It is cleared by the hardware if a bus error occurs (I2Cn_IBCSR:BER = '1').

Note: The interface immediately stops transmitting or receiving if it is being dis-abled. This might leave the I2C bus in an undesired state.


[2] ALCLR R0W1

0x0 Arbitration Lost Interrupt Flag Clear bit

This bit is clear bit for arbitration lost inter-rupt request flag.

'0': No effect

'1': Clears I2Cn_IBCSR:AL register bit

Reading this bit always returns '0'.

[1] BERCLR R0W1

0x0 Bus Error Interrupt Flag Clear bit

This bit is clear bit for bus error interrupt request flag.

'0': No effect

'1': Clears I2Cn_IBCSR:BER register bit


[0] INTCLR R0W1

0x0 Interrupt Request Flag Clear bit

This bit is clear bit for interrupt request flag.

'0': No effect

'1': Clears I2Cn_IBCSR:INT register bit and I2Cn_IBCSR:AL register bit


Table 3-1116: I2Cn_IEICR Register




I2Cn_DDMACFG

Description: DMA Configuration Register



Table 3-1117: I2Cn_DDMACFG Register





[2] DMAMODE RW 0x0 DMA Mode for Data Registers

This bit is used to enable/disable DMA mode for I2Cn_IODAR:IODAR and I2Cn_ICDIDAR:IDIDAR registers.

'0': I2Cn_IBCSR:INT bit is not cleared at write operation to I2Cn_IODAR:IODAR or read operation from I2Cn_ICDIDAR:IDI-DAR

'1': I2Cn_IBCSR:INT bit is cleared at write operation to I2Cn_IODAR:IODAR or read operation from I2Cn_ICDIDAR:IDIDAR

[1] ENDMAREQTX RW 0x0 DMA Enable bit for Transmission

This bit is used to enable/disable DMA request for transmission.

'0': DMA request for transmission is dis-abled

'1': DMA request for transmission is enabled:

TX DMA request is set if I2Cn_IBCSR:INT gets set, I2Cn_IBCSR:TRX = '1', and I2Cn_IBCSR:AL = '0'.

TX DMA request is cleared when is acknowledged by the DMA controller.




I2Cn_IEIER

Description: Error Interrupt Enable Register



Table 3-1118: I2Cn_IEIER Register



[1] ALEIE RW 0x0 Error Interrupt Enable bit for Arbitration Lost

This bit enables the error interrupt genera-tion (IRQER). It only can be changed by the user.

'0': Error interrupt disabled for arbitration lost

'1': Error interrupt enabled for arbitration lost

Setting this bit to '1' enables error interrupt generation when the I2Cn_IBCSR:AL bit is set to '1' (by the hardware).

[0] BEREIE RW 0x0 Error Interrupt Enable bit for Bus Error

This bit enables the error interrupt genera-tion (IRQER). It only can be changed by the user.

'0': Error interrupt disabled for bus error

'1': Error interrupt enabled for bus error

Setting this bit to '1' enables error interrupt generation when the I2Cn_IBCSR:BER bit is set to '1' (by the hardware).




3.13 U(S)ART-LIN Registers

In this section, the ‘Register Overview’ table summarizes all U(S)ART/LIN registers, including baseaddress of the module and name, description, and the absolute address of each register, which are thendescribed separately in the following tables.


3.13.1 Lin-USART Register Overview




BASEADDR + 0x0000 USARTn_SMR Serial Mode Register

BASEADDR + 0x0001 USARTn_SCR Serial Control Register

BASEADDR + 0x0002 USARTn_SMSR Serial Mode Set Register

BASEADDR + 0x0003 USARTn_SCSR Serial Control Set Register


BASEADDR + 0x0005 USARTn_SCCR Serial Control Clear Register

BASEADDR + 0x0006 USARTn_TDR Transmission Data Register

BASEADDR + 0x0007 USARTn_SSR Serial Status Register

BASEADDR + 0x0008 USARTn_RDR Reception Data Register

BASEADDR + 0x0009 USARTn_SSSR Serial Status Set Register

BASEADDR + 0x000A Reserved Do not modify

BASEADDR + 0x000B USARTn_SSCR Serial Status Clear Register

BASEADDR + 0x000C USARTn_ECCR Extended Communication Control Register

BASEADDR + 0x000D USARTn_ESCR Extended Status/Control Register

BASEADDR + 0x000E USARTn_ECCSR Extended Communication Control Set Register

BASEADDR + 0x000F USARTn_ESCSR Extended Status/Control Set Register

BASEADDR + 0x0010 USARTn_ECCCR Extended Communication Control Clear Register

BASEADDR + 0x0011 USARTn_ESCCR Extended Status/Control Clear Register

BASEADDR + 0x0012 USARTn_ESIR Extended Serial Interrupt Register

BASEADDR + 0x0013 USARTn_EIER Extended Interrupt Enable Register

BASEADDR + 0x0014 USARTn_ESISR Extended Serial Interrupt Set Register

BASEADDR + 0x0015 USARTn_EIESR Extended Interrupt Enable Set Register

BASEADDR + 0x0016 USARTn_ESICR Extended Serial Interrupt Clear Register

BASEADDR + 0x0017 USARTn_EIECR Extended Interrupt Enable Clear Register

BASEADDR + 0x0018 USARTn_EFERL Extended Feature Enable Register L

BASEADDR + 0x0019 USARTn_EFERH Extended Feature Enable Register H

BASEADDR + 0x001A USARTn_RFCR Reception FIFO Control Register

BASEADDR + 0x001B USARTn_TFCR Transmission FIFO Control Register

BASEADDR + 0x001C USARTn_RFCSR Reception FIFO Control Set Register

BASEADDR + 0x001D USARTn_TFCSR Transmission FIFO Control Set Register

BASEADDR + 0x001E USARTn_RFCCR Reception FIFO Control Clear Register

BASEADDR + 0x001F USARTn_TFCCR Transmission FIFO Control Clear Register

BASEADDR + 0x0020 USARTn_RFSR Reception FIFO Status Register

BASEADDR + 0x0021 USARTn_TFSR Transmission FIFO Status Register

BASEADDR + 0x0022 USARTn_CSCR Checksum Status and Control Register

BASEADDR + 0x0023 USARTn_ESR Extended Status Register

BASEADDR + 0x0024 USARTn_CSCSR Checksum Status and Control Set Register


BASEADDR + 0x0026 USARTn_CSCCR Checksum Status and Control Clear Register

BASEADDR + 0x0027 USARTn_ESCLR Extended Status Clear Register

BASEADDR + 0x0028 USARTn_BGRLL Baud Rate Generation Reload Register L

BASEADDR + 0x0029 USARTn_BGRLM Baud Rate Generation Reload Register M

BASEADDR + 0x002A USARTn_BGRLH Baud Rate Generation Reload Register H

BASEADDR + 0x002B Reserved Do not modify

BASEADDR + 0x002C USARTn_BGRL Baud Rate Generation Register L

BASEADDR + 0x002D USARTn_BGRM Baud Rate Generation Register M

BASEADDR + 0x002E USARTn_BGRH Baud Rate Generation Register H



BASEADDR + 0x002F Reserved Do not modify

BASEADDR + 0x0030 USARTn_STXDR Serial Transmit DMA Configuration Register

BASEADDR + 0x0031 USARTn_SRXDR Serial Receive DMA Configuration Register

BASEADDR + 0x0032 USARTn_STXDSR Serial Transmit DMA Configuration Set Register

BASEADDR + 0x0033 USARTn_SRXDSR Serial Receive DMA Configuration Set Register

BASEADDR + 0x0034 USARTn_STXDCR Serial Transmit DMA Configuration Clear Register

BASEADDR + 0x0035 USARTn_SRXDCR Serial Receive DMA Configuration Clear Register

BASEADDR + 0x0036 USARTn_SFTRL Sync Field Timeout Register L

BASEADDR + 0x0037 USARTn_SFTRM Sync Field Timeout Register M

BASEADDR + 0x0038 USARTn_SFTRH Sync Field Timeout Register H


BASEADDR + 0x003A USARTn_FIDR Frame-ID Register

BASEADDR + 0x003B Reserved Do not modify


BASEADDR + 0x003D Reserved Do not modify






USARTn_SMR

Description: Serial Mode Register



Table 3-1120: USARTn_SMR Register


[7:6] MD RW 0x0 Operation Mode Selection

These two bits set the LIN-USART opera-tion mode.

'00': Mode 0: Asynchronous normal

'01': Mode 1: Asynchronous multiprocessor

'10': Mode 2: Synchronous

'11': Mode 3: Asynchronous LIN

Changing the mode bits causes any ongo-ing reception or transmission to be aborted.

[5] OTO RW 0x0 One-to-One External Clock Selection

This bit sets an external clock directly to the LIN-USART's serial clock. This function is used for operating mode 2 (synchronous) slave mode operation.

'0': Use external clock with baud rate gen-erator (reload counter)

'1': Use external clock as it is

[4] EXT RW 0x0 External Clock Selection

This bit selects internal or external clock source for the reload counter.

'0': Use internal baud rate generator (Reload Counter)

'1': Use external serial clock source

[3] REST R0W 0x0 Restart of Transmission Reload Counter

'0': No effect

'1': Reload counter is restarted

Reading from this bit always returns '0'.



[2] UPCL R0W 0x0 LIN-USART Programmable Clear (software reset)

'0': No effect

'1': Resets LIN-USART immediately. The register settings are preserved. Possible reception or transmission will be cut off

This bit also resets TX and RX FIFO block, CRC generation and verification logic, header detection state machine, and sync field detection timeout counter.

All flags are cleared and the Reception Data Register (USARTn_RDR) contains 0x00.

Reading from it always returns '0'.

LIN-USART reset should be performed after disabling the reception and transmis-sion and its interrupt enable bits.


[0] NFEN RW 0x0 Noise Filter Enable for USART_DI pin

'0': Noise filter is not used

'1': Noise filter is used

Note:

When this bit is set to '0', oversampling of USART_DI pin is done depending on the USARTn_EFERL:OSDE bit value.

When this bit is set to '1', additional noise filter is used for USART_DI input and hence oversampling should be disabled, by setting USARTn_EFERL:OSDE bit to '1'.

Table 3-1120: USARTn_SMR Register




USARTn_SCR

Description: Serial Control Register



Table 3-1121: USARTn_SCR Register


[7] PEN RW 0x0 Parity Enable

This bit selects whether to add a parity bit during transmission or detect it during reception.

Parity is provided in mode 0 and in mode 2 if USARTn_ECCR:SSM is selected. This bit is fixed to '0' (no parity) in mode 1 (multi-processor).

'0': Parity disabled

'1': Parity enabled

[6] P RW 0x0 Parity Selection

When parity is provided and enabled this bit selects even or odd parity.

'0': Even parity enabled

'1': Odd parity enabled

[5] SBL RW 0x0 Stop Bit Length Selection

This bit selects the length of the stop bit of an asynchronous data frame or asynchro-nous frame if USARTn_ECCR:SSM is selected. This bit is fixed to '0' (1 stop bit) in mode 3 (LIN).

'0': 1 stop bit

'1': 2 stop bits

[4] CL RW 0x0 Character (Data frame) Length

This bit specifies the length of transmission or reception data. This bit is fixed to '1' (8 bits) in mode 2 and 3.

'0': 7 bits

'1': 8 bits

[3] AD RW 0x0 Address or Data Selection

This bit sets the AD status of transmitted frame in multiprocessor mode 1.

'0': Indicates a usual data frame

'1': Indicates an address frame

When read this bit returns the AD status of transmitted frame in multiprocessor mode 1.



[2] CRE R0W 0x0 Clear Reception Error Flags

This bit clears the flags USARTn_SSR:FRE, USARTn_SSR:ORE, and USARTn_SSR:PE.

It can also reset any ongoing reception depending on USARTn_EFERL:RSTRFM (default is reset).

'0': Has no effect

'1': Clears the error flags


[1] RXE RW 0x0 Reception Enable

This bit enables or disables LIN-USART reception.

'0': LIN-USART disables the reception of data frames

'1': LIN-USART enables the reception of data frames

Note:

If RXE is set to '0' during reception, recep-tion is stopped immediately. In this case, data is not guaranteed.

[0] TXE RW 0x0 Transmission Enable

This bit enables or disables LIN-USART transmission.

'0': LIN-USART disables the transmission of data frames

'1': LIN-USART enables the transmission of data frames

Note:

If TXE is set to '0' during transmission, transmission is stopped immediately. In this case, data is not guaranteed.

Table 3-1121: USARTn_SCR Register




USARTn_SMSR

Description: Serial Mode Set Register



Table 3-1122: USARTn_SMSR Register



[3] RESTS R0W1

0x0 REST Set

'0': No effect

'1': Sets the USARTn_SMR:REST bit


[2] UPCLS R0W1

0x0 UPCL Set

'0': No effect

'1': Sets the USARTn_SMR:UPCL bit





USARTn_SCSR

Description: Serial Control Set Register



Table 3-1123: USARTn_SCSR Register



[3] ADS R0W1

0x0 AD Set

This bit sets the AD bit to be used in trans-mission.

'0': No effect

'1': Indicates an address frame


[2] CRES R0W1

0x0 CRE Set

'0': No effect

'1': Sets the USARTn_SCR:CRE bit


[1] RXES R0W1

0x0 RXE Set

'0': No effect

'1': Sets the USARTn_SCR:RXE bit


[0] TXES R0W1

0x0 TXE Set

'0': No effect

'1': Sets the USARTn_SCR:TXE bit




USARTn_SCCR

Description: Serial Control Clear Register



Table 3-1124: USARTn_SCCR Register



[3] ADC R0W1

0x0 AD Clear

This bit clears the AD bit to be used in transmission.

'0': No effect

'1': Indicates a usual data frame



[1] RXEC R0W1

0x0 RXE Clear

'0': No effect

'1': Clears the USARTn_SCR:RXE bit


[0] TXEC R0W1

0x0 TXE Clear

'0': No effect

'1': Clears the USARTn_SCR:TXE bit




USARTn_TDR

Description: Transmission Data Register



Table 3-1125: USARTn_TDR Register


[7:0] D R0W 0x0 Transmission Data

These bits when written indicates transmis-sion data.

Reading this register always returns '0'.



USARTn_SSR

Description: Serial Status Register



Table 3-1126: USARTn_SSR Register


[7] PE R 0x0 Parity Error Flag

This bit is set to '1' when a parity error occurs during reception.

It is cleared when '1' is written to the USARTn_SCR:CRE.

An error interrupt request is output when this bit and USARTn_ESIR:PEIE bit are '1.

Data in the Reception Data Register (USARTn_RDR) is invalid when this flag is set.

If RX FIFO is enabled (USARTn_RFCR:RXFE = '1') this bit remains '1' till it is cleared by software.

'0': No parity error occurred

'1': A parity error occurred during reception

[6] ORE R 0x0 Overrun Error Flag

This bit is set to '1' when an overrun error occurs during reception.


An error interrupt request is output when this bit and USARTn_ESIR:OREIE bit are 1.


If RX FIFO is enabled (USARTn_RFCR:RXFE = '1') this bit is set when the reception FIFO is full and another data byte is received.

'0': No overrun error occurred

'1': An overrun error occurred during recep-tion



[5] FRE R 0x0 Framing Error Flag

This bit is set to '1' when a framing error occurs during reception.


An error request is output when this bit and USARTn_ESIR:FREIE bit are '1'.


If RX FIFO is enabled (USARTn_RFCR:RXFE = '1') this bit remains '1' till it is cleared by software.

'0': No framing error occurred

'1': A framing error occurred during recep-tion

[4] RDRF R 0x0 Receive Data Register Full Flag

This flag indicates the status of the Recep-tion Data Register (USARTn_RDR).

This bit is set to '1' when reception data is loaded into USARTn_RDR.

It is cleared when the Reception Data Reg-ister (USARTn_RDR) is read.

A reception interrupt request is output when this bit and USARTn_SSR:RIE bit are '1' (when RX FIFO is disabled USARTn_RFCR:RXFE = '0').

A reception interrupt request is output when this bit and USARTn_EIER:RXFIE bit are '1' (when RX FIFO is enabled USARTn_RFCR:RXFE = '1').

When RX FIFO is enabled (USARTn_RFCR:RXFE = '1') this bit is set to '1' when the number of data in the RX FIFO reaches the trigger level programmed in USARTn_RFCR:RXFLC[4:0].

'0': Reception Data Register is empty

'1': Reception Data Register is full

Note: RDRF flag is set on conditions men-tioned above, irrespective of occurrence of any error.

Note: USARTn_ESIR:RDRF has the same behavior as this bit. But it is not cleared when the Reception Data Register (USARTn_RDR) is read.





[3] TDRE R 0x1 Transmission Data Register Empty

This flag indicates the status of the Trans-mission Data Register (USARTn_TDR).

This bit is cleared to '0' when transmission data is written to USARTn_TDR and is set to '1' when data is loaded into the Trans-mission Shift Register and transmission starts.

A transmission interrupt request is gener-ated if both this bit and USARTn_SSR:TIE bit are '1' (when TX FIFO is disabled USARTn_TFCR:TXFE = '0').

A transmission interrupt request is gener-ated if both this bit and USARTn_EIER:TXFIE bit are '1' (when TX FIFO is enabled USARTn_TFCR:TXFE = '1').

If the USARTn_ECCR:LBR is set to '1' while this bit is '1', it changes to '0' and after the completion of LIN sync break genera-tor, this bit changes back to '1'.

When TX FIFO is enabled (USARTn_TFCR:TXFE = '1') the TDRE flag is asserted when the number of data in the TX FIFO reaches the programmed trigger level USARTn_TFCR:TXFLC[4:0].

'0': Transmission Data Register is full

'1': Transmission Data Register is empty

Note:

This bit is set to '1' (USARTn_TDR empty) as its initial value.

USARTn_ESIR:TDRE has the same behavior as this bit. But it is not cleared when transmission data is written to USARTn_TDR.





[2] BDS RW 0x0 Transfer Direction Selection

This bit selects whether to transfer serial data from the least significant bit or from the most significant bit.

'0': LSB first

'1': MSB first

Note:

The high-order and low-order sides of serial data are interchanged with each other during reading from or writing to the Serial Data Register.

If this bit is set to another value after the data is written to the USARTn_RDR regis-ter the data becomes invalid.

This bit is fixed to '0' in mode 3 (LIN mode).

[1] RIE RW 0x0 Receive Interrupt Request Enable

This bit enables or disables the reception interrupt.

If USARTn_SSR:RDRF bit is set and this bit is '1', then a reception interrupt is sig-naled to the Interrupt Controller.

'0': Disables reception interrupt

'1': Enables reception interrupt

Note: If RX FIFO is enabled (TFCRn:RXFE = 1), RIE has no effect on reception inter-rupt generation. Instead EIERn:RXFIE is used to enable or disable reception inter-rupt.

[0] TIE RW 0x0 Transmission Interrupt Request Enable

This bit enables or disables the transmis-sion interrupt.

A transmission interrupt request is output when this bit and USARTn_SSR:TDRE bit are '1'.

This interrupt can be used as replacement of last bit shifted out interrupt (USARTn_EIER:LBSOIE).

Only one of these interrupts should be enabled at the same time.

'0': Disables transmission interrupt

'1': Enables transmission interrupt

Note: If TX FIFO is enabled (TFCRn:TXFE = 1), TIE has no effect on transmission interrupt generation. Instead EIERn:TXFIE is used to enable or disable transmission interrupt.





USARTn_RDR

Description: Reception Data Register



Table 3-1127: USARTn_RDR Register


[7:0] D R 0x0 Received Serial Data

Stores the data received over the serial line.



USARTn_SSSR

Description: Serial Status Set Register



Table 3-1128: USARTn_SSSR Register



[1] RIES R0W1

0x0 RIE Set

'0': No effect

'1': Sets the USARTn_SSR:RIE bit


[0] TIES R0W1

0x0 TIE Set

'0': No effect

'1': Sets the USARTn_SSR:TIE bit




USARTn_SSCR

Description: Serial Status Clear Register


Instance no 0: 0x0009600B

Table 3-1129: USARTn_SSCR Register



[1] RIEC R0W1

0x0 RIE Clear

'0': No effect

'1': Clears the USARTn_SSR:RIE bit


[0] TIEC R0W1

0x0 TIE Clear

'0': No effect

'1': Clears the USARTn_SSR:TIE bit




USARTn_ECCR

Description: Extended Communication Control Register



Table 3-1130: USARTn_ECCR Register


[7] INV RW 0x0 Invert Serial Data

This bit inverts the serial data at USART_DI and USART_DO pin. USART_CLK is not affected (see USARTn_ESCR:SCES).

'0': Serial data is not inverted (NRZ)

'1': Serial data is inverted (NRZI)

[6] LBR R0W 0x0 Generate LIN Sync Break

Writing a '1' to this bit generates a LIN sync break in mode 3 and mode 0.

Length is selected by USARTn_ESCR:LBL[1:0] and USARTn_EFERH:LBL2.

'0': Ignored

'1': Generate LIN break


[5] MS RW 0x0 Master Slave Mode select

This bit selects master or slave mode of LIN-USART in synchronous mode 2.

If master mode is selected LIN-USART generates the synchronous clock by itself.

If slave mode is selected LIN-USART receives external serial clock.

This bit is fixed to '0' in operation mode 0, 1, and 3.

'0': Master mode (generating serial clock)

'1': Slave mode (receiving external serial clock)

Note: If slave mode is selected the clock source must be external and set to 'one-to-one' (USARTn_SMR:EXT = '1' and USARTn_SMR:OTO = '1').



[4] SCDE RW 0x0 Serial Clock Delay Enable

If this bit is set, the serial output clock is delayed.

As shown in Figure 20.8.4, 'Delayed trans-mitting clock signal (SCDE = 1)', if LIN-USART operates in master mode 2.

'0': Disable clock delay

'1': Enable clock delay

This bit is ignored in modes 0, 1, and 3 and read value is '0' in these modes.

[3] SSM RW 0x0 Start_Stop Bit Mode Enable

This bit adds start and stop bits to the syn-chronous data format in operation mode 2.


'0': No start_stop bits in synchronous mode 2

'1': Enable start_stop bits in synchronous mode 2

[2] BIE RW 0x0 Bus Idle Interrupt Enable

This bit enables an interrupt on a bus idle condition.

It enables a transmit interrupt if there is nei-ther reception nor transmission ongoing (USARTn_ECCR:RBI = '1' and USARTn_ECCR:TBI = '1') to indicate that the bus is idle.

Do not use this bit in mode 2 when USARTn_ECCR:MS = '1'.

'0': Disable bus idle interrupt

'1': Enable bus idle interrupt

Note: When using the bus idle interrupt functionality, set USARTn_ESIR:AICD = '1' to prevent that the interrupt is cleared auto-matically when the bus is no longer idle.

[1] RBI R X Reception Bus Idle Flag

This bit is '1' if there is no reception activity on the USART_DI pin.

It is '0' when reception activity is ongoing on the USART_DI pin.


'0': Reception is ongoing

'1': No reception activity





[0] TBI R X Transmission Bus Idle Flag

This bit is '1' if there is no transmission activity on the USART_DO pin.


'0': Transmission is ongoing

'1': No transmission activity





USARTn_ESCR

Description: Extended Status/Control Register


Instance no 0: 0x0009600D

Table 3-1131: USARTn_ESCR Register


[7] LBIE RW 0x0 LIN Sync Break Detection Interrupt Enable

This bit enables or disables LIN sync break interrupt.

LIN sync break interrupt is connected to the receive interrupt.

When in mode 3 the LBD bit is set and this bit is '1' a receive interrupt is signaled to the Interrupt Controller. This bit is fixed to '0' in operation mode 1 and 2.

'0': LIN sync break interrupt disable

'1': LIN sync break interrupt enable

[6] LBD R 0x0 LIN Sync Break Detected Flag

This bit goes '1' if a LIN sync break was detected in operating mode 3.

It is recommended to write '0' to the USARTn_SCR:RXE before using this bit.

'0': No LIN sync break detected

'1': LIN sync break detected

[5:4] LBL RW 0x0 LIN Sync Break Length Selection

These two bits determine how many serial bit times the LIN sync break is generated by LIN-USART. Receiving a LIN sync break is always fixed to 11-bit times.

During transmission the LIN break length can be varied from 13 to 20 bits times using these two bits and USARTn_EFERH:LBL2 bit as msb. The table for various LIN break length configuration is given below.

{LBL2 LBL1 LBL0}: LIN break length

'000': 13 bit times

'001': 14 bit times

'010': 15 bit times

'011': 16 bit times

'100': 17 bit times

'101': 18 bit times

'110': 19 bit times

'111': 20 bit times



[3] SOPE RW 0x0 Serial Output Pin Direct Access Enable

Setting this bit to 1 enables the direct write to the USART_DO pin.

'0': Serial Output Pin Direct Access disable

'1': Serial Output Pin Direct Access enable

[2] SIOP R 0x1 Serial Input Output Pin Direct Access

Reading this bit always returns the actual value of the USART_DI pin.

This is a read-only bit, writing has no effect.

[1] CCO RW 0x0 Continuous Clock Output Enable

This bit enables a continuous serial clock at the USART_CLK pin if LIN-USART oper-ates in master mode 2 (synchronous) and the USART_CLK pin is configured as a clock output.

'0': Continuous clock output disabled

'1': Continuous clock output enabled

Note: When this bit is '1' use USARTn_ECCR:SSM bit as set to '1'.

[0] SCES RW 0x0 Serial Clock Edge Select

This bit inverts the serial clock signal in operation mode 2 (synchronous communi-cation).

Receiving data is sampled at the falling edge of the internal clock when USARTn_ECCR:SCDE = 0.

If USARTn_ECCR:MS register is '0' (mas-ter mode) the output clock signal is also inverted.


'0': Sampling on rising clock edge (normal)

'1': Sampling on falling clock edge (inverted clock) when USARTn_ECCR:SCDE is set to '0'

Table 3-1131: USARTn_ESCR Register




USARTn_ECCSR

Description: Extended Communication Control Set Register


Instance no 0: 0x0009600E

Table 3-1132: USARTn_ECCSR Register



[6] LBRS R0W1

0x0 LBR Set

'0': No effect

'1': Sets the USARTn_ECCR:LBR bit



[2] BIES R0W1

0x0 BIE Set

'0': No effect

'1': Sets the USARTn_ECCR:BIE bit





USARTn_ESCSR

Description: Extended Status/Control Set Register


Instance no 0: 0x0009600F

Table 3-1133: USARTn_ESCSR Register


[7] LBIES R0W1

0x0 LBIE Set

'0': No effect

'1': Sets the USARTn_ESCR:LBIE bit



[2] SIOPS R0W1

0x0 USART_DO Pin Set

'0': No effect

'1': Sets the USART_DO pin to '1'




mb88f33x ‘indigo2(-x)’ - fujitsu...0-06 27.02.2013 rvr minor changes, more formatting issues....

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