may 8, 20012 usb 2.0 technical overview brad hosler usb engineering manager intel corporation
TRANSCRIPT
May 8, 2001 2
USB 2.0 Technical Overview
USB 2.0 Technical Overview
Brad HoslerBrad Hosler
USB Engineering ManagerUSB Engineering Manager
Intel CorporationIntel Corporation
May 8, 2001 3
Conference GoalConference Goal
Provide you with the information youProvide you with the information youneed to build USB 2.0 productsneed to build USB 2.0 products– USB 2.0 technical detailsUSB 2.0 technical details– USB 2.0 InfrastructureUSB 2.0 Infrastructure– Building USB 2.0 devicesBuilding USB 2.0 devices– USB 2.0 Building BlocksUSB 2.0 Building Blocks
May 8, 2001 4
USB 2.0: Conference AgendaUSB 2.0: Conference Agenda
Architecture OverviewArchitecture Overview– Peripheral Development EnablingPeripheral Development Enabling– Hi-speed powerHi-speed power– Hi-speed performanceHi-speed performance
Microsoft SW UpdateMicrosoft SW Update USB 2.0 Compliance and Logo ProgramUSB 2.0 Compliance and Logo Program USB 2.0 Compliance TestingUSB 2.0 Compliance Testing
Single Track: Topics for EveryoneSingle Track: Topics for Everyone
May 8, 2001 5
Split Track: Focused TopicsSplit Track: Focused TopicsUSB 2.0: Technical AgendaUSB 2.0: Technical Agenda
USB2 SpecificationsUSB2 Specifications– ElectricalsElectricals– ProtocolProtocol– HubsHubs
Power ManagementPower Management Host Controller SpecHost Controller Spec
– Compliance testingCompliance testing Cable TestingCable Testing USB “On the Go”USB “On the Go”
USB2 SoftwareUSB2 Software– Writing Quality DriversWriting Quality Drivers– HS Isoch InterfaceHS Isoch Interface
Building USB2 DevicesBuilding USB2 Devices Design OptionsDesign Options Transceiver MacrocellTransceiver Macrocell AnalyzersAnalyzers
Platform DesignPlatform Design BIOS considerationsBIOS considerations
May 8, 2001 6
ArchitectureOverview
ArchitectureOverview
May 8, 2001 7
USB 2.0: What Changed??USB 2.0: What Changed??
Low level electricals for High Speed (HS) Low level electricals for High Speed (HS) signalingsignaling– Much higher bit rate (480Mb/s) requires new Much higher bit rate (480Mb/s) requires new
transmitter/receiver transmitter/receiver Hub changes for backward compatibilityHub changes for backward compatibility
– Features limit bandwidth impact of Full Speed (FS)Features limit bandwidth impact of Full Speed (FS)and Low Speed (LS) devices on HS devicesand Low Speed (LS) devices on HS devices
– FS/LS devices consume a bit-rate equivalentFS/LS devices consume a bit-rate equivalentof HS bandwidthof HS bandwidth
Architecture OverviewArchitecture Overview
May 8, 2001 8
USB 2.0: What Didn’t Change?USB 2.0: What Didn’t Change?
Same host/device modelSame host/device model– Host is in chargeHost is in charge– Devices are inexpensiveDevices are inexpensive
Same basic protocolSame basic protocol– Token, data, handshakeToken, data, handshake
Same device frameworkSame device framework– DescriptorsDescriptors
Same software interfacesSame software interfaces– USBDIUSBDI
Architecture OverviewArchitecture Overview
May 8, 2001 9
Same power distribution and consumptionSame power distribution and consumption– 500ua suspend, 100ma unconfigured,500ua suspend, 100ma unconfigured,
500ma configured500ma configured Same power management featuresSame power management features
– Suspend/resume model unchangedSuspend/resume model unchanged Same topology managementSame topology management
– Hub features to handle connect, disconnect,Hub features to handle connect, disconnect,enable, disable, …enable, disable, …
Same cables and connectorsSame cables and connectors
ContinuedContinued
Architecture OverviewArchitecture Overview
USB 2.0: What Didn’t Change?USB 2.0: What Didn’t Change?
May 8, 2001 10
System SWSystem SW
Client DriverClient Driver Client DriverClient Driver
USB 1.1 HubUSB 1.1 Hub
USB 1.1 USB 1.1 DeviceDevice
USB 1.1 USB 1.1 DeviceDevice
HS HubHS HubHS HubHS Hub
USB 1.1 HubUSB 1.1 Hub
USB 1.1 USB 1.1 DeviceDevice
USB 1.1 USB 1.1 DeviceDevice
HS DeviceHS DeviceHS DeviceHS Device
USB 2.0 HostUSB 2.0 HostControllerController
USB 2.0 HostUSB 2.0 HostControllerController
Full/Low SpeedFull/Low Speed
High Speed OnlyHigh Speed Only
(2 x 12Mb/s(2 x 12Mb/sCapacity)Capacity)
Sample USB 2.0 TopologySample USB 2.0 Topology
Hub provides high-speed expansion (ala USB 1.1 hub)Hub provides high-speed expansion (ala USB 1.1 hub) Hub provides additional Full/Low speed bus(es)Hub provides additional Full/Low speed bus(es)
Architecture OverviewArchitecture Overview
May 8, 2001 11
USB 2.0 Host ControllerUSB 2.0 Host Controller
Allows port functionality regardless of OS versionAllows port functionality regardless of OS version– USB 1.1 OS will ‘just work’ as USB 1.1 portsUSB 1.1 OS will ‘just work’ as USB 1.1 ports
USB 1.1 HCs can go away over timeUSB 1.1 HCs can go away over time– Replaced with integrated USB 2.0 HubReplaced with integrated USB 2.0 Hub
Architecture OverviewArchitecture Overview
USB 2.0 Host Controller (HC)
Port 1
USB 1.1 USB 1.1 HCsHCsHigh-Speed ModeHigh-Speed Mode
(Enhanced Interface) USB HC(Enhanced Interface) USB HC
Port 1 Port 2
Port OwnerPort OwnerControl(s)Control(s)
Port 1 Port 2
Port Routing Logic
Port N
HC Control Logic/Data BufferingEnhanced HC Control Logic
Enhanced Data Buffering
Port 2 Port N
Port N
May 8, 2001 12
USB 2.0 HubUSB 2.0 Hub
Hub controller same as USB1.1Hub controller same as USB1.1 Routing logic connects device to appropriate pathRouting logic connects device to appropriate path
TransactionTransactionTranslatorTranslator
TransactionTransactionTranslatorTranslator
PortPortPortPortRouting LogicRouting LogicRouting LogicRouting Logic
HS SignalHS SignalRepeaterRepeater
HS SignalHS SignalRepeaterRepeater
HubHubControllerController
HubHubControllerController
PortPortPortPortPortPortPortPort PortPortPortPort
High Speed onlyHigh Speed only
Full/LowFull/LowSpeedSpeed
Architecture OverviewArchitecture Overview
May 8, 2001 13
Transaction Translator (TT)Transaction Translator (TT)
TT handles low/full speed transactionsTT handles low/full speed transactions– Driven with split transactionsDriven with split transactions
Start-SplitStart-Split– Host tells Hub to initiate full/low speed transactionHost tells Hub to initiate full/low speed transaction
Complete-SplitComplete-Split– Host asks Hub for results of previous full/lowHost asks Hub for results of previous full/low
speed transactionspeed transaction
Architecture OverviewArchitecture Overview
May 8, 2001 14
Bandwidth UsageBandwidth Usage
Low/full speed devices use bit-rate equivalent of Low/full speed devices use bit-rate equivalent of USB2.0 bandwidthUSB2.0 bandwidth– 6Mbps classic camera (50% of classic) uses less than 6Mbps classic camera (50% of classic) uses less than
2% of USB2.0 bandwidth (6Mbps/480Mbps)2% of USB2.0 bandwidth (6Mbps/480Mbps)
Architecture OverviewArchitecture Overview
May 8, 2001 15
ISOCH IN through a TTISOCH IN through a TT
HS Bus
Full Speed Bus
uSOF
1ms
uSOF uSOF uSOF uSOF uSOF uSOF uSOF uSOF
SOF SOF
SS
SS = Start Split
CS CS CS CS
125us
CS = Complete Split
Architecture OverviewArchitecture Overview
May 8, 2001 16
SummarySummary
Two major changes for USB 2.0Two major changes for USB 2.0– Higher speed electricalsHigher speed electricals– Transaction translator in USB2.0 hubTransaction translator in USB2.0 hub
Backward compatibilityBackward compatibility– All Full/Low-speed devices continue to workAll Full/Low-speed devices continue to work– Has little impact on HS bandwidthHas little impact on HS bandwidth
Architecture OverviewArchitecture Overview
May 8, 2001 17
Enabling Peripheral Development
Enabling Peripheral Development
May 8, 2001 18
USB 2.0 HC CardsUSB 2.0 HC Cards
PCI and PCCard versionsPCI and PCCard versions– Use NEC siliconUse NEC silicon– Full EHCI implementationFull EHCI implementation
Available in retailAvailable in retail– Frys, Circuit City, …Frys, Circuit City, …– www.orangemicro.com,www.orangemicro.com,
www.adaptec.com, …www.adaptec.com, …
Peripheral EnablingPeripheral Enabling
May 8, 2001 19
Driver SoftwareDriver Software
HC driver for Windows 2000 and Windows XPHC driver for Windows 2000 and Windows XP– Available at www.usb.org for member companiesAvailable at www.usb.org for member companies
Drivers provide full functionalityDrivers provide full functionality– All high-speed transfer typesAll high-speed transfer types– Full support for USB 2.0 hub transaction translatorFull support for USB 2.0 hub transaction translator
Drivers are for development use onlyDrivers are for development use only– Cannot be shipped with productsCannot be shipped with products
Peripheral EnablingPeripheral Enabling
May 8, 2001 20
Single Transaction ToolSingle Transaction Tool
Software application for generating individual Software application for generating individual high-speed transactionshigh-speed transactions
Very useful for early device debugVery useful for early device debug Doesn’t require a device to enumerateDoesn’t require a device to enumerate Any type of transaction can be generatedAny type of transaction can be generated
– Including individual parts of Control transfersIncluding individual parts of Control transfers Available at www.usb.orgAvailable at www.usb.org
Peripheral EnablingPeripheral Enabling
May 8, 2001 21
Transceiver MacrocellTransceiver Macrocell
ASICASICASICASIC
Serial Interface EngineSerial Interface EngineSerial Interface EngineSerial Interface Engine
DeviceDeviceSpecificSpecific
LogicLogic
DeviceDeviceSpecificSpecific
LogicLogic
Endpoint Logic
Endpoint Logic
…SIE
Control Logic
USB 2.0USB 2.0Endpoint Logic
Device Device HardwareHardware
USB 2.0 USB 2.0 TransceiverTransceiver
USB 2.0 USB 2.0 TransceiverTransceiver
Defines Standard Interfacefor Transceiver Macrocell
Defines Standard Interfacefor Transceiver Macrocell
USB 2.0 Transceiver Macrocell Interface (UTMI) USB 2.0 Transceiver Macrocell Interface (UTMI) http://developer.intel.com/technology/usb/spec.htmhttp://developer.intel.com/technology/usb/spec.htm
Broad Industry supportBroad Industry support Discrete versions availableDiscrete versions available
Peripheral EnablingPeripheral Enabling
May 8, 2001 22
VHDL (IP) CoresVHDL (IP) Cores
ASICASICASICASIC
Serial Interface EngineSerial Interface EngineSerial Interface EngineSerial Interface Engine
DeviceDeviceSpecificSpecific
LogicLogic
DeviceDeviceSpecificSpecific
LogicLogic
Endpoint Logic
Endpoint Logic
…SIE
Control Logic
USB 2.0USB 2.0Endpoint Logic
Device Device HardwareHardware
USB 2.0 USB 2.0 TransceiverTransceiver
USB 2.0 USB 2.0 TransceiverTransceiver
Tran-Tran-sceiversceiver
ProductProductFunctionFunction
USB 2.0USB 2.0
3rd Party VHDL3rd Party VHDL
Peripheral EnablingPeripheral Enabling
May 8, 2001 23
Building BlocksBuilding Blocks
MicrocontrollersMicrocontrollers– CypressCypress
Interface chipsInterface chips– NetchipNetchip
IDE/ATAPI bridgesIDE/ATAPI bridges– In-System Design, NECIn-System Design, NEC
ENET 10/100 BridgeENET 10/100 Bridge– Kawasaki LSIKawasaki LSI
UTMI macro cellsUTMI macro cells– Seiko-Epson, Kawasaki LSISeiko-Epson, Kawasaki LSI
UTMI TransceiversUTMI Transceivers– Lucent, Kawasaki LSILucent, Kawasaki LSI
Peripheral EnablingPeripheral Enabling
May 8, 2001 24
Bus AnalyzersBus Analyzers
Available nowAvailable now CatalystCatalyst
– http://www.catalyst-ent.comhttp://www.catalyst-ent.com CATCCATC
– http://www.catc.comhttp://www.catc.com Crescent HeartCrescent Heart
– http://www.c-h-s.comhttp://www.c-h-s.com Data TransitData Transit
– http://www.data-transit.comhttp://www.data-transit.com
Peripheral EnablingPeripheral Enabling
May 8, 2001 25
Peripheral Integration LabPeripheral Integration Lab
Integration lab at Intel’s Architecture LabsIntegration lab at Intel’s Architecture Labsin Oregonin Oregon– Multiple hosts and devices (interop testing)Multiple hosts and devices (interop testing)– Test equipment (scopes, analyzers, TDRs, etc.)Test equipment (scopes, analyzers, TDRs, etc.)– Expert help from HW and SW engineersExpert help from HW and SW engineers– Compliance testingCompliance testing– Platforms and host controllers welcome tooPlatforms and host controllers welcome too
Available to anyone planning on deliveringAvailable to anyone planning on deliveringUSB 2.0 device in 2001USB 2.0 device in 2001
Peripheral EnablingPeripheral Enabling
May 8, 2001 26
Hi-Speed Power Issues
Hi-Speed Power Issues
May 8, 2001 27
Power RequirementsPower Requirements
Suspended - ~2.5maSuspended - ~2.5ma Configured - 500maConfigured - 500ma UnConfigured - 100maUnConfigured - 100ma
Examine each of these from a hi-speed device and Examine each of these from a hi-speed device and infrastructure (host, hub, cable) perspectiveinfrastructure (host, hub, cable) perspective
Hi-Speed PowerHi-Speed Power
May 8, 2001 28
Suspend CurrentSuspend Current
Device: Device: – Device is always in FS mode, HS clocks are offDevice is always in FS mode, HS clocks are off– Implementations should be similar to current solutionsImplementations should be similar to current solutions
Host/Hub: Host/Hub: – Important for Instantly Available PCsImportant for Instantly Available PCs– Dual-mode power supplies are sized to provide power Dual-mode power supplies are sized to provide power
to USB port when machine is ‘sleeping’to USB port when machine is ‘sleeping’– ‘‘Don’t care’ for hubs and cablesDon’t care’ for hubs and cables
Hi-Speed PowerHi-Speed Power
May 8, 2001 29
Configured CurrentConfigured Current
Device:Device:– Hi-speed transceivers tend to consume more powerHi-speed transceivers tend to consume more power– Less power available for device functionLess power available for device function
Host/Hub: Host/Hub: – Power supplies sized to support thisPower supplies sized to support this– Cable conductors sized for appropriate IR dropCable conductors sized for appropriate IR drop
Hi-Speed PowerHi-Speed Power
May 8, 2001 30
Unconfigured CurrentUnconfigured Current
Device:Device:– Hi-speed transceiver can consume most of budgetHi-speed transceiver can consume most of budget– Difficult to build bus-powered hi-speed devicesDifficult to build bus-powered hi-speed devices
Host/Hub:Host/Hub:– Important for bus-powered hubsImportant for bus-powered hubs
Four downstream ports at 100ma eachFour downstream ports at 100ma each– ‘‘Don’t care’ for hosts, self-powered hubs, and cablesDon’t care’ for hosts, self-powered hubs, and cables
Hi-Speed PowerHi-Speed Power
May 8, 2001 31
IssuesIssues
We like bus-powered devicesWe like bus-powered devices– This is an essential characteristic for productsThis is an essential characteristic for products
Is the 100ma limit really a problem?Is the 100ma limit really a problem?– Transmit/receive differencesTransmit/receive differences
Device is >99% receiving when unconfiguredDevice is >99% receiving when unconfigured Would increasing to 150ma be enough?Would increasing to 150ma be enough?
– Impacts bus-powered hubsImpacts bus-powered hubs Limited to two ports (300ma for ports, 200 for hub silicon)Limited to two ports (300ma for ports, 200 for hub silicon)
– Any other impacts?Any other impacts?
Comments/suggestions to [email protected]/suggestions to [email protected]/suggestions to [email protected]/suggestions to [email protected]
Hi-Speed PowerHi-Speed Power
May 8, 2001 32
Hi-Speed Detection Handshake
Hi-Speed Detection Handshake
May 8, 2001 33
Downstream PortsDownstream Ports
Port is driving Port is driving RESETRESET
Port must detect Port must detect 2.5us ChirpK 2.5us ChirpK starting from 2.5us starting from 2.5us after asserting after asserting RESET until 7ms RESET until 7ms after asserting after asserting RESETRESET
Hi-Speed HandshakeHi-Speed Handshake
Device turns onHS termination
Reset
May 8, 2001 34
Upstream PortsUpstream Ports
Two cases: Reset from FS and reset from HSTwo cases: Reset from FS and reset from HS Both casesBoth cases
– ChirpK must be at least 1ms in duration and must be ChirpK must be at least 1ms in duration and must be complete within 7ms after RESET begancomplete within 7ms after RESET began
Reset from FSReset from FS– Device must start ChirpK sometime between 2.5us and Device must start ChirpK sometime between 2.5us and
6ms after detecting RESET6ms after detecting RESET Reset from HSReset from HS
– After device sees SE0 for 3ms and reverts to FS After device sees SE0 for 3ms and reverts to FS terminations, then does ChirpK if there is still an SE0terminations, then does ChirpK if there is still an SE0
Hi-Speed HandshakeHi-Speed Handshake
May 8, 2001 35
Reset from HSReset from HSHi-Speed HandshakeHi-Speed Handshake
μSOFμSOF Device ChirpDevice Chirp Hub ChirpHub Chirp
D+
D–
3.0-3.125 ms 100-875 μs > 1.0 ms
< 7.0 ms
< 100 μs 100-500 μs
> 10 ms
Device Chirp
Start ofReset
Device EntersHS < 500 UsAfter DetectingHub Chirp
Start ofReset
End ofReset
End ofHub Chirp
Start ofHub Chirp
μSOFμSOF
Hub
Dev
ice
SE0SE0 SE0SE0SE0SE0 HS idleHS idle
Devicegoes
into FS
Devicetests for
SE0
May 8, 2001 36
Hi-Speed USB Performance
Hi-Speed USB Performance
May 8, 2001 37
Mass Storage PerformanceMass Storage Performance
Standard IDE drive connected through different meansStandard IDE drive connected through different means
ConnectionConnection ReadRead(MB/s)(MB/s)
WriteWrite(MB/s)(MB/s)
Seek TimeSeek Time(msec)(msec)
USB 2.0USB 2.0 12.112.1 9.99.9 13.513.5
USB 1.1USB 1.1 0.920.92 0.880.88 15.415.4
IDE same busIDE same bus 2.12.1 2.02.0 14.214.2
IDE separate busIDE separate bus 15.115.1 13.613.6 12.312.3
Data provided by In System Design.
Values measured with HD Tach 2.61, 30GB IBM drive, 333Mhz PIII system, 320MB RAM
Hi-Speed USB PerformanceHi-Speed USB Performance
May 8, 2001 38
Mass Storage PerformanceMass Storage Performance
Benchmark comparison of USB 2.0 high-speed Benchmark comparison of USB 2.0 high-speed USB drive with IDE driveUSB drive with IDE drive
BenchmarkBenchmark PIO-3PIO-3 PIO-4PIO-4 UDMAUDMA USB1USB1
Business Disk Business Disk WinMark 99WinMark 99 105%105% 106%106% 90%90% 260%260%
High-End Disk High-End Disk WinMark 99WinMark 99 155%155% 154%154% 95%95% 534%534%
Data provided by Quantum Corp.
Hi-Speed USB PerformanceHi-Speed USB Performance
May 8, 2001 39
USB1USB1 IDEIDE USB2USB2
‘‘Rip’ an audio CDRip’ an audio CD 15m 15m 6m 40s 6m 40s 3m 15s3m 15s
Write an audio CDWrite an audio CD 24m 24m 6m 10s6m 10s 4m 20s4m 20s
CD/RW PerformanceCD/RW Performance
Time comparison for reading and writing an audio CDTime comparison for reading and writing an audio CD
Time to copy data CD: 6m 28sTime to copy data CD: 6m 28s– USB2 to USB2USB2 to USB2
P4 system, 128MB, 1.3GHz . TDK 16/10/40 CDRW. In System IDE bridge.
Hi-Speed USB PerformanceHi-Speed USB Performance
May 8, 2001 40
SummarySummary
Everything you need to develop USB2 productsEverything you need to develop USB2 productsis availableis available– Tools, host controllers, building blocks, analyzersTools, host controllers, building blocks, analyzers
Building bus-powered high-speed productsBuilding bus-powered high-speed productsis difficultis difficult– Is a change to unconfigured power limit needed?Is a change to unconfigured power limit needed?
High-speed products deliver great performanceHigh-speed products deliver great performance– Comparable to ‘inside-the-box’ performanceComparable to ‘inside-the-box’ performance