Low Power, 18 MHz Variable Gain Amplifier Data Sheet AD8338

Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES Voltage controlled gain range of 0 dB to 80 dB 3 mA supply current at gain of 40 dB Low frequency (LF) to 18 MHz operation Supply range: 3.0 V to 5.0 V Adjustable gain range Low noise: 4.5 nV/√Hz Fully differential signal path Offset correction (offset null) feature Adjustable bandwidth Internal 1.5 V reference 16-lead LFCSP Automatic gain control feature Wide gain range for high dynamic range signals

APPLICATIONS Front end for inductive telemetry systems Ultrasonic signal receivers RF baseband signal conditioning

GENERAL DESCRIPTION The AD8338 is a variable gain amplifier (VGA) for applications that require a fully differential signal path, low power, low noise, and a well-defined gain over frequencies from LF to 18 MHz. The device can also operate using single-ended sources if required.

The basic gain function is linear-in-dB with a nominal gain range of 0 dB to 80 dB; the nominal gain range corresponds to a control voltage on the GAIN pin of 0.1 V to 1.1 V. The gain range can be adjusted up or down via direct access to the internal summing nodes at the INPD and INMD pins. For example, if a 47 Ω resistor is applied to the INPD and INMD pins, a gain range of 20 dB to 100 dB is set with an input referred noise level of 1.5 nV√Hz.

The AD8338 includes additional circuits to enable offset correction and automatic gain control (AGC). DC offset voltages are removed by the offset correction circuit, which behaves like a high-pass filter. The high-pass filter corner frequency is set using an external capacitor. The AGC function varies the gain of the AD8338 to maintain a constant rms output voltage. A user supplied voltage controls the target output rms voltage. A user supplied capacitor to ground at the DETO pin controls the response time of the AGC circuit.

FUNCTIONAL BLOCK DIAGRAM

INPR

INPD

INMD

INMR

MODECOMM GAIN

FBKM

OUTP

OUTM

DETO VAGC

FBKP

+

–

+

–

VREF

VGA CORE

0dB TO 80dB

OFFSET NULL

OUTPUTSTAGE

0dB

OFSN VREFVBAT

AUTOMATICGAIN

CONTROL

GAIN INTERFACE

AD8338

1127

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1

Figure 1.

100

–40

–20

0

20

40

60

80

10k 100M10M1M100k

GA

IN (d

B)

FREQUENCY (Hz)

VGAIN = 0.1VVGAIN = 0.2VVGAIN = 0.3VVGAIN = 0.4VVGAIN = 0.5VVGAIN = 0.6VVGAIN = 0.7VVGAIN = 0.8VVGAIN = 0.9VVGAIN = 1.0VVGAIN = 1.1V

1 127

9-00

5

Figure 2. Gain vs. Frequency

The AD8338 offers additional versatility by allowing user access to the internal summing nodes. With a few discrete components, users can customize the gain, bandwidth, input impedance, and noise profile of the part to fit their application.

The AD8338 uses a single supply voltage of 3.0 V to 5.0 V and is very power efficient, consuming as little as 3 mA quiescent current. The AD8338 is available in a 3 mm × 3 mm, RoHS compliant, 16-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.

AD8338 Data Sheet

Rev. 0 | Page 2 of 16

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3

AC Specifications .......................................................................... 3 Absolute Maximum Ratings ............................................................ 4

Thermal Resistance ...................................................................... 4 ESD Caution .................................................................................. 4

Pin Configuration and Function Descriptions ............................. 5 Typical Performance Characteristics ............................................. 6

Theory of Operation ...................................................................... 12 Getting Started with the AD8338 ............................................. 12 Offset Correction Circuit .......................................................... 12 Explanation of the Gain Function ............................................ 12 AGC Circuit ................................................................................ 13 Adjusting the Output Common-Mode Voltage ..................... 14

Applications Information .............................................................. 15 Simple On-Off Keyed (OOK) Receiver ................................... 15 Interfacing the AD8338 to an ADC ......................................... 15

Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16

REVISION HISTORY 4/13—Revision 0: Initial Version

Data Sheet AD8338

Rev. 0 | Page 3 of 16

SPECIFICATIONS AC SPECIFICATIONS VBAT = 3.0 V, TA = 25°C, CL = 2 pF on OUTP and OUTM, RL = ∞, MODE pin high, RIN = 2 × 500 Ω, VGAIN = 0.6 V, differential operation, unless otherwise noted.

Table 1. Parameter Test Conditions/Comments Min Typ Max Unit INPUT INTERFACE

Gain Range Standard configuration using the INPR and INMR inputs

0 80 dB

Gain Span 80 dB Input Voltage Range 3 V p-p Input 1 dB Compression Differential input, VCM = 1.5 V,

gain = 0.1 V/0 dB

f = 400 kHz 2.2 V p-p f = 1 MHz 2 V p-p f = 4 MHz 1.6 V p-p f = 10 MHz 0.75 V p-p −3 dB Bandwidth 18 MHz Gain Accuracy Standard configuration using the INPR

and INMR inputs; 0.1 V < VGAIN < 1.1 V −2 +0.5 +2 dB

Input Resistance Standard configuration using the INPR and INMR inputs

0.8 1 1.2 kΩ

Input Capacitance 2 pF OUTPUT INTERFACE OUTP and OUTM pins

Small Signal Bandwidth VGAIN = 0.6 V 18 MHz Peak Slew Rate VGAIN = 0.6 V 50 V/μs Peak-to-Peak Output Swing Differential output 2.8 V p-p Common-Mode Voltage 1.5 V Input-Referred Noise Voltage Standard configuration using the INPR

and INMR inputs 4.5 nV/√Hz

Driving external 47 Ω input resistors connected to INPD and INMD

1.5 nV/√Hz

Offset Voltage RTO, VGAIN = 0.1 V, offset null on −10 +10 mV RTO, VGAIN = 0.6 V, offset null on −10 +10 mV RTO, VGAIN = 0.1 V, offset null off −50 +50 mV RTO, VGAIN = 0.6 V, offset null off −200 +200 mV

POWER SUPPLY VBAT 3.0 5.0 V IVBAT Min gain, VGAIN = 0.1 V 6.0 8.0 mA Mid gain, VGAIN = 0.6 V 3.0 3.8 mA Max gain, VGAIN = 1.1 V 4.5 6.0 mA

GAIN CONTROL Gain Voltage 0.1 1.1 V Gain Slope 77 80 83 dB/V 12.5 mV/dB

VREF ACCURACY VREF = 1.5 V 2 % DETO OUTPUT CURRENT ±10 μA AGC CONTROL MODE = 0 V

Maximum Target Amplitude Expected rms output value for target = VAGC − VREF = 1.0 V

1.0 V rms

AD8338 Data Sheet

Rev. 0 | Page 4 of 16

ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating VBAT to COMM −0.3 V to +5.5 V INPR, INPD, INMD, INMR, MODE, GAIN,

FBKM, FBKP, OUTM, OUTP, VAGC, VREF, OFSN

COMM to VBAT

Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 3. Thermal Resistance Package Type θJA Unit 16-Lead LFCSP 48.75 °C/W

ESD CAUTION

Data Sheet AD8338

Rev. 0 | Page 5 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1INPR2INPD3INMD4INMR

11 OUTP12 FBKP

10 OUTM9 FBKM

5C

OM

M6

MO

DE

7G

AIN

8D

ETO

15VB

AT

16VR

EF

14O

FSN

13VA

GC

AD8338TOP VIEW

(Not to Scale)

NOTES1. THE EXPOSED PAD SHOULD BE TIED

TO A QUIET ANALOG GROUND. 1127

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Figure 3. Pin Configuration

Table 4. Pin Function Descriptions Pin No. Mnemonic Description 0 EPAD Exposed Pad. The exposed pad should be tied to a quiet analog ground. 1 INPR Positive 500 Ω Resistor Input for Voltage Input Applications. 2 INPD Positive Input for Current Input Applications. 3 INMD Negative Input for Current Input Applications. 4 INMR Negative 500 Ω Resistor Input for Voltage Input Applications. 5 COMM Ground. 6 MODE Gain Mode. This pin selects positive or negative gain slope for gain control. When this pin is tied to VBAT, the

gain of the AD8338 increases proportionally with an increase of the voltage on the GAIN pin. When this pin is tied to COMM, the gain decreases with an increase of the voltage on the GAIN pin.

7 GAIN Gain Control Input, 12.5 mV/dB or 80 dB/V. 8 DETO Detector Output Terminal, ±10 µA. If the AGC feature is not used, tie this pin to COMM. 9 FBKM Negative Feedback Node. For more information, see the Adjusting the Output Common-Mode Voltage section. 10 OUTM Negative Output. 11 OUTP Positive Output. 12 FBKP Positive Feedback Node. For more information, see the Adjusting the Output Common-Mode Voltage section. 13 VAGC Voltage for Automatic Gain Control Circuit. This pin controls the target rms output voltage for the AGC circuit.

For more information, see the AGC Circuit section. 14 OFSN Offset Null Terminal. For more information, see the Offset Correction Circuit section. 15 VBAT Positive Supply Voltage. 16 VREF Internal 1.5 V Voltage Reference.

AD8338 Data Sheet

Rev. 0 | Page 6 of 16

TYPICAL PERFORMANCE CHARACTERISTICS

80

0

10

20

30

40

50

60

70

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

GA

IN (d

B)

VGAIN (V)

MODE PIN LOW MODE PIN HIGH

1127

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3

Figure 4. Gain vs. VGAIN

80

0

10

20

30

40

50

60

70

NU

MB

ER O

F H

ITS

GAIN SLOPE (dB/V)78.0 78.3 78.6 78.9 79.2 79.5 79.8 80.1 80.4

1127

9-10

5

Figure 5. Gain Slope Histogram

100

–40

–20

0

20

40

60

80

10k 100M10M1M100k

GA

IN (d

B)

FREQUENCY (Hz)

VGAIN = 0.1VVGAIN = 0.2VVGAIN = 0.3VVGAIN = 0.4VVGAIN = 0.5VVGAIN = 0.6VVGAIN = 0.7VVGAIN = 0.8VVGAIN = 0.9VVGAIN = 1.0VVGAIN = 1.1V

1127

9-10

6

Figure 6. Gain vs. Frequency

80

–60

–40

–20

0

20

40

60

100k 1M 10M 100M

GA

IN (d

B)

FREQUENCY (Hz)

VGAIN = 100mV

VGAIN = 350mV

VGAIN = 600mV

1127

9-10

9

Figure 7. Gain vs. Frequency, RIN = 50 Ω

80

–80

–60

–40

–20

0

20

40

60

100k 1M 10M 100M

GA

IN (d

B)

FREQUENCY (Hz)

VGAIN = 100mV

VGAIN = 350mV

VGAIN = 600mV

VGAIN = 850mV

VGAIN = 1100mV

1127

9-10

7

Figure 8. Gain vs. Frequency, RIN = 5 kΩ

5

–5

–4

–3

–2

–1

0

1

2

3

4

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

GA

IN E

RR

OR

(dB

)

VGAIN (V)

–40°C

+25°C

+85°C

+105°C

VS = 3Vf = 1MHz

1127

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6

Figure 9. Gain Error vs. VGAIN over Temperature

Data Sheet AD8338

Rev. 0 | Page 7 of 16

1.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

GA

IN E

RR

OR

(dB

)

VGAIN (V)

10kHz100kHz1MHz2MHz4MHz8MHz10MHz12MHz14MHz

1127

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7

Figure 10. Gain Error vs. VGAIN over Frequency

30

0

5

10

15

20

25

100k 1M 10M 100M

DEL

AY

(ns)

FREQUENCY (Hz) 1127

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0

Figure 11. Group Delay vs. Frequency

0

10

20

30

40

50

60

NU

MB

ER O

F H

ITS

DIFFERENTIAL OFFSET VOLTAGE (mV)–3 –2 –1 0 1 2

1 127

9-11

1

OFFSET NULL ONRELATIVE TO OUTPUTVGAIN = 0.6V

Figure 12. Differential Offset Voltage Histogram

5

–5

–4

–3

–2

–1

0

1

2

3

4

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

OFF

SET

VOLT

AG

E (m

V)R

EFER

RED

TO

OU

TPU

T

VGAIN (V)

–40°C+25°C+85°C+105°C

VS = 3V

1127

9-01

2

Figure 13. Differential Offset Voltage vs. VGAIN, Offset Null On

350

300

0

50

100

150

200

250

100k 1M 10M 100M

IMPE

DA

NC

E (Ω

)

FREQUENCY (Hz)

SINGLE-ENDED

DIFFERENTIAL

1127

9-11

2

Figure 14. Output Impedance vs. Frequency

20

–120

–100

–80

–60

–40

–20

0

100k 1M 10M 100M

BA

LAN

CE

ERR

OR

(dB

)

FREQUENCY (Hz) 1127

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5

GAIN = 1

GAIN = 10

GAIN = 100

GAIN = 1000

Figure 15. Output Balance Error vs. Frequency

AD8338 Data Sheet

Rev. 0 | Page 8 of 16

0

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10k 100k 1M 10M

CM

RR

(dB

)

FREQUENCY (Hz)

0dB20dB40dB60dB80dB

1127

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5

Figure 16. CMRR vs. Frequency over Gain, Offset Null On,

Referred to Input

100k

10k

1k

1000 0.4 0.8 1.20.3 0.7 1.10.2 0.6 1.00.1 0.5 0.9

NO

ISE

(nV/

Hz)

VGAIN (V) 1127

9-01

7

–40°C+25°C+85°C

Figure 17. Output Referred Noise vs. VGAIN

1k

1

10

100

0 1.21.11.00.90.80.70.60.50.40.30.20.1

NO

ISE

(nV/

Hz)

VGAIN (V)

–40°C+25°C+85°C

1127

9-11

9

Figure 18. Input Referred Noise vs. VGAIN

1000

0.1

1

10

100

10k 100k 1M 100M10M

NO

ISE

(nV/

Hz)

FREQUENCY (Hz)

GAIN = 1, OFFSET NULL OFFGAIN = 10, OFFSET NULL OFFGAIN = 100, OFFSET NULL OFFGAIN = 1000, OFFSET NULL ONGAIN = 10000, OFFSET NULL ON

1127

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Figure 19. Input Referred Noise vs. Frequency, VBAT = 3 V

0

–90

–80

–70

–60

–50

–40

–30

–20

–10

50k 500k 5M

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

FREQUENCY (Hz)

HD2, 1kΩHD3, 1kΩHD2, 10kΩHD3, 10kΩ

VOUT = 0.5V p-p

1127

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8

Figure 20. Harmonic Distortion vs. Frequency

0

–10

–20

–30

–40

–50

–60

–70

–800.5 3.02.52.01.51.0

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

VOUT (V p-p)

HD2HD3

1127

9-12

0

Figure 21. Harmonic Distortion vs. Output Amplitude

Data Sheet AD8338

Rev. 0 | Page 9 of 16

0

–10

–20

–30

–40

–50

–60

–70

–800.1 1.10.90.70.50.3 1.00.80.60.40.2

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

VGAIN (V)

HD2, MODE PIN HIGHHD3, MODE PIN HIGHHD2, MODE PIN LOWHD3, MODE PIN LOW

1127

9-12

3

VOUT = 0.5V p-p

Figure 22. Harmonic Distortion vs. VGAIN

20

10

0

–10

–20

–30

–40

–50

–60

–700.1 0.3 0.5 0.7 0.9 1.1

P1dB

CO

MPR

ESSI

ON

(dB

m)

VGAIN (V)

1127

9-12

2

OUTPUT

INPUT

Figure 23. Input and Output 1 dB Compression vs. VGAIN

25

0

5

10

15

20

0.1 1.10.90.5 0.70.3

OIP

3 (d

Bm

)

VGAIN (V)

1127

9-12

5

100kHz

1MHz

Figure 24. OIP3 vs. VGAIN

0

–10

–20

–30

–40

–50

–60

–70

–8020k 20M2M200k

IMD

3 D

ISTO

RTI

ON

(dB

c)

FREQUENCY (Hz)

1127

9-12

4

Figure 25. IMD3 Distortion vs. Frequency

2.0

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

0 100 200 300 400 500 600 700 800

V OU

T (V

)

TIME (ns)

VOUT = 2V p-pf = 1MHzGAIN = 0dB

1127

9-02

7

Figure 26. Large Signal Pulse Response vs. Time, VGAIN = 0 V

2.0

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

0 0.2 0.4 0.6 0.8

V OU

T (V

)

TIME (µs)

VOUT = 2V p-pf = 1MHzGAIN = 80dB

1127

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8

Figure 27. Large Signal Pulse Response vs. Time, VGAIN = 1.0 V

AD8338 Data Sheet

Rev. 0 | Page 10 of 16

2.0

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

0 0.2 0.4 0.6 0.8

V OU

T (V

)

TIME (µs)

VOUT = 2V p-pf = 1MHzGAIN = 40dB

1127

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0

Figure 28. Large Signal Pulse Response vs. Time, VGAIN = 0.6 V

100

–100

–80

–60

–40

–20

0

20

40

60

80

0 0.2 0.4 0.6 0.8

V OU

T (m

V)

TIME (µs)

CL = 0pFCL = 10pFCL = 20pFCL = 47pF

VOUT = 100mV p-pf = 1.5MHzGAIN = 1

1127

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1

Figure 29. Small Signal Pulse Response vs. Time (Varying Capacitive Loads)

0.6

0.1

1.0

0

–1.0

0 108642 97531

GA

IN S

TEP

(V)

TIME (µs) 1127

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7

VGAIN

VOUT

Figure 30. Gain Step Response vs. Time

1.5

0.5

1.0

0

–0.5

–1.5

–1.0

0 80 160 20060 14040 12020 100 180

OU

TPU

T VO

LTA

GE

(V)

TIME (µs) 1127

9-01

8

f = 100kHzVIN LOW = 2mVVIN HIGH = 20mVGAIN = 40dB

Figure 31. Overdrive Recovery vs. Time

12

10

8

6

4

2

00 1.21.11.00.80.60.40.2 0.90.70.50.30.1

I DD

(mA

)

VGAIN (V)

–40°C, MODE PIN HIGH+25°C, MODE PIN HIGH+85°C, MODE PIN HIGH–40°C, MODE PIN LOW+25°C, MODE PIN LOW+85°C, MODE PIN LOW

1127

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1

Figure 32. Supply Current vs. VGAIN

50

–40

–30

–20

–10

0

10

20

30

40

20 100 1k 10k 100k 1M 10M 100M

GA

IN (d

B)

FREQUENCY (Hz)

1127

9-13

4

0.01µF

0.1µF

1µF10µF

OFFSET NULL OFF

GAIN = 100

Figure 33. Offset Null Bandwidth vs. Offset Null Capacitor

Data Sheet AD8338

Rev. 0 | Page 11 of 16

0

–10

–100

–90

–80

–70

–60

–50

–40

–30

–20

100 1k 10k 100k 1M 10M

PSR

R (d

B)

FREQUENCY (Hz) 1127

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3

Figure 34. PSRR vs. Frequency

0.6

0.1

0

–1.0

1.0

0 10 30 405 252015 35

VOLT

AG

E (V

)

TIME (µs) 1127

9-01

9

AGC VOLTAGE

OUTPUT VOLTAGE

Figure 35. AGC Response vs. Time, No Load

0.6

0.1

0

–1.0

1.0

0 2 6 10981 543 7

VOLT

AG

E (V

)

TIME (ms) 1127

9-02

0

AGC VOLTAGE

OUTPUT VOLTAGE

Figure 36. AGC Response vs. Time, CL = 0.01 µF

3.0

0

0.5

1.0

1.5

2.0

2.5

20k 100k

OU

TPU

T C

OM

MO

N-M

OD

E VO

LTA

GE

(V)

RESISTANCE (Ω)

VS = 3V

VS = 5V

1127

9-13

5

Figure 37. Output Common-Mode Voltage vs. RCM to VBAT

3.0

0

0.5

1.0

1.5

2.0

2.5

10k 100k

OU

TPU

T C

OM

MO

N-M

OD

E VO

LTA

GE

(V)

RESISTANCE (Ω)

VS = 3V

1127

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6

Figure 38. Output Common-Mode Voltage vs. RCM to COMM

AD8338 Data Sheet

Rev. 0 | Page 12 of 16

THEORY OF OPERATION GETTING STARTED WITH THE AD8338 The AD8338 is a variable gain amplifier (VGA) that provides a variable gain range of 80 dB. With a constant −3 dB bandwidth of 18 MHz across all gains, a gain bandwidth product of 180 GHz is achieved at the highest gain using only 4.5 mA of supply current. The differential output allows the AD8338 to directly drive an ADC input, simplifying board design and saving space and power.

In addition to its gain, bandwidth, and power performance, the AD8338 includes a range of features that increase its versatility.

• Single-supply operation ranging from 3.0 V to 5.0 V • Built-in offset correction circuit to cancel out dc offsets • Automatic gain control (AGC) circuit to control the gain

and keep the output at a steady rms level

Access to internal nodes at both the input and output allows the user to adjust the gain range, adjust the output common-mode voltage, and tune the bandwidth.

INPR and INMR Pins in the Standard Configuration

The gain is controlled by a user supplied voltage input applied to the GAIN pin. The gain can be varied from 0 dB to 80 dB when the default internal resistors are used; the voltage at the GAIN pin can be varied from 0.1 V to 1.1 V. The default internal resistors are used by applying the input voltage to the INPR and INMR pins (Pin 1 and Pin 4; see Figure 39).

INPR

INPD

INMD

INMR

500Ω

500Ω

IINVIN

0dB TO 80dB

OUTP

OUTM

+VOUT/2 + VREF

–VOUT/2 + VREF

1127

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Figure 39. Input Voltage Applied to the INPR and INMR Pins

In the standard configuration, a differential input voltage applied across INPR and INMR is amplified, with the output voltage appearing differentially across OUTP and OUTM. The outputs have a default common-mode voltage of VREF, which is equal to 1.5 V.

GAIN and MODE Pins

The gain of the AD8338 is controlled by the GAIN and MODE pins. Adjusting the voltage at the GAIN pin from 0.1 V to 1.1 V adjusts the gain from its lowest to highest value.

The MODE pin controls the polarity of the gain adjustment. When MODE is tied to VBAT, the gain of the AD8338 increases propor-tionally with an increase of the voltage on the GAIN pin. When MODE is tied to COMM, the gain decreases with an increase of the voltage on the GAIN pin.

OFFSET CORRECTION CIRCUIT The AD8338 provides an offset correction circuit to cancel out any dc offsets that may be present. Connecting a 0.2 µF capacitor from the OFSN pin to VREF allows frequencies above 400 Hz to pass through, but eliminates dc offsets. For dc-coupled operation, disable the offset correction circuit by connecting the OFSN pin directly to the COMM pin. When the part is operated without offset correction, exercise caution with large gains because any offsets present large errors on the outputs.

Unlike a high-pass filter, the offset correction circuit allows signals below the corner frequency to pass through with high levels of crossover distortion. If a frequency below the band of interest may present itself to the inputs, apply a filter in front of the VGA for best performance.

For lower frequency operation, a larger value of COFSN gives unpredictable results. If the part is operated at frequencies below 400 Hz, disable the offset correction circuit and compensate the offset externally.

The corner frequency can be approximately calculated as follows:

OFSNC

Cf

××π=

6002

1 (1)

EXPLANATION OF THE GAIN FUNCTION From a designer’s standpoint, the gain of the AD8338 can be modeled as three cascaded gain stages. The first stage can be thought of as a differential input transconductance stage, where the input current is proportional to the differential input voltage that is applied to the input resistors, as follows:

NPIN

R R

INMxINPxI

+

−= (2)

This current is then fed into the conceptual second stage, a current input-current output VGA, which has a gain range of −26 dB to +54 dB. The conceptual output current is given by Equation 3.

IOUT_VGA = IIN × 10−26 + 80 × ((VGAIN − 0.1)/20) (3)

When VGAIN = 0.1 V, the output current is −26 dB less than the input current; when VGAIN = 1.1 V, the output current is +54 dB greater than the input current.

The third and final stage can be modeled as a transimpedance stage, expressed as follows:

VOP = IOUT_VGA × RFEEDBACK (4a)

VON = −IOUT_VGA × RFEEDBACK (4b)

VOUT = VOP − VON = 2 × IOUT_VGA × RFEEDBACK (4c)

Data Sheet AD8338

Rev. 0 | Page 13 of 16

For example, if the 500 Ω input resistors and 9.5 kΩ feedback resistors are used and a 1 V p-p signal is applied with VGAIN set to 0.1 V, the output value is as follows:

IIN = 1/(500 + 500) = 1 mA (5a)

IOUT_VGA = 1 mA × 10−26/20 = 50 µA (5b)

VOUT = 2 × 50 µA × 9.5 kΩ = 0.95 V p-p (5c)

The calculation in Equation 5 results in a total gain of approx-imately −0.4 dB under the specified conditions. Compressing Equation 2 through Equation 4 produces the following simplified gain equation:

Gain (dB) = (VGAIN − 0.1) × 80 + 20log(RFEEDBACK/RIN) − 26 (6)

where RFEEDBACK and RIN are the resistor values from a single input to a single output.

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9-20

0

INPR

INPD

INMD

INMR

MODECOMM GAIN DETO VAGC

VGA CORE

–26dB TO +54dB

OFFSET NULL

OFSN VREFVBAT

AUTOMATICGAIN

CONTROL

GAIN INTERFACE

AD8338

9.5kΩ

9.5kΩ

VREF

FBKP

OUTP

OUTM

FBKM

IOUTIIN

500Ω

500Ω

Figure 40. Functional Block Diagram

For example, if a design requires a minimum gain of 20 dB using a few additional components, Equation 6 shows that applying a 47 Ω resistor to both the INPD and INMD pins (overriding the value of RIN) sets a gain range of 20 dB to 100 dB (see Figure 41).

INPR

INPD

INMD

INMR

500Ω

500Ω47Ω

47Ω IINVIN

20dB TO 100dB

OUTP

OUTM

+VOUT/2 + VREF

–VOUT/2 + VREF

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4

Figure 41. Using External Resistors at the INPD and INMD Pins

Similarly, if the user requires a minimum gain of −10 dB, applying a 1.5 kΩ resistor to both the INPD and INMD pins sets a gain range of −10 dB to +70 dB.

Effects of Using External Resistors

When the gain is modified through the use of external resistors, several trade-offs must be considered. For example, with the appli-cation of 47 Ω resistors at the inputs, the input noise decreases to approximately 1.5 nV/√Hz, less than the 4.5 nV/√Hz obtained when using the internal 500 Ω resistors. However, the −3 dB bandwidth is reduced from 18 MHz to approximately 3 MHz.

AGC CIRCUIT The automatic gain control (AGC) circuit compares the rms output of the part with the desired rms output at the VAGC pin. Based on this comparison, the DETO pin either sources or sinks current. By connecting the DETO and GAIN pins together and by connecting the MODE pin to ground, the AGC circuit can be used to keep the output rms voltage constant.

To ensure that the AGC circuit reacts fast enough to adjust the gain, but slow enough to allow signals through, place a capacitor from DETO to ground. For example, in an on-off keying (OOK) application with a carrier frequency of 6.795 MHz and a bit rate of 10 kb/sec, a capacitor value of 0.01 µF is recommended. This value ensures that the gain reacts to the bit energy but does not react to the carrier signal.

To set the target rms output voltage, apply a voltage to VAGC. The target output voltage is lowest when VAGC is set to 1.5 V and increases when the applied voltage diverges from the 1.5 V reference voltage. To enable an increasing voltage at the VAGC pin to increase the rms output voltage, use Equation 7.

VORMS = 1.7 × VAGC − 2.264 (7)

To enable a decreasing voltage at the VAGC pin to increase the rms output voltage, use Equation 8.

VORMS = −1.7 × VAGC + 2.864 (8)

If the AGC feature is not used, tie the DETO pin to COMM.

AD8338 Data Sheet

Rev. 0 | Page 14 of 16

ADJUSTING THE OUTPUT COMMON-MODE VOLTAGE As with any differential output, the output of the AD8338 is a differential voltage that is centered about a common-mode voltage. The output common-mode voltage (VOCM) of the AD8338 is nominally set to 1.5 V using an internal reference (see Figure 42).

9.5kΩ

9.5kΩ

VREF = 1.5V

FBKP

OUTP = 1.5V + VOUT/2

OUTM = 1.5V – VOUT/2

FBKM

IOUT

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Figure 42. Output Common-Mode Voltage Set to 1.5 V (Default Setting)

The output common-mode voltage of the AD8338 can be adjusted to directly drive ADCs with various input common-mode requirements. To adjust the output common-mode voltage, add a resistor from each feedback node (FBKP and FBKM) to either COMM or VBAT. Adding a resistor from each feedback node to VBAT decreases the output common-mode voltage; add-ing a resistor from each feedback node to COMM increases the output common-mode voltage (see Figure 43 and Figure 44).

Table 5 and Table 6 provide examples of resistor values for decreasing or increasing the output common-mode voltage.

Table 5. Resistor Values for Decreasing the Output Common-Mode Voltage (Resistor Tied to VBAT) VBAT (V) Target VOCM (V) Resistor Value (Ω) Tied to 5.0 0.9 55,417 VBAT 3.3 0.9 28,500 VBAT 3.0 0.9 23,750 VBAT

Table 6. Resistor Values for Increasing the Output Common-Mode Voltage (Resistor Tied to COMM) VBAT (V) Target VOCM (V) Resistor Value (Ω) Tied to Any 1.8 47,500 COMM Any 2.0 28,500 COMM Any 2.5 14,250 COMM

9.5kΩ R1

R2

9.5kΩ

VREF = 1.5V

FBKP

FBKM

VBAT

VBAT

IOUT

OUTP = 1.5V – + VOUT/2(VBAT – 1.5V) × 9.5kΩR1

OUTM = 1.5V – + VOUT/2(VBAT – 1.5V) × 9.5kΩR2

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Figure 43. Decreasing the Output Common-Mode Voltage (Resistors

Connected Between the FBKP and FBKM Pins to the VBAT Pin)

9.5kΩ R1

R2

9.5kΩ

VREF = 1.5V

FBKP

FBKM

COMM

COMM

IOUT

OUTP = 1.5V – + VOUT/2(0 – 1.5V) × 9.5kΩR1

OUTM = 1.5V – + VOUT/2(0 – 1.5V) × 9.5kΩR2

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7

Figure 44. Increasing the Output Common-Mode Voltage (Resistors

Connected Between the FBKP and FBKM Pins to the COMM Pin)

The AD8338 uses its internal reference for all signal processing. Therefore, although the output common-mode voltage can be changed through the application of external resistors, the VREF signal cannot be changed. For applications that require dc coupling to an ADC, a differential amplifier must be used.

Data Sheet AD8338

Rev. 0 | Page 15 of 16

APPLICATIONS INFORMATION The excellent performance of the AD8338 results in a flat response over various gains with rail-to-rail output signal swing, high drive capability, and a very high dynamic range at a low 12 mW. These features make the AD8338 an exceptional choice for use in battery-operated equipment, low frequency and baseband applications, and many other applications.

SIMPLE ON-OFF KEYED (OOK) RECEIVER For low complexity, low power data communications, a simple link built using a modulating carrier tone in an on/off state provides a fast and cost-effective solution to the designer. Such designs are used in a variety of applications, including near-field communications among noninterference mechanical systems, low data rate sensors, RFID tags, and so on.

The schematic shown in Figure 45 demonstrates a complete inductive telemetry on-off keyed (OOK) front end. The crystal is cut for the target receive frequency of interest, creating a very narrow-band filter, typically around the 6.78 MHz ISM band.

The AD8338 amplifies the signal (the gain is set by an external controller) and drives a full-wave rectifier bridge. The output of this bridge is then low-pass filtered into 100 Ω terminations. This design provides excellent rejection of RF and excellent baseband information recovery for the decision stage that follows.

The reactive filter components—Capacitors C1 through C4 and Inductors L1 and L2—set the baseband recovery performance. A design trade-off exchanges baseband response for RF attenuation.

Table 7 provides typical values for these components at two data rates. Note that Capacitors C1 through C4 are all of equal value, and Inductor L2 has the same value as L1.

Table 7. Typical Values for Components in Reactive Filter

Data Rate C1 to C4 L1 and L2 Carrier Attenuation, f = 6.78 MHz

19,200 bps 12 nF 240 µH −101 dB 57,600 bps 3.9 nF 82 µH −73 dB

INTERFACING THE AD8338 TO AN ADC The AD8338 is well suited to drive a high speed analog-to-digital converter (ADC) and is compatible with many ADCs from Analog Devices, Inc. This example illustrates the interfacing of the AD8338 to the AD7451. The AD7451 is a low power, 3.0 V ADC, which is also competitively priced for a low cost total solution.

Figure 46 shows the basic connections between the AD8338 and the AD7451. The common-mode voltage provided by the AD8338 is within the specifications of the AD7451.

The AD8338 can be coupled directly to the AD7451 for full dc-to-18 MHz operation at the highest level of performance with low operating power (160 mW typical). The glueless interface enables a physically small, high performance data acquisition system that is ideal for many field instruments. A filter before the VGA provides the antialiasing function and noise limiting.

In applications where the modulated information is not encoded in the signal amplitude, use the AGC feature of the AD8338 to reduce any bit errors in the sampled signal.

VREF

MODE

VREF

OUTP

OUTM

CO

MM

OFS

N

CRYSTAL

AN

TEN

NA

CTU

NE U1

AD8338

C60.01µF

GAIN

3.0V

INPR

INMR

DET

O

C50.1µF

D1 D2

D4 D3

C1

C3

C2

C4

L1

L2

R1100Ω

R2100Ω

OOK_P

OOK_M

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Figure 45. Complete, Low Power OOK Receiver

VREF

MODE

VREF

OUTP

OUTM

CO

MM

OFS

N

U1AD8338

FILTEROUTPUT

3.0V

3.0V

INPR

INMR

DET

O

C30.1µF

SCLK

GND

AD7451VIN+

VIN–

C10.1µF

C20.1µF

SDATACS

VDD VREF

R149.9Ω

TOMICRO-

CONTROLLER

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Figure 46. Basic Connections to the AD7451 ADC

AD8338 Data Sheet

Rev. 0 | Page 16 of 16

OUTLINE DIMENSIONS

3.103.00 SQ2.90

0.300.230.18

1.751.60 SQ1.45

08-1

6-20

10-E

10.50BSC

BOTTOM VIEWTOP VIEW

16

589

1213

4

EXPOSEDPAD

PIN 1INDICATOR

0.500.400.30

SEATINGPLANE

0.05 MAX0.02 NOM

0.20 REF

0.25 MIN

COPLANARITY0.08

PIN 1INDICATOR

FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

0.800.750.70

COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22)

Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding AD8338ACPZ-R7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-22 Y4K AD8338ACPZ-RL −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-22 Y4K 1 Z = RoHS Compliant Part.

©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11279-0-4/13(0)