lecture7 ee689 eq intro txeq

8/10/2019 Lecture7 Ee689 Eq Intro Txeq

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Sam Palermo Analog & Mixed-Signal Center

Texas A&M University

ECEN689: Special Topics in High-SpeedLinks Circuits and Systems

Spring 2012

Lecture 7: Equalization Introduction & TX FIR Eq


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Announcements

Exam 1 is March 7 5:45-7:10PM (10 extra minutes) Closed book w/ one standard note sheet

8.5x11 front & back Bring your calculator Covers material through lecture 6

Previous years exam 1s are posted on thewebsite for reference

2


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Agenda

Equalization theory and circuits Equalization overview Equalization implementations

TX FIR RX FIR RX CTLE RX DFE

TX FIR Equalization FIR filter in time and frequency domain MMSE Coefficient Selection Circuit Topologies

Equalization overview paper posted on website 3


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6

Channel Performance Impact


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8/27

Channel Equalization

8

Equalization goal is to flatten the frequency response out to theNyquist Frequency and remove time-domain ISI


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TX FIR Equalization

TX FIR filter pre-distorts transmitted pulse inorder to invert channel distortion at the cost ofattenuated transmit signal (de-emphasis)

9

L

L L

L

L

L

L

L

L

1x 4x 2x 1x

1/4 1 1/2 1/4IDACs&

BiasControl

sgn -1 sgn 0 sgn 1 sgn 2

50

Out-P

Out-N

4:2MUX

2

2

2

21

D0

D1

D2

D3

VDDA=1.2VVDD=1.0V

VDDIO=1.0V

VDDA=1.2V

1

1

1

C2 (5GHz)

From on-chip PLL

2

( 2 . 5

G b / s )

(10Gb/s)

(5Gb/s)

ESD

L

L L

L

L

L

L

L

L

LL

LL LL

LL

LL

LL

LL

LL

LL

1x 4x 2x 1x

1/4 1 1/2 1/4IDACs&

BiasControl


50

Out-P

Out-N

4:2MUX

2

2

2

21

D0

D1

D2

D3

VDDA=1.2VVDD=1.0V

VDDIO=1.0V

VDDA=1.2V

1

1

1

C2 (5GHz)

From on-chip PLL

2

( 2 . 5

G b / s )

(10Gb/s)

(5Gb/s)

ESD

] 2

210102101

TERM out

R D I D I D I D I V

A Low Power 10Gb/s Serial Link Transmitter in 90-nmCMOS, A. Rylyakov et al., CSICS 2005

I -1 I 0 I 1 I 2

D(1) D(0) D(-1) D(-2)


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RX Equalization #1: RX FIR

Pros With sufficient dynamic range, can amplify

high frequency content (rather thanattenuate low frequencies)

Can cancel ISI in pre-cursor and beyondfilter span

Filter tap coefficients can be adaptivelytuned without any back-channel

Cons Amplifies noise/crosstalk Implementation of analog delays Tap precision

11

w -1

z -1

x w 0

z -1

x

z -1

x w n-1

z -1

w nx

DEQ

D in

Analog Delay Elements

*

*D. Hernandez-Garduno and J. Silva-Martinez, A CMOS 1Gb/s 5-Tap Transversal Equalizer based on 3 rd-Order Delay Cells,"ISSCC, 2007.


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RX Equalization #2: RX CTLE

12

Din- D in+

Vo-Vo+

Pros Provides gain and

equalization with lowpower and areaoverhead

Can cancel both pre-cursor and long-tail ISI

Cons Generally limited to 1st

order compensation Amplifies noise/crosstalk PVT sensitivity

Can be hard to tune


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RX Equalization #3: RX DFE

13

z -1clk

x

w 1

z -1x

w 2

z -1x

w n-1

z -1x

w n

D in D RX

Pros No noise and crosstalk

amplification Filter tap coefficients

can be adaptively tunedwithout any back-channel

Cons Cannot cancel pre-

cursor ISI Critical feedback timing

path Timing of ISI

subtraction complicatesCDR phase detection


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Equalization Effectiveness

Some observations: Big initial performance boost with 2-tap TX eq. With only TX eq., not much difference between 2 to 4-tap RX equalization, particularly DFE, allows for further performance

improvement Caution hard to build fast DFEs due to critical timing path 14

I n c r e a s

i n g

E q u a

l i z a t

i o n

Channel Responses


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Link with Equalization

15

S e r i a l i z e r

DTX[N:0]

TX ClkGeneration

(PLL)

TX FIREqualization

RX ClkRecovery

(CDR/Fwd Clk)

RX CTLE + DFEEqualization

D e s e r i a l i z e r

DRX[N:0]

Channel

f


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Channel Equalization

16

Equalization goal is to flatten the frequency response out to theNyquist Frequency and remove time-domain ISI


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TX FIR Equalization Freq. Domain

18

z -1

z -1

z -1

w -1

w 0

w 1

w 2

TX

data

z -1 w n

( ) 21 274.0595.0131.0 += z z zW :10GbpsFor

( )( )ss fT j fT j fT e z

z z zW s

2sin)2cos(

274.0595.0131.02

21

+==+=

w/

( )( ) ( ) dB f W j z

f

4.14190.001)0sin(0cos ===+== 0ResponseFrequencyLow

( ) dBT

f W j z

T f

s

s

0121

1)sin(cos

21

=

==+=

=

ResponseFrequencyNyquist

Equalizer has 14.4dB of frequency peaking

Attenuates DC at -14.4dB and passes Nyquist frequency at 0dB

Note: T s=T b=100ps


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TX FIR Coefficient Selection

Multiplying input symbols by TX Eq., wc=w*c

20

( )( )

( )

( )( ) ( )

( ) ( )( )

( )( ) ( )

( ) ( )( )

( )( )

( )

=

++ 1...

1

0

10...000

21...000

..................

00...001

00...000

10...000

21...000

..................

00...001

00...000

3

...

1

0

lc

c

c

nw

nwnw

ww

w

k h

k hk h

hh

h

k nl y

y

y Total system

( )( )

( )

( )( ) ( )

( ) ( )( )

( )( )

( )+

=

++ 1...

1

0

10...00021...000

..................

00...001

00...000

3

...

1

0

lnwc

wc

wc

k hk hk h

hh

h

k nl y

y

y

We desire the output vector, y, to be ISI free( )( ) ++=

++===

1#tapprecursorEq#samplecursor-preChannel

1#tapprecursorEq#samplecursor-preChannel

nn y

nn y y

des

desdes ,0

,1


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Lone-Pulse Equalization Example

21

With lone-pulse equalization,l =1 input symbols, i.e. c=[1]

( )

( )

( )

[ ]1

2

1

0

0.0067 0 0

0.0090 0.0067 0

0.0097 0.0090 0.0067

0.0152 0.0097 0.0090

0.0162 0.0152 0.0097

0.0224 0.0162 0.0152

0.0360 0.0224 0.01620.0526 0.0360 0.0224

0.0917 0.0526 0.0360

0.1775 0.0917 0.0526

0.3437 0.1775 0.0917

0.0812 0.3437 0.1775

0.0052 0.0812 0.3437

0.0023 0.0052 0.0812

0.0010 0.0023 0.0052

0.0004 0.0010 0.0023

0 0.0004 0.0010

0 0 0.0004

0

0

0

0

0

0

00

0

0

0

1

0

0

0

0

0

0

=

w

w

w

Y des

Channel pulse matrix H with 5 pre-

cursor samples and 10 post-cursorsamples, 3 columns for 3 eq taps

3-tap EqMatrix, W

Symbol Matrix,C for

Lone Pulse

Y des (5+1+1=7)=1

Channel pre-cursor samples

Equalization pre-cursor taps


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TX FIR Coefficient Selection

Differentiating this w.r.t. tap matrix taps to find taps which yield

minimum error norm2

22

inputpulsewithdesdesC des Y HW Y HW Y Y E === We can calculate the error w.r.t. a desired output

H Y H H W

H Y H H W E dW d

T des

T T

T des

T T

=

== 0222

Solving for optimum TX Eq taps, W ( ) desT T ls Y H H H W 1=

des

T

des

T

des

T T Y Y HW Y HW H W E += 22

Computing the error matrix norm 2

This will yield a W matrix to produce a value of 1 at the output cursor,i.e. an FIR filter with gain Need to normalize by the total abs(tap) sum for TX FIR realization

( ) ( )

( )=

=n

i ls

lslsnorm

nW

nW nW

1


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TX FIR Circuit Architectures

Direct FIR vs Segmented DAC Direct FIR Parallel output drivers for output taps Each parallel driver must be sized to

handle its potential maximum current Lower power & complexity Higher output capacitance

Segmented DAC Minimum sized output transistors to

handle peak output current Lowest output capacitance Most power & complexity

Need mapping table (RAM) Very flexible in equalization

24

Segmented DAC

Direct FIR

[Zerbe ]

[Zerbe ]


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Direct FIR Equalization

25

L

L L

L

L

L

L

L

L

1x 4x 2x 1x

1/4 1 1/2 1/4IDACs

&BiasControl


50

Out-P

Out-N

4:2MUX

2

2

2

21

D0

D1

D2

D3

VDDA=1.2VVDD=1.0V

VDDIO=1.0V

VDDA=1.2V

1

1

1

C2 (5GHz)From on-chip PLL

2

( 2

. 5 G b / s )

(10Gb/s)

(5Gb/s)

ESD

L

L L

L

L

L

L

L

L

LL

LL LL

LL

LL

LL

LL

LL

LL

1x 4x 2x 1x

1/4 1 1/2 1/4IDACs

&BiasControl


50

Out-P

Out-N

4:2MUX

2

2

2

21

D0

D1

D2

D3

VDDA=1.2VVDD=1.0V

VDDIO=1.0V

VDDA=1.2V

1

1

1

C2 (5GHz)From on-chip PLL

2

( 2

. 5 G b / s )

(10Gb/s)

(5Gb/s)

ESD

] 2

210102101

TERM out

R D I D I D I D I V

A Low Power 10Gb/s Serial Link Transmitter in 90-nmCMOS, A. Rylyakov et al., CSICS 2005

I -1 I 0 I 1 I 2

D(1) D(0) D(-1) D(-2)


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Segmented DAC Example

26

[Casper ISSCC 2006 ]Row = 4-bit data patternColumn = 6-bit weighting

4 filtered bits(parallel) at 6-bit

resolution

Sized only todeliver maximum

total current


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Next Time

RX FIR RX CTLE RX DFE

Alternate/Future Approaches

27

lecture7 ee689 eq intro txeq

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