lecture 13users.jyu.fi/~loberg/fyse420slides/fyse420lecture13vhd.pdf · 2012. 4. 12. · 13...

Lecture 13Lecture 13

1

[1] Douglas L. Perry, VHDL, third edition, ISBN 0-07-049436-3, McRaw-

Hill Series on Computer Engineering.

[2] Kevin Skahil, VHDL for programmable logic, ISBN 0-201-89586-2

Addison-Wesley.

[3] David Pellerin, Douglas Taylor, VHDL Made Easy, ISBN 0-13-650763-8

Prentice Hall.

[4] Ben Cohen, VHDL Answers to Frequently Asked Question, 2nd edition,

ISBN 0-7923-8115-7, Kluwer Academic Publishers.

Reference list

[5] Sudhakar Yalamanchili, Introductory VHDL Simulation to Synthesis,

ISBN 0-13-080982-9, Prentice Hall.

[6] Digital design with Hardware Description Languages, Mark Davidson,

Jyrki Alamaunu, Tommi Zetterman, Autum 2000.

[7] Peter J Ashenden, The Student’s Guide to VHDL, ISBN 1-55860-520-7

Morgan Kaufmann Publishers, Inc, San Francisco California, www.mkp.com

[8] DIGITAL INTEGRATED CIRCUITS a design perspective, second ed. ,

Jan M. Rabaey, Anantha Chandrakasan, Borivoje Niklic', Prentice Hall,

ISBN 0-13-120764-4.

[9] Digital Design, Prinsiples and Practices, fourth ed. , John F. Wakerly

ISBN 0-13-186389-4.2

Example: RS-FF

architecture behave of rsff is

begin

q <= not ( qb and set ) after 2 ns ;

Delay

Modeling

[1]p. 20

q <= not ( qb and set ) after 2 ns ;

qb <= not ( q and reset ) after 2 ns ;

end behave ;

3©Loberg

Driver

Drivers are created by signal assignment statements.

A concurrent signal assignment inside of an architecture pro-

duces one driver for each signal assignment.

Modeling

[1]p. 19

Example:

architecture Test_Beh of test is

begin

a <= b after 10 ns ;

a <= c after 10 ns ;

end Test_Beh

Creates multiple driven signal.

See resolution function

4©Loberg

Conditional Signal Assignment

entity my_mux is

port (sel: in std_logic_vector (0 to 1) ;

A,B,C,D : in std_logic_vector (0 to 3) ;

Y : out std_logic_vector (0 to 3) ) ;

end my_mux ;

Example

Modeling

[3]p. 145, [4]p. 343

end my_mux ;

architecture mux1 of my_mux is

begin

Y <= A when sel = "00" else

B when sel = "01" else

C when sel = "10" else

D when others ;

end mux1 ;

5©Loberg

entity my_mux is

port (sel: in std_logic_vector (0 to 1) ;

A,B,C,D : in std_logic_vector (0 to 3) ;

Y : out std_logic_vector (0 to 3) ) ;

end my_mux ;

Selected Signal Assignment

Example

Modeling

end my_mux ;

architecture mux1 of my_mux is

begin

with sel select

Y <= A when "00" ;

B when "01" ;

C when "10" ;

D when others ;

end mux1 ;

[3]p. 147, [4]p. 349

6©Loberg

Using a Process

A process can be used to describe the behavior of a circuit over time.

Process statement consistsSensitivity list

Modeling

[1]p. 11, [3]p. 46

of a number of parts: Sensitivity list

Process declarative part

Process statement part

7©Loberg

Process Statement

Sensitivity list

architecture architecture_name of entity_name is

begin

process_name : process (sensitivity_list)

local_declaration ;

local_declaration ;

…

Modeling

[1]p. 11, [3]p. 47

Process declarative

region

Process statement

part

…

begin

sequential statements ;

sequential statements ;

.

.

end process ;

end architecture_name ;

8©Loberg

Sensitivity list

Events on these signals will cause the process

to be executed.

Process declarativeThis area is used to declare local variables

Process Statement

Modeling

[1]p. 11, [3]p. 48

Process declarative

region This area is used to declare local variables

or constants that can be used only inside

of the process.

Process statement

part The order of execution is the order of the

statements in the process statement.

9©Loberg

use work.std_logic_1164.all ;

entity nand2 is

port ( a, b : in std_logic ;

c : out std_logic ) ;

end nand2 ;

architecture nand2 _arc of nand2 is

if ( temp = 1 ) then

c <= temp after 6 ns ;

elsif ( temp = 0 ) then


else


Process Statement

Example

Modeling

[1]p. 11

architecture nand2 _arc of nand2 is

begin

process ( a , b )

variable temp : std_logic ;

begin

temp := not ( a and b ) ;


end if ;

end process ;

end nand2_arc ;

ab

c

10©Loberg

Process Statement Without Sensitivity List

architecture arch_name of entity_name is

begin

process_name : process

local_declaration ;

local_declaration ;

….

A process must include either

a sensitivity list, or one or more

wait statements.

Modeling

[3]p. 51

….

begin

sequential statement ;

wait until (condition) ;

sequential statement ;

….

wait for (time) ;

….

end process ;

end arch_name ;

11©Loberg

process

begin

wait until clk = '1' and clk'event;

m_out <= data_in;

Process statement suspends

the process until there is rising

edge on the clock.

Process Statement Without Sensitivity List

Example

Modeling

[3]p. 168

m_out <= data_in;

wait until clk = '1' and clk'event;

m_out <= not data_in;

end process;

12©Loberg

Using Process for Combinational Logic

Processes can be used to describe combinational logic as well as

registered logic.

Note !

Modeling

[3]p. 169

Registered logic can be accidentally created when one or more

input conditions are left undefined.

13©Loberg

Example

architecture mux_Beh of simple_mux is

begin

process (sel,A,B,C,D)

begin

if sel = "00" then

Y <= A;

Process describes combinational

logic when all inputs are listed in

the sensitivity list and there are no

undefined input conditions.


Modeling

[3]p. 170

entity simple_mux is

port (sel : in bit_vector (0 to 1);

A,B,C,D : in bit;

Y : out bit );

end simple_mux;

Y <= A;

elsif sel = "01" then

Y <= B;


Y <= C;


Y <= D;

end if;

end process;

end mux_Beh;

14©Loberg

if (condition1) then

x <= value1 ;

elsif (condtion2) then

x <= value2 ;

else

The following code


Example

Modeling

[2]p. 179

else

x <= value3 ;

end if ;

results in this equation:

x = condition1*value1

+ /condition1*condition2*value2

+ /condition1*/condition2*condition3*value3 + ...

15©Loberg

architecture test_case_arch of test_case is

begin

process (address)

begin

case address is

when "001" => decode <= X"11";

library ieee;

use ieee.std_logic_1164.all;

entity test_case is

port (

address: in std_logic_vector (2 downto 0);

decode: out std_logic_vector (7 downto 0)


Example

Modeling

when "001" => decode <= X"11";

when "111" => decode <= X"42";

when "010" => decode <= X"44";

when "101" => decode <= X"88";

when others => decode <= X"00";

end case;

end process;

end test_case_arch;

decode: out std_logic_vector (7 downto 0)

);

end test_case;

[2]p. 184

Case statement

Address decoder

16©Loberg

After synthesis we have following combinational logic.

decode0 = address0*/address1*/address2

decode1 = address0*address1*address2

decode2 = /address0*address1*/address2


Case statement

Address decoder

Example

Modeling

[2]p. 184

decode2 = /address0*address1*/address2

decode3 = address0*/address1*address2

decode4 = address0*/address1*/address2

decode5 = 0 (gnd)

decode6 = address0*address1*address2 + /address0*address1*/address2

decode7 = address0*/address1*address2

17©Loberg

Modeling Registered Logic

Using Process for Synchronous Logic

Case statement

State Machine FSM

dr= 1

dr= 0dr= 0

reset=0

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

library SYNOPSYS;

use SYNOPSYS.attributes.all;

[2]p. 184

dr= 1

dr= 0

dr= 0

dtk=1

dtk=1

dtk=1

dtk=0

dr= 0

S4

S1

S2

S3


entity dtkfsm is

port (dr: in STD_LOGIC;

kello: in STD_LOGIC;

reset: in STD_LOGIC;

dtk: out STD_LOGIC);

end;

18©Loberg

architecture dtkfsm_arch of dtkfsm is

-- BINARY ENCODED state machine: Sreg0

Sreg0_machine: process (kello) is

begin

if kello'event and kello = '1' then

if reset='0' then

Sreg0 <= S1;

dtk <= '1' ;

else

case Sreg0 is

Synchronous reset


Case statement


-- BINARY ENCODED state machine: Sreg0

type Sreg0_type is (S1, S2, S3, S4);

attribute enum_encoding of Sreg0_type: type is

"00 " & -- S1

"01 " & -- S2

"10 " & -- S3

"11"; -- S4

signal Sreg0: Sreg0_type;

begin

case Sreg0 is

when S1 =>

if dr='1' then

Sreg0 <= S1;

dtk <='1' ;

elsif dr='0' then

Sreg0 <= S2;

dtk <='1' ;

end if;

dr= 1

dr= 1

dr= 0

dr= 0

dtk=1

dtk=1dtk=1

dtk=0

dr= 0

reset=0

S4

S1

S2

S319

©Loberg

when S2 =>

if dr='1' then

Sreg0 <= S1;

dtk <='1' ;

elsif dr='0' then

Sreg0 <= S3;

dtk <='0' ;

when S4 =>

if dr='0' then

Sreg0 <= S4;

dtk <='1' ;

elsif dr='1' then

Sreg0 <= S1;

dtk <='1' ;


Case statement


dtk <='0' ;

end if;

when S3 =>

Sreg0 <= S4;

dtk <='1' ;

dtk <='1' ;

end if;

when others => -- trap state

Sreg0 <= S1;

end case;

end if;

end if;

end process;

end dtkfsm_arch;

dr= 1

dr= 1

dr= 0

dr= 0

dtk=1

dtk=1dtk=1

dtk=0

dr= 0

reset=0

S4

S1

S2

S3 20©Loberg

OHE encoded FSM

dr= 1

dr= 0

reset=0

Use enumerated type to

represent the various

states of the state machine.



dr= 1

dr= 0

dr= 0

dtk=1

dtk=1dtk=1

dtk=0

dr= 0

S4

S1

S2

S3

State diagram


21©Loberg

library IEEE;


use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

library SYNOPSYS;


entity dtkfsm is


OHE encoded FSM

dr= 1

dr= 1

dr= 0

dtk=1

dr= 0

reset=0

S1


architecture dtkfsm_arch of dtkfsm is

-- ONE HOT ENCODED state machine: Sreg0


attribute enum_encoding of Sreg0_type: type is

"0001 0010 0100 1000” ;

signal Sreg0: Sreg0_type;

begin

entity dtkfsm is

port (dr: in STD_LOGIC;

kello: in STD_LOGIC;


dtk: out STD_LOGIC);

end;

dr= 1

dr= 0

dtk=1

dtk=1dtk=1

dtk=0

S4 S2

S3

22©Loberg

Sreg0_machine: process (kello)

begin

if kello'event and kello = '1' then

if reset='0' then

Sreg0 <= S1;

dtk <= '1' ;

else

when S2 =>

if dr='1' then

Sreg0 <= S1;

dtk <='1' ;

elsif dr='0' then

Sreg0 <= S3;

dtk <='0' ;


OHE encoded FSM


else

case Sreg0 is

when S1 =>

if dr='0' then

Sreg0 <= S2;

dtk <='1' ;

elsif dr='1' then

Sreg0 <= S1;

dtk <='1' ;

end if;

dtk <='0' ;

end if;

when S3 =>

Sreg0 <= S4;

dtk <='1' ;

dr= 1

dr= 1

dr= 0

dr= 0

dtk=1

dtk=1dtk=1

dtk=0

dr= 0

reset=0

S4

S1

S2

S3

23©Loberg

when S4 =>

if dr='0' then

Sreg0 <= S4;

dtk <='1' ;

elsif dr='1' then

Sreg0 <= S1;


OHE encoded FSM

dr= 1

dr= 1

dr= 0

dtk=1

dtk=1dtk=1

dr= 0

reset=0

S4

S1

S2


Sreg0 <= S1;

dtk <='1' ;

end if;

when others => -- trap state

Sreg0 <= S1;

end case;

end if;

end if;

end process;

end dtkfsm_arch;

dr= 1

dr= 0

dtk=1dtk=1

dtk=0

S4 S2

S3

24©Loberg

/RESET+DR*(Sreg0<0> + Sreg0<1> + Sreg0<3>)

RESET*Sreg0<0>*/DR

Sreg0<0>

Sreg0<1>

S1

S2

OHE encoded FSM


After synthesis we have following OHE encoded FSM


RESET*Sreg0<1>*/DR

RESET*Sreg0<2> + RESET*Sreg0<3>*/DR

/RESET + /Sreg0<1> + DR

Sreg0<1>

Sreg0<2>

Sreg0<3>

DTK

S2

S3

S4

KELLORESET

DR

25©Loberg

Simple DFF model without asynchronous reset or preset.

d q

DFF

clk

Rising edge triggered D-type flip-flop

…..

WAIT UNTIL clk'EVENT AND clk='1';

…..

Wait until statement


clk

Falling edge triggered D-type flip-flop

clk

qd

…..

…..


…..

26©Loberg

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY dff IS

PORT (clk,d: IN std_logic;

q: OUT std_logic );

Wait until statement


Note !

First in the process.


q: OUT std_logic );

END dff;

ARCHITECTURE behave OF dff IS

BEGIN

PROCESS

BEGIN


q <= d;

END PROCESS;

END behave;

First in the process.

d q

DFF

clk

27©Loberg

d q

DFF

clk

Rising edge triggered D-type flip-flop

…..

IF (clk'EVENT AND clk='1') THEN

…..


If statement


clk

clk

qdFalling edge triggered D-type flip-flop

…..


…..

[2]p. 188

28©Loberg

LIBRARY ieee;


ENTITY dff IS


q: OUT std_logic );


If statement

d q

DFF

clk


q: OUT std_logic );

END dff;


BEGIN

PROCESS (clk)

BEGIN


q <= d;

END IF;

END PROCESS;

END behave;

[2]p. 188

29©Loberg

Simple D-latch model using if statement.

D-latch

d qD Q

…..

Note!

Content of sensitivity

list


clk LE

Level-sensitive latch

…..

process (clk, d)

begin

if (clk= '1') then

q <= d;

end if;

end process;

…..

[2]p. 189

30©Loberg

Note !We did not see else condition in previous DFF and D-latch

examples.

Simple D-latch model using if statement.


[2]p. 189

Why? Without an else, there is implied memory, which is consistent

with the operation of a flip-flop.

Q will keep its value when the if condition is not met.

31©Loberg

t qT Q

Description of a T-type flip-flop

library IEEE;


entity tff is

port ( t,clk : in std_logic;

q : buffer std_logic

);

end tff;


[2]p. 190

tff

clk

end tff;

architecture tff_arch of tff is

begin

process (clk)

begin

if (clk'event and clk = '1') then

if (t='1') then

q <= not (q);

else

q <= q;

end if;

end if;

end process;

end tff_arch;32

©Loberg

Implementation of a T-type flip-flop is device-specific.

qQD

Description of a T-type flip-flop

0


[2]p. 191

qQD

CE

CLRclk

t

'0'

XILINX

QD

CE

clk

1

0

t

q

Implemented with

multiplexer and DFF.

'1'

33©Loberg

Rising_edge and falling_edge functions

The std_logic_1164 package defines the

functions rising_edge and falling_edge

to detect rising and falling edges of signals.

LIBRARY ieee;


ENTITY dff IS



[2]p. 192


q: OUT std_logic );

END dff;


BEGIN

PROCESS (clk)

BEGIN

IF rising_edge(clk) THEN

q <= d;

END IF;

END PROCESS;

END behave;

34©Loberg

Initialize the hardware to the known state.

The standard specifies that for simulation it gets initialized

to the 'left value of its type.

If signals are not explicitly initialized.


[2]p. 193

to the 'left value of its type.

Bit

Std_logic

'0'

'U'

35©Loberg

clk

d qD Q

DFF with asynchronous

reset

…..

architecture dff_asres_arch of dff is

begin

process (clk, reset)

begin

if reset = '1' then



[2]p. 193

CLR

reset

if reset = '1' then

q <= '0';

elsif rising_edge(clk) then

q <= d;

end if;

end process;

end dff_asres_arch;

…..

36©Loberg

clk

d qD Q

DFF with asynchronous

preset

…..

architecture dff_asres_arch of dff is

begin

process (clk, preset)

begin



[2]p. 194

P

preset

begin

if preset = '1' then

q <= '1';

elsif rising_edge(clk) then

q <= d;

end if;

end process;

end dff_asres_arch;

…..

37©Loberg

DFF with synchronous

reset

…..

architecture dff_syncres_arch of dff is

begin

process (clk) begin

if rising_edge(clk) then

if (reset ='1') thenclk

qD Qd

reset



[2]p. 193

if (reset ='1') then

q <= '0';

else

q <= d;

end if;

end if;

end process;

end dff_syncres_arch;

…..

38©Loberg

8-bit register with clock enable.

library IEEE;


entity reg_8_bit is

port (

ina: in STD_LOGIC_VECTOR (7 downto 0);

ina(0)

ina(1)

outa(0)

outa(1)


ina: in STD_LOGIC_VECTOR (7 downto 0);

ce: in STD_LOGIC;

clk: in STD_LOGIC;

outa: out STD_LOGIC_VECTOR (7 downto 0)

);

end reg_8_bit;

.

.

ina(6)

ina(7)

outa(6)

outa(7)

ce

clk

39©Loberg

architecture reg_8_bit_arch of reg_8_bit is

begin

process (clk)

begin


8-bit register with clock enable.



if (ce = '1') then

outa <= ina;

end if;

end if;

end process;

end reg_8_bit_arch;

Clock enable

40©Loberg

8-bit register with asynchronous reset and synchronous preset .

library ieee;

use ieee.std_logic_1164.all;

entity reg_logic is port (

d : in std_logic_vector(0 to 7);

reset, init, clk : in std_logic;

q : out std_logic_vector(0 to 7) );

end reg_logic;

architecture reg_logic_arch of reg_logic is


architecture reg_logic_arch of reg_logic is

begin

process(reset, clk)

begin

if (reset = '1') then

q <= b”00000000”;

elsif (clk'event and clk ='1') then

if (init = '1') then

q <= b”11111111”;

else

q <= d;

end if;

end if;

end process;

end reg_logic_arch;[2]p.195

41©Loberg

Asynchronous reset

Synchronous reset

Registered output FSM

Next state combinational

logic and next output

combinational logic are

described in different

process statements.Next state

Current state

Next

state


State and output registers

are described in different

process statements.

Four concurrent process

statements

State registers

Output

registers

Next state

comb. Log.

Next output

comb. Log.

Next

output

clk

External

inputs

Registered

outputs

42©Loberg

Example

library IEEE;


entity fsm1 is

port (State0

X=0

X=0

X=1 /Z=1

/Z=1

/Z=0

Behavioral model



port (

clk: in STD_LOGIC;


x: in STD_LOGIC;

z: out STD_LOGIC

);

end fsm1;

State1

X=1 /Z=0

State diagram

reset=1

continued[5]p.138

43©Loberg

architecture fsm1_arch of fsm1 is

type statetype is (state0,state1);

signal state, next_state: statetype;

signal next_output: STD_LOGIC;

when state0 =>

if x='0' then

next_state <= state1;

else


Next state combinational logic


Example

Behavioral model


signal next_output: STD_LOGIC;

begin

comb_process:process (state,x) is

begin

case state is


end if;

when state1 =>

if x= '1' then


else


end if;

end case;

end process comb_process;

continued 44©Loberg

clk_process: process(clk) is

begin

if (clk'event and clk= '1') then

State register


Example

Behavioral model


if (clk'event and clk= '1') then

if reset = '1' then

state <= state0;

else

state <= next_state;

end if;

end if;

end process clk_process;

Note !

Synchronous reset initialize

FSM into state State0.


output_process: process(x,state)

begin

case state is

when state0 =>

if x= '1' then

next_output <= '0';

else

Next output combinational logic


Example

Behavioral model


else

next_output <= '1';

end if;

when state1 =>

if x='1' then

next_output <= '0';

else

next_output <= '1';

end if;

end case;

end process output_process;


clk_outprocess: process(clk)

begin

if(clk'event and clk='1') then

if reset = '1' then

Output Z is initialized synchro-

nously into state -0-.


Example

Behavioral model


Output register

if reset = '1' then

z <= '0';

else

z <= next_output;

end if;

end if;

end process clk_outprocess;

end fsm1_arch;


Optimized hardware implementation has only one DFF which

you can see from the state diagram.


Example

Behavioral model


C

D QX

reset

ZComb. logic

Give solution for the

combinational logic.

48©Loberg

lecture 13users.jyu.fi/~loberg/fyse420slides/fyse420lecture13vhd.pdf · 2012. 4. 12. · 13...

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