lecture 5 - jyväskylän yliopistousers.jyu.fi/~loberg/fyse420slides/fyse420lecture5.pdf · lecture...

FYSE420 DIGITAL ELECTRONICS

Lecture 5

1

DIGITAL LOGIC

CIRCUIT ANALYSIS

& DESIGN Nelson, Nagle, Irvin, Carrol

ISBN 0-13-463894-8

DIGITAL DESIGN Morris Mano

Fourth edition

ISBN 0-13-198924-3

Digital Design Principles and Practices

Fourth edition

Wakerly John F.

ISBN 0-13-186389-4

[1]

[2]

[3]

2

State assignment

Circuit with m states Binary code contains n bits, where 2n ≥ m

Binary Code

Cray Code (unit distance code)

One-Hot (One Flip-Flop for each state)

Synchronous Sequential Logic Synthesis

3

Sequential logic has external reset input

Circuit enters to the starting state.

All flip-flops are reset or set to the 0 or 1 respectively.

©Loberg

4

One Hot

One-Hot assignment are used mostly in register-rich field-programmable gate arrays.

Circuit with m states has m state variable flip-flops (D flip-flop).

Only one flip-flop is set in each time.

Synchronous Sequential Logic

State assignment Synthesis

©Loberg

Simpler decoding logic (exitation functions) Faster sequential logic usually

a 000 000 00001

b 001 001 00010

c 010 011 00100

d 011 010 01000

e 100 110 10000

State Binary Gray One-hot

Possible binary state assignments

Large number of unused binary combinations

Synchronous Sequential Logic Synthesis State assignment

5

One Hot

©Loberg

First state D flip-flop is set (1) and others reset (0).

Used with computer aided design softwares.

Synthesis State assignment

6


One Hot

11

S3 S4

S2

S1

X1X2=10

00

01

11

01 00

00

Part of the state diagram

©Loberg

An example of manually designed

One-Hot State Machine

State 3 (S3) D Flip-Flop

11

S3 S4

S2

S1

X1X2=10

00

01 11

01 00

00

Part of the state diagram

D Q

C

R

X1

X1

X2

X2

S2

X1

X2

S1

X1

X2

S4

X1

X2

S3

-1- tilassa poistuttaessa S3-tilalta

-0- tilassa poistuttaessa

S3-tilalta

-0- poistuttaessa tilalta S3

-1- saavuttaessa tilalle S3

Tilalta S3

poistumisfunktiot

Tilalle S3

saapumisfunktiot

Exitation function


7


One Hot

©Loberg

The first state register

First state S0 Power up

Reset

D Q

C

R

Exitation

function

Global reset

S0




8


One Hot

©Loberg

Circuit has one synchronous output : DTACK*

Circuit has one synchronized input : DR*

a/1

b/1 d/1

c/0

DR*=1

0

1

0 0

1 0

1

State diagram of the circuit

Block diagram of the circuit

Variables for

Exitation

functions

a

b

c

d

DTACK*

Clock

DDTACK




9


One Hot

©Loberg

a/1

b/1 d/1

c/0

DR*=1

0

1

0 0

1 0

1

State diagram of the circuit

a b,1 a,1

c,0 a,1

d,1 d,1

d,1 a,1

b

c

d

DR* 0 1

State table

b

c

d

a b c

X

b,d a,d

b,d

X

X a,d

x x

x x

Implication table

Four states : a, b, c and d

One-Hot Assignment :

a 1 0 0 0

b 0 1 0 0

c 0 0 1 0

d 0 0 0 1

State Qa Qb Qc Qd




10


One Hot

©Loberg

a/1

b/1 d/1

c/0

DR*=1

0

1

0 0

1 0

1

One-Hot Assignment

a 1 0 0 0

b 0 1 0 0

c 0 0 1 0

d 0 0 0 1

State Qa Qb Qc Qd

a 1 0 0 0

a 1 0 0 0

b 0 1 0 0

b 0 1 0 0

c 0 0 1 0

c 0 0 1 0

d 0 0 0 1

d 0 0 0 1

State Qa Qb Qc Qd

b 0 1 0 0

a 1 0 0 0

c 0 0 1 0

a 1 0 0 0

d 0 0 0 1

d 0 0 0 1

d 0 0 0 1

a 1 0 0 0

State Qa Qb Qc Qd

Present time t Next time (t+1)

0

1

0

1

0

1

0

1

DR* DTACK*

1

1

0

1

1

1

1

1

(t+1)

State table

During a proper operation there is no unused state

variable combinations, only states: a, b, c and d.

*** DRbDRbDDTACK




11


One Hot

©Loberg

a/1

b/1 d/1

c/0

DR*=1

0

1

0

0

1 0

1

D Q

C

R

Qb

a

DR*

D Q

C

R

Qb

DR*

DR*

a

DR*

Always at high (-1-)

Always at

low (-0-)

0

Simplified circuit

diagram

Exitation function of the

state flip-flop b

*DRaDb




12


One Hot

©Loberg

a/1

b/1 d/1

c/0

DR*=1

0

1

0 0

1 0

1

Always -1-

D Q

C

R

Qc

DR*

DR* Always -0-

0

b DR*

D Q

C

R

Qc b DR*

Simplified circuit

diagram


state flip-flop c

*DRbDc




13


One Hot

©Loberg

a/1

b/1 d/1

c/0

DR*=1

0

1

0 0

1 0

1

D Q

C

R

Qd c

DR*

DR*

c DR*


state flip-flop d

Simplified circuit

diagram

D Q

C

R

Qd c

DR*

cDRQD dd *




14


One Hot

©Loberg

a/1

b/1 d/1

c/0

DR*=1

0

1

0 0

1 0

1 D Q

C

R

Qa d

DR*

DR*

b DR*


state flip-flop a

*** DRbDRdDRQD aa




15


One Hot

©Loberg

Qa d b Qb a Qc

b

Qd

c

DR*

Clock

Reset*

DTACK*

P R R R R


An example of manually designed One-Hot State Machine

16


One Hot

©Loberg

An example of manual design of Registered-Output FSM

ER*

DR1*

DTACK*

DR* Parity error OK OK

Timing diagram of the

data transfer cycle.

D0-D7

Reg Parity

Parity bit

DR1*

ER*

DTACK*

D0-D7

FSM

Receiver

ADC

Sender

DR*

DTK*

Synthesis

17


©Loberg

Inputs: DR* (DR)

DTACK* (DT)

ER* (ER)

Outputs: DR1*

state

DR1*

DR,DT,ER

a

1

b

1 c

0

d

1

e

1

111

111

011 011

011

011

011

DR,DT,ER=111

001

001

101

010

010

State diagram

Wait until DR* = 1

and DTACK* = 1

Wait until

ER* = 1


18


Synthesis

©Loberg

011 100 101 110 111 001 010 000

a

b

c

d

e

a,1

a,1

d,1

b,1

a,1 d,1

c,0

e,1

c,0

c,0

d,1

d,1 e,1

DR,DT,ER

state

STATE,DR1*

X

X

X

X X

X x

√

√

√

b,d

b

c

d

e

a b c d

Implication table

State table

Compatible pairs : (a) (d) (b,c,e)

A B C

011 100 101 110 111 001 010 000

A

B

C

A,1

A,1 C,1

B,1

C,0 B,1 C,1

DR,DT,ER

state

STATE,DR1*

B,1

A,1

B,1


19


Synthesis

©Loberg

State table

State assignment

A 00

B 01

C 11

State y1 y0

state 011 100 101 110 111 001 010 000

A

B

C

A,1

A,1 C,1

B,1

C,0 B,1 C,1

DR,DT,ER

STATE,DR1*

B,1

A,1

B,1

011 100 101 110 111 001 010 000

00

01

11

00,1

00,1 11,1

01,1

11,0 01,1 11,1

DR,DT,ER

y1y0

Y1Y0,DR1*

01,1

00,1

01,1

Transition table


20


Synthesis

©Loberg

011 100 101 110 111 001 010 000

00

01

11

00,1

00,1 11,1

01,1

11,0 01,1 11,1

DR,DT,ER

y1y0

Y1Y0,DR1*

01,1

00,1

01,1

Transition table

K-maps of the Y0

DT,ER

y0,DR

00

00 01 11 10

01

11

10

y1=1

1

0

1 1

DT,ER

y0,DR

00

00 01 11 10

01

11

10

y1=0

1

0

1 0

1 1

DRDTY 0


21


Synthesis

©Loberg

011 100 101 110 111 001 010 000

00

01

11

00,1

00,1 11,1

01,1

11,0 01,1 11,1

DR,DT,ER

y1y0

Y1Y0,DR1*

01,1

00,1

01,1

K-maps of the Y1

DT,ER

y0,DR

00

00 01 11 10

01

11

10

y1=1

1

0

0 1

DT,ER

y0,DR

00

00 01 11 10

01

11

10

y1=0

1

0

0 0

0 0

Transition table


DTDRyERDRyY 10122


Synthesis

©Loberg

011 100 101 110 111 001 010 000

00

01

11

00,1

00,1 11,1

01,1

11,0 01,1 11,1

DR,DT,ER

y1y0

Y1Y0,DR1*

01,1

00,1

01,1

Transition table DT,ER

y0,DR

00

00 01 11 10

01

11

10

y1=1

1

1

1 0

y1=0

1

1

1 1

1 1

DT,ER

y0,DR

00

00 01 11 10

01

11

10


1*1 yERDRDTDR 23


Synthesis

©Loberg

CLR

C

Q D

CLR C

Q D

CLR C

Q D

Y0

Y1

DR*

DTACK*

ER*

CLOCK

DR1*

RESET

Circuit diagram

An example of manual design Registered-Output FSM

Assumption: all control

inputs are

synchronized

24


Synthesis

©Loberg

clock

reset

DR*

DTACK*

ER*

DR1*

a b c e e e c d d a

Timing diagram of the

data transfer cycle.


25


Synthesis

©Loberg

lecture 5 - jyväskylän yliopistousers.jyu.fi/~loberg/fyse420slides/fyse420lecture5.pdf · lecture...

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