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Jae Wook Lee SIC R&D Lab. LG Electronics

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Page 1: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Jae Wook Lee

SIC R&D Lab.

LG Electronics

Page 2: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Contents

• Introduction

• Why power validation on mobile application processor? • Then, what to validate? Who is in charge of validation?

• Power Validation • Components of power • Lower power techniques and validation challenge • Type of power debugging • Why leakage power became so important? • Scenario power • Low power validation essentials • Correlation effort • High volume manufacturing

• Summary

Page 3: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Why are we validating power on mobile AP?

[Source: http://www.embedded.com/design/mcus-processors-and-socs]

Heat Sink, Cooling Fan

Cooling fan inside a mobile phone? Maximum power consumption on a mobile phone < several watts

[Source: http://anandtech.com]

Page 4: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Why are we validating power on mobile AP?

Skin surface temperature while using a mobile phone

[Source: http://www.eetimes.com/document.asp?doc_id=1279666] [Source: http://thebestsmartphones.org/iphone/the-iphone-5-review/]

Users want longer battery life !

Page 5: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Then, what to validate?

Various low power techniques are used when mobile AP are developed.

[Source: http://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/Art4-low-power-IssQ2-12.aspx]

Page 6: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Who is in charge of validation?

Previously, one person, but now a team is needed with a good collaboration.

[Source: http://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/Art4-low-power-IssQ2-12.aspx]

Page 7: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Components of power

Power = Static Power + Dynamic Power (+Short Circuit Power)

[Source: http://electronicdesign.com/power/understanding-low-power-ic-design-techniques]

Major leakage components

- Gate tunneling leakage - Sub-threshold leakage - Junction leakage

Dynamic power

- Charging/discharging Short circuit power - Shoot-through power

So, expecting simple validation?

Page 8: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Low-power techniques and validation challenge

[Source: http://soccentral.com/results.asp?CatID=488&EntryID=25950]

[Source: http://low-powerdesign.com/article_mentor_NarayananJilla.htm]

[Source: http://www.tela-inc.com/products/power-

optimization/leakage-speed-tradeoffs/]

Multi-Vt optimization Leakage power

MCMM Scenario power, Dynamic power

PG, DVFS Scenario power, DVFS, Minimum Vdd

Low Vdd Standby Power management, PG

[Source: http://www.pcworld.com/article/2010642/meet-clover-trail-

intels-chip-for-mid-range-windows-8-tablets-and-hybrids.html]

Page 9: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Type of power debugging

Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating efficiency SoC

Dynamic power validation In-house power-virus Industrial standard power-virus: i.e. Dhrystone Benchmark tests

DVFS (Dynamic Voltage and Frequency Scaling) validation Adaptive/Dynamic voltage scaling considering process variation

Scenario power validation including idle/stand-by power validation

IR-drop/PMIC-droop validation Low-power validation, power-management validation, etc.

Page 10: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Why leakage power becomes so important?

We cannot disregard leakage power any more !

[Source: http://www.eetimes.com/]

Leakage current has a strong dependency on Voltage Temperature Process

Leakage power while enjoying a game? Voltage condition in

DVFS scheme?

Necessitates power-gating with multiple power domains low leakage cells for non-critical paths good power-management in both AP and S/W

Page 11: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Why leakage power becomes so important?

Leakage current is a good indicator of process along with Vth in power and performance optimization process tuning improving yield or reducing test cost

Performance (1/Vth)

Leakage

(in log scale)

Target

Target Target

Target

Target

Target

Target

Target

Target

Target

Page 12: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Type of power debugging – DVFS/DVS/AVS

[Source: http://www.cadence.com/Community/blogs/lp/archive/2010/08/24/dynamic-power-management-closed-loop-voltage-scaling.aspx]

[Source: http://www.eetimes.com/document.asp?doc_id=1202563]

Open-loop scaling requires statistical silicon data

using a tester safe margin from coarse

granularity

Closed-loop scaling validating HPM better optimization

Page 13: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Scenario power validation

3G Talk, Web browsing, Camera burst-shot, Idle, 1080p playing, etc.

Usage Case 1

Usage Case 2

Usage Case 3

Usage Case 4

Usage Case 5

Usage Case 6

Po

wer

Page 14: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Low power validation essentials

Debugging tools/environment

[Source: http://www.extremetech.com/extreme/166413-post-post-

pc-the-new-materials-tech-and-cpu-designs-that-will-revive-

overclocking-and-enthusiast-computing]

[Source: http://www.semiwiki.com/forum/content/405-moore%92s-law-semiconductor-

design-manufacturing.html]

Statistical analysis

Thermal control

Understanding DFT, clock network, and power management

Measurement technique

Page 15: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Correlation effort

Correlation among three parties are essential in early validation stage Degree of confidence Various benchmarks and usage scenario vs. volume data

[Source: http://www1.verigy.com/ate] [Source: http://www.logicbricks.com]

Design Kit/Platform board Production Tester/ATE

Power Management/Power Estimation

Page 16: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

High volume manufacturing

[Source: http://anandtech.com/show/5365/intels-medfield-atom-z2460-arrive-for-smartphones]

How to guarantee the power consumption of each AP? Killing/Screening parts: When? Yield? Proper test contents with good correlation Volume data analysis Dynamic Voltage and Frequency Scaling support Test hole/escape between HVM and system board test Test time is also important !

Page 17: Jae Wook Lee SIC R&D Lab. LG Electronicskoreatest.or.kr/sub08/sub08_data/이재욱.pdfType of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating

Summary

Validating power in mobile AP becomes important, especially leakage power Validating low-power features/techniques and MMMC (Multi-mode multi-corner) is always challenging Analog value, not pass/fail: many of iterations Statistical analysis for better judgment become essential Improving power estimation accuracy/confidence in defining a new project