introduction of signal integrity and power integrity for the high...
TRANSCRIPT
Samsung ElectronicsSamsung ElectronicsModule Design Team,
Jonghoon Kim ([email protected])
2008년 11월 15일
한국반도체TEST학회 Workshop
Introduction
of Signal Integrity and Power Integrity
for the High-speed Signaling
2008. 11. 15.
김 종 훈
Module개발팀, 메모리 사업부, 삼성전자
2/48Module Design Team,
Jonghoon Kim ([email protected]) Samsung ElectronicsSamsung Electronics 2008년 11월 15일
한국반도체TEST학회 Workshop
Preface
Contents
Signal Integrity
Power Integrity
Importance of Electrical Circuit Model of High-speed Tester
Summary
References
Signal Integrity <김정호교수 (KAIST)>, 삼성반도체초청세미나, 2003.
High-speed Digital Design <박광수, 박성주, 윤칠남>, 삼성전자사내교육, 2004.
Power & Noise Theory <김종훈, 조정현, 이재준>, 삼성전자사내교육, 2004.
DRAM TEST Roadmap <조성범>, 삼성전자사내세미나, 2008
Samsung ElectronicsSamsung ElectronicsModule Design Team,
Jonghoon Kim ([email protected])
2008년 11월 15일
한국반도체TEST학회 Workshop
Signal Integrity (SI)
Understanding of Signal Integrity
Single & Coupled Transmission Line
Current Return Path
4/48Module Design Team,
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한국반도체TEST학회 Workshop
Signaling System
1. Transmitter encodes data as voltage/current signal levels onto the line2. Transmission line delivers the signal to the receiver3. Receiver compares signal with reference to recover data4. Terminator removes signals from line, once they're received5. Clocks tell transmitter when to drive a new signal, receiver when to sample
※ Reference : Text book ?
5/48Module Design Team,
Jonghoon Kim ([email protected]) Samsung ElectronicsSamsung Electronics 2008년 11월 15일
한국반도체TEST학회 Workshop
Signal IntegritySignal integrity (Wikipedia, http://en.wikipedia.org)
Signal integrity or SI is a measure of the quality of an electrical signal.
In digital electronics, …, at high bit rates and over longer distances, various effects can degrade the electrical signal to the point where errors occur, and the device fails. Signal integrity engineering is the task of analyzing and mitigating these impairments.
Signal Integrity of Digital Signal (Jonghoon Kim)송신단에서수신단으로원하는신호를잘전달할수있도록하는기술
“송신회로 + 전송선 + 수신회로”의궁합이중요함
송신회로Driver
전송선로Channel
수신회로Receiver
송신단 수신단
6/48Module Design Team,
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History of Signaling
Signaling = Wiring = Connection
전송선이론을이용한신호전송
Driver & Receiver도고려한 Channel Topology
10 ~ 100 MHz
1G ~ 10GHz
연결만하면신호전송가능(Mapping이중요)
Impedance Control 중요+ Optimal Topology 중요
산포및전원설계중요
Power Integrity와 Random Noise를고려한 Signaling
7/48Module Design Team,
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Random Noise (Jitter) Analysis
※ 자료출처 : KAIST 김정호교수 (20050909, IDEC Jitter Seminar)
8/48Module Design Team,
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회로도로 표시한 Signaling System 변천
Driver ReceiverDriver Receiver
Driver Receiver
Driver Receiver
Power
Ground
Signal Channel
Signal Channel
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dielectric
• Signal and ground (reference) conductor• Uniform shape & dimension along the length of the line
Common Transmission Line Types
Coaxial Line
GND
Signal
Microstrip Line
dielectric substrate
GND
Signal
GND
Signal
GND
Strip Line
Signal GND
2 Wire Line
10/48Module Design Team,
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Transmission Line Model
• Transmission Parameters : impedance, delayL : self-inductance / unit lengthC : self-capacitance / unit length
• Loss parameters : loss, attenuationR : series resistance / unit lengthG : shunt conductance / unit length
i (z)
v (z)+
-∆z
R ∆z L ∆zG ∆z C ∆z
∆z
i (z+∆z)
v (z+ ∆z)+
-
i (z)
v (z)
GND
Signal
11/48Module Design Team,
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Transmission Line Parameters
: Characteristic Impedance
ZLC0 =
γ ω ω α β= + + = +( )( )R j L G j C j : Propagation constant
( α : attenuation constant, β : phase constant)
Lossless Line (R=G=0) 가정하면,
ZVI
VI
R j LG j C0
0
0
0
0= = − =
++
+
+
−
−
ωω
γ ω β= =j LC j
v w LC= =/ /β 1Wave velocity :
wavelength : λ π β= =2 1/ / /f LC
vr r
= =×c
ε ε3 108
12/48Module Design Team,
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Limits of Lumped Model
∆z
L ∆zC ∆z 20dB/decade
Tran
smis
sion
f
fz LC tdB
d3
12
12
= =⋅π π∆
Tran
smis
sion
f
All pass transfer function: infinite cutoff frequency
infinite bandwidth
Low pass transfer function : finite bandwidth
• Lumped RLGC model of the transmission line is valid only for low frequency region
20dB/decade
40dB/decade
Four
ier
com
pone
nt
ff
t t z LCfc
r ddB= 1 1
21
2 3π π π⋅<<
⋅= =
∆
• The time delay of the lumped modeled line section should be much smaller than the signal rise time.f
tcr
= 1π ⋅
tr
Fast rise/fall time = more lumped sections to model transmission line
13/48Module Design Team,
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Unintentional DiscontinuityThe ends of the line
A package lead
An input-gate capacitance
A via between signal layers
A corner
A stub
A branch
A test pad
A gap in the return path
A neck down in a via field
A crossover
14/48Module Design Team,
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Reflections at Z0 Changes
Whenever a signal sees a change in the instantaneous impedance, there will be some reflected signal, and the transmitted signal will be distorted.
Reflection is the primary source of signal-quality problems
Γ = =−+
VV
Z ZZ Z
r
i
1 0
1 0
(Voltage) Refection coefficientVt
Z1Z0
Vi
Vr
Impedance Matching (Z0 = Z1) : NO Reflection.
15/48Module Design Team,
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Multiple Reflection Waveform
Zs > Z0 인경우
Zs > Z0 인경우
16/48Module Design Team,
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Simulating Reflected Waveforms
For a 10-Ohm driver and 50-Ohm characteristic-impedance line, showing the far-end voltage with different rise times for the signal.
Changing the series-source terminating resistor and displaying the voltage at the far end.
Examples of the variety of simulations possible with SPICE.
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bW WS
εrb
W
WS εr
W WS
εrd
Coupled strip line (planar) Coupled strip line (stacked) Coupled Microstrip line
Typical Planar Coupled Transmission Lines
Coupling Mechanism
Inductive Coupling Capacitive Coupling
Coupled Transmission Line
Equivalent Circuit Model
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oZ
oZ
oZ
oZ
Crosstalk by mutual capacitance
Sourceend
Loadend
Far-end Crosstalk(FEXT)
Near end Crosstalk(NEXT)
Crosstalk by mutual inductance
Crosstalk
Crosstalk is the noise due to the coupled energy from one line to another.
NCv
+ + + +
- - - -
+ +
dtdv(t)C(t)i mC =
FCvNLv
FLv
+ -
-- +dtdi(t)L(t)v mL =
+ --
19/48Module Design Team,
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Near end crosstalk- constructive interaction between capacitive & inductive crosstalk- time domain crosstalk waveform is a wide pulse
Far end crosstalk- destructive interaction between capacitive & inductive crosstalk- time domain crosstalk waveform is a narrow pulse
Homogeneous medium (strip line)- capacitive crosstalk = inductive crosstalk- near zero forward crosstalk- large backward crosstalk
Crosstalk Waveforms
20/48Module Design Team,
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Signal Distortion by Crosstalk
Assumption : Fully 3-coupled micro-strip line model with 6 mil space, No PKG coupling
With Crosstalk Odd mode Crosstalk: aggressor의 입력 신호가
victim의 입력 신호와위상이 반대인 경우
Crosstalk makes the Signal Integrity bad dramatically.
Without Crosstalk
Aggressor
Victim
Aggressor
Even mode Crosstalk: aggressor의 입력 신호가
victim의 입력 신호와위상이 동일한 경우
21/48Module Design Team,
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Current flows along the least impedance path• Low frequency : Resistance dominant Short path length• High frequency : Inductance dominant Small loop area
Low frequency current return- distributed over the plane
High frequency current return- concentrated under the signal path
Current Return Path
※ Current Return Path = Signal Return Path = Ground Return Path = Return Ground Path
22/48Module Design Team,
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Unwanted inductanceSlot Slow down rising edge
Inductive crosstalk
A B Increased inductance
C D Increased mutual inductanceIncreased common ground impedance
Ground Plane Discontinuity #1
Samsung ElectronicsSamsung ElectronicsModule Design Team,
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2008년 11월 15일
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Power Integrity (PI)
Understanding of Power Integrity
Modeling of PDN (Z11, Decoupling Capacitor)
Power Integrity Simulation
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뛰어야 할 것과 뛰지 말아야 할 것
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SSN (Simultaneous Switching Noise)
Para
sitic
on P
CB
ChipPackagePCB
Para
sitic
on P
AC
KA
GE
Decoupling Capacitor
전원선의전압변동잡음 (SSN)의효과적인축소
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Power Integrity (PI)Power Integrity Modeling and Design for Semiconductors and Systems
Ege Engin, Madhavan Swaminathan, 출판사 (Prentice Hall), 2007
Managing Power Integrity is the process by which the variations on the power supply of the transistors can be maintained within a specified tolerance value.
A power distribution network (PDN) consists of interconnections in the chip, package and board that include decoupling capacitors, ferrite beads, dc-dc converters and other components.
Power Integrity in Digital System (Jonghoon Kim)Power와 Ground 사이의 Noise를최소화 (혹은 Spec PASS) 시키는기술
“Power Supply + PDN + Operating Current”의동시고려필요
DCPowerSupply
PDN (Power Delivery Network)Connector (Socket), PCB, Package,
Decoupling Capacitor, …
ActiveCircuit
Current
VoltageP
G
27/48Module Design Team,
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EMI (Electromagnetic Interference) Effects
Commercial 8-bit Micro-Controller의 EMI 특성개선
EMI 10dB 축소는SSN 10dB 축소에
기인함.
EMI 발생원인= 전원회로
28/48Module Design Team,
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SI (Signal Integrity) Effects
P/G noise
Ideal P/G
45p
Practical P/G
5p
P/G noise
Ideal P/G
Practical P/G
VddqPACKAGE
Vssq
DRAM
+_
Board
Jae-Jun Lee’s Simulation
29/48Module Design Team,
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PDN Modeling Impedance (Z) MatrixZ-parameter를이용한 Impedance Analysis @ P/G Port
Self Impedance (Input Impedance) : Z11,… Dominant !
Transfer Impedance : Z21,…
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
333231
232221
131211
ZZZZZZZZZ
−
+
1V−
+
3V
−+ 2V
1I 3I
2I
nn IZIZIZIZV ⋅+⋅⋅⋅+⋅+⋅+⋅= 33332321313
Power Delivery Network ⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜
⎝
⎛
⋅×
⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜
⎝
⎛
⋅⋅⋅⋅⋅⋅
⋅⋅⋅
=
⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜
⎝
⎛
⋅
nnnnnn
n
n
n
n I
III
ZZZZ
ZZZZZZZZZZZZ
V
VVV
3
2
1
331
3333231
2232221
1131211
3
2
1
SSN Z-parameter Δ-I
30/48Module Design Team,
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Z (Impedance) Parameter : 2 Port Network
( )
( )( ) 0=
=fii
fj
fiij i
vZ
( )fv1( )fi1( )
( )f
f
iv
Z1
111 = ( )fv1
( )
( )f
f
iv
Z2
112 = ( )fi2
( )fi1( )
( )f
f
iv
Z1
221 = ( )fv2
( )
( )f
f
iv
Z2
222 = ( )fv2 ( )fi2
( )fiv( )fii ijZ ( )fjv ( )fjiSuperposition of Current Source
Current Source Open
Zij : Port j를제외한모든 Port가 Open된 (전류가흐르지않는)상태에서 Port j 전류와 Port i 전압의비율
일반적으로 Zii가 Zij (i≠j) 보다크므로, Zii (혹은 Z11)이더욱중요Zii와전원 Noise는비례관계 Zii를작은값으로유지시켜야함
31/48Module Design Team,
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C Dominant ESL dominant
ESR limits the lowest Impedance.
C
ESL
ESR
Parasiticparameters
FLC n p
MHz= = ≈1
21
2 100 80017 8
π π *.
C=100nF
Decoupling Capacitor의 주파수 특성
Capacitor는고주파에서 Inductor로변한다 !!!
32/48Module Design Team,
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C pF nFESL pHESR mohm
===
1 10080010
~ C nFESL pH nHESR mohm
===
1001 10010
~
C nFESL pHESR mohm ohm
===
10080001 10. ~
Capacitor의 C, ESL, ESR 영향
Increasing ESLIncreasing C
Incr
easi
ng E
SR
공진주파수를기준으로
저주파는 C dominant영역이고,공진주파수부근은 ESR 영역이며,고주파는 ESL dominant 영역이다.
33/48Module Design Team,
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…
λ1
2134= mm
λ2 134= mm
F c MHzr
11
546 2= ≈λ ε
.
F c GHzr
22
1092= ≈λ ε
.
…
F1 F2
The PCB structure determines the resonant freq. of MM bare PCB.
FLC
MHz
C Ad
nF
ESLF C
nH
s pcb
pcb r
pcb
_ .
.
( ).
= ≈
= ≈
∴ = =
12
329 5
0177
12
1318
0
2
π
ε ε
π
DDR2 Bare PCB의 주파수 특성
34/48Module Design Team,
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Capacitance Z11 of DIMM PCB
C=100nF C=10nF C=1nF
C=100pF C=10pF C=1pF
Z11
: Location of de-cap.
: Measure points
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<Front>
<Back>
DDR2 RDIMM RC - C Module : 2R X8 ECC
133.35mm
30
.00
mm
Application to Memory Module
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Improvement of Zij
37/48Module Design Team,
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Power Integrity Verification : Review
PCB의 PI 특성사전검증방법 : Z11 simulation (PowerSI, SIwaves)
사상 : PCB에서구현가능한최대한의 PI 특성확보
Cost 관련 Trade-off 고려 (주로 De-cap 관련)
PCB 위의 DRAM ball pad에서 Z11 관찰
Bare PCB + Decoupling (+ bulk) capacitor만포함
Decoupling Capacitor 배치기준
JEDEC 및기존제품의배치경험에준하여선정
현재검증방법의부족한점
DRAM Current를고려한 P/G Noise 예측미흡
VDD/VSS noise on DRAM 관리미흡 (Z11 @ PCB의의미: DRAM ball에서의 PI 특성)
38/48Module Design Team,
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P/G Noise Simulation
P/G Noise Simulation 추진 방향
P/G Current
+
P/G noise SpecRevision 제품개발PASS (RISK)FAIL (RISK)
39/48Module Design Team,
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Simulation of SSN @ time domain
Effects of Reference Plane Changing on PI & SI
DIMM PCB design file+
Equivalent circuit model(DRAM, Package)
+Assumed DRAM Current
Simulated P/G Noise Simulated Signal waveform
(Real Mother Board design),
Real DIMM PCB file,
Real Package PCB design file,
Real DRAM Operation Current를
이용한 Simulation
40/48Module Design Team,
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PDN Design Methodology
Conceptual Simulation
Layout (PCB Artwork)
Post Routing Simulation
OK ?
OK ?
Guideline
Fabrication
Experimental Verification
Report #1
Report #2
Report #3
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Importance
of Electrical Circuit Model
of High-speed Tester
Tester Interface
Example of PI & SI Improvement
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Memory Tester Trend
43/48Module Design Team,
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Power Line ☞ Device가 요구하는 전력을 충분히 공급
Signal Line ☞ 입력된 Signal을 출력단 까지 왜곡 없이 전달
DUTDUTSocket BoardSocket Board
Test Interface의 기능 및 요구 성능
44/48Module Design Team,
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Power Noise (@ GDDR3 Test Board) Bulk-cap 보강및 De-cap 위치이동
Test Interface - PI 특성 개선 사례
Bulk-cap 용량증가에따른
PI 특성강화됨을 확인
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DQ/DQS Signal 전송특성분석및예측 (@ DDR2 Test Board)
Test Interface - SI 특성 개선 사례 1/2
ATEInternalChannel
Socket DRAM
Equivalent Electrical Circuit Model of TESTER
TESTER 공급업체로부터 ATE 내부의 Channel Model을제공받음
Mode별 Driver & Receiver Model, Circuit Model of Signal Channel
Samsung 내부에서 Channel Simulation을통한동작특성예측More High-speed operation 가능성미리확인
의미 : 확신을가지고해당업체의 ATE를사용할수있는계기가됨
46/48Module Design Team,
Jonghoon Kim ([email protected]) Samsung ElectronicsSamsung Electronics 2008년 11월 15일
한국반도체TEST학회 Workshop
Test Interface - SI 특성 개선 사례 2/2
Simulated ATE ~ DRAM channel : DQ/DQS Signal (@ DDR2 Test Board)
Samsung ElectronicsSamsung ElectronicsModule Design Team,
Jonghoon Kim ([email protected])
2008년 11월 15일
한국반도체TEST학회 Workshop
Summary
48/48Module Design Team,
Jonghoon Kim ([email protected]) Samsung ElectronicsSamsung Electronics 2008년 11월 15일
한국반도체TEST학회 Workshop
Summary
Signal IntegrityUnderstanding of Signal IntegritySingle & Coupled Transmission Line
Current Return Path
Power IntegrityUnderstanding of Power IntegrityModeling of PDN (Z11, Decoupling Capacitor)
Power Integrity Simulation
Importance of Electrical Circuit Model of High-speed TesterTester Interface
Example of PI & SI Improvement
Acknowledgement : 자료인용및도움을주신많은분들께감사드립니다.
문의 : 김종훈 ([email protected], [email protected], 011-9769-4252)