Analog VLSI DesignAnalog VLSI Design

Technology TrendsTechnology Trends

3 Crises in VLSI Design3 Crises in VLSI Design

Power CrisesPower Crises

VLSI - Ever Increasing PowerVLSI - Ever Increasing Power

Trends in Power, VDD and CurrentTrends in Power, VDD and Current

Power/Delay Trade-OffPower/Delay Trade-Off

Leaky TransistorsLeaky Transistors

3 Strategies for Low Power3 Strategies for Low Power

Low Power StrategiesLow Power Strategies

Interconnect Interconnect

Interconnect TrendsInterconnect Trends

InterconnectInterconnectTrendsTrends

Design IssuesDesign Issues

Coupled NoiseCoupled Noise

ComplexityComplexity

Which Way Forward?Which Way Forward?

Future Chips 2014Future Chips 2014

ChallengeChallenge

ANALOG VLSI DESIGNANALOG VLSI DESIGN

Principles, Techniques, Building BlocksPrinciples, Techniques, Building Blocks

No, not true!No, not true! Total analog chip sales for 2002 $39 billion, 2004 ~ $48billionTotal analog chip sales for 2002 $39 billion, 2004 ~ $48billion 10% increase over previous year, growth predicted for next 3 years10% increase over previous year, growth predicted for next 3 years Raw transducer output in most systems is analog in nature Raw transducer output in most systems is analog in nature Although very small %age of total chip area is analog, still a Although very small %age of total chip area is analog, still a

need for good design practice since analog component may be the need for good design practice since analog component may be the limiting factor on overall system performancelimiting factor on overall system performance

Days of pure analog design are over, majority of systems are integrated Days of pure analog design are over, majority of systems are integrated with increased functionality in digital domainwith increased functionality in digital domain

Will attempt to introduce some hierarchy - use building block approach Will attempt to introduce some hierarchy - use building block approach as for digitalas for digital

Bottom Line:Bottom Line: Ability to design both analog and digital circuits and Ability to design both analog and digital circuits and understand interactions between the 2 domains adds dimension to understand interactions between the 2 domains adds dimension to your design portfolioyour design portfolio

Is Analog VLSI Design Dead?

Analog Building BlocksAnalog Building Blocks

Basic Blocks include Basic Blocks include

Current SourcesCurrent Sources

Current MirrorsCurrent Mirrors

Single Stage AmplifiersSingle Stage Amplifiers

Differential Amplifiers & Op AmpsDifferential Amplifiers & Op Amps

ComparatorsComparators

Voltage ReferencesVoltage References

Data ConvertersData Converters

Switched Capacitor CircuitsSwitched Capacitor Circuits

MOS Market dominates worldwide chip sales (>75%)MOS Market dominates worldwide chip sales (>75%) Total MOS sales 2003/2004 ~ $250 billionTotal MOS sales 2003/2004 ~ $250 billion Illustrates strength of CMOS technology - feature sizes now < 0.1umIllustrates strength of CMOS technology - feature sizes now < 0.1um True system-level integration on a chip i.e. converters, filters, dsp True system-level integration on a chip i.e. converters, filters, dsp

processors, microcontroller cores, memory all reside on one dieprocessors, microcontroller cores, memory all reside on one die >180 million transistors/chip>180 million transistors/chip Decreases in feature size cause some complexities:Decreases in feature size cause some complexities:

Layout issues more importantLayout issues more important

Modeling is a key issueModeling is a key issue

Parasitic effects significantParasitic effects significant

Power dissipation issues challenging (BiCMOS, VDD-hopping, etc)Power dissipation issues challenging (BiCMOS, VDD-hopping, etc)

CMOS Technology

Low Power + High Speed=BiCMOSLow Power + High Speed=BiCMOS

Future of Gigascale Integration lies in BiCMOS technologyFuture of Gigascale Integration lies in BiCMOS technology Application Example : Wireless Communications - pagers, Application Example : Wireless Communications - pagers,

cellular phones, laptops, palmtopscellular phones, laptops, palmtops Requirement for high speed low power front end challenge for Requirement for high speed low power front end challenge for

analog designers (cannot afford time and energy to digitize first)analog designers (cannot afford time and energy to digitize first)

Historical Roadmap: Bipolar/CMOS• 1930’s – MOS invented, didn’t catch on, dormant for 30 yrs

• 1940’s- 50’s – Bipolars invented, became dominant thru the early 70’s

• 1970’s - Power consumption issues re-ignited interest in MOS

• 1980 MOS/Bipolar share of market 50/50 (largely due to CMOS)

• 1983 – BiCMOS invented

• 1990’s – CMOS dominant

• 2000’s - BiCMOS integrated into CMOS, Gigascale Integration

Improvement TrendsImprovement Trends

Functionality (e.g. non-volatility, smart power)Functionality (e.g. non-volatility, smart power) Integration Level (e.g. components per chip, Moore’s Law)Integration Level (e.g. components per chip, Moore’s Law) Compactness (e.g. components/sq cm)Compactness (e.g. components/sq cm) Speed (e.g. microprocessor clock in MHZ)Speed (e.g. microprocessor clock in MHZ) Power (e.g. laptop or cellphone battery life)Power (e.g. laptop or cellphone battery life) Cost (e.g. cost per function, historically decreasing)Cost (e.g. cost per function, historically decreasing)

Available from scaling & tech improvements over last 30yrsAvailable from scaling & tech improvements over last 30yrs

Future Trends: Future Trends: International Technology International Technology Roadmap for Semiconductors (ITRS)Roadmap for Semiconductors (ITRS)

S/C industry has become a global industry in the 90’s: manufacturers, S/C industry has become a global industry in the 90’s: manufacturers, suppliers, alliances, world wide operations. Since 1992 Semiconductor suppliers, alliances, world wide operations. Since 1992 Semiconductor Industries Association (SIA) has produced a 15year outlook on major Industries Association (SIA) has produced a 15year outlook on major trends in the s/c industry trends in the s/c industry (ITRS)(ITRS)

Technical challenges identifiedTechnical challenges identified Solutions proposed (where possible)Solutions proposed (where possible) Traditional is reaching fundamental limitsTraditional is reaching fundamental limits New materials must be introduced to further extend scaling limitsNew materials must be introduced to further extend scaling limitsWay to go: Way to go: System In a Package (SiPSystem In a Package (SiP P-SoC (Performance System-on-a-Chip): integration of multiple silicon P-SoC (Performance System-on-a-Chip): integration of multiple silicon

technologies on a chiptechnologies on a chip NanotechnologyNanotechnology Neuromorphic Systems - emulate natural signal processing (circuits Neuromorphic Systems - emulate natural signal processing (circuits

operating in subthreshold/weak inversion )operating in subthreshold/weak inversion )

ITRS: Technology Working Groups (TWG’s)ITRS: Technology Working Groups (TWG’s)

Purpose: To provide guidance, host and edit workshop in following Purpose: To provide guidance, host and edit workshop in following areasareas

DesignDesign TestTest Process Integration, Devices, StructuresProcess Integration, Devices, Structures Front End ProcessesFront End Processes LithographyLithography InterconnectInterconnect Factory IntegrationFactory Integration Assembly & PackagingAssembly & Packaging Cross Cutting Working Groups in environment, safety, defect Cross Cutting Working Groups in environment, safety, defect

reduction, metrology, modeling/simulationreduction, metrology, modeling/simulation

ITRS: Example of Key Lithography-Related ITRS: Example of Key Lithography-Related CharacteristicsCharacteristics

Year 99 2002 2004 2008Year 99 2002 2004 2008 DRAM pitch 180nm 130nm 110nm 70nmDRAM pitch 180nm 130nm 110nm 70nm MPU Gate Length 140nm 100nm 70nm 45nmMPU Gate Length 140nm 100nm 70nm 45nm

What is S-o-C (system on a chip)?What is S-o-C (system on a chip)? S-o-C chips are often mixed-technology designs, including such S-o-C chips are often mixed-technology designs, including such

diverse combinations as embedded DRAM, high-performance or diverse combinations as embedded DRAM, high-performance or low-power logic, analog, RF, esoteric technologies like Micro-low-power logic, analog, RF, esoteric technologies like Micro-Electro Mechanical Systems (MEMS) , optical input/output. Electro Mechanical Systems (MEMS) , optical input/output.

Time-to-market for particular application-specific capability is keyTime-to-market for particular application-specific capability is key Product families will be developed around specific SoC Product families will be developed around specific SoC

architectures and many SoC designs customized for target architectures and many SoC designs customized for target markets by programming part (using software, FPGA, Flash, and markets by programming part (using software, FPGA, Flash, and others). others).

Category of SoC is referred to as a Category of SoC is referred to as a programmable platformprogrammable platform. The . The design tools and technologies needed to assemble, verify, and design tools and technologies needed to assemble, verify, and program such embedded SoC’s will present a major challenge program such embedded SoC’s will present a major challenge over the next decade.over the next decade.

Interconnect Working GroupInterconnect Working Group Function of interconnect is to distribute clock and other signals and Function of interconnect is to distribute clock and other signals and

to provide power/groundto provide power/ground Requirement for interconnect is to meet the high-speed Requirement for interconnect is to meet the high-speed

transmission needs of chips despite further scaling of feature sizes. transmission needs of chips despite further scaling of feature sizes. As supply voltage reduced, cross-talk an issue, near term solution As supply voltage reduced, cross-talk an issue, near term solution

is use of thinner copper metallization to lower line-to-line is use of thinner copper metallization to lower line-to-line capacitance. capacitance.

Although copper-containing chips introduced in 1998, copper must Although copper-containing chips introduced in 1998, copper must be combined with new insulator materials. Introduction of new low be combined with new insulator materials. Introduction of new low dielectrics, CVD metal/barrier/seed layers, and additional dielectrics, CVD metal/barrier/seed layers, and additional elements for SoC, provide process integration challenges.elements for SoC, provide process integration challenges.

Emerging system-in-a-package (SiP) and system-on-a-chip, or SoCEmerging system-in-a-package (SiP) and system-on-a-chip, or SoC For long term, material innovation with traditional scaling will no For long term, material innovation with traditional scaling will no

longer satisfy performance requirements. New design or longer satisfy performance requirements. New design or technology solutions (such as coplanar waveguides, free space RF, technology solutions (such as coplanar waveguides, free space RF, optical interconnect) will be needed to overcome the performance optical interconnect) will be needed to overcome the performance limitations of traditional interconnect.limitations of traditional interconnect.

Analog VLSI Design ECE567 Spr 2008Analog VLSI Design ECE567 Spr 2008 Professor: Dr. Abby Ilumoka, Room UT 235, Ph: (860) - 768 - 5231Professor: Dr. Abby Ilumoka, Room UT 235, Ph: (860) - 768 - 5231 Email: ILUMOKANW@MAIL.HARTFORD.EDU Email: ILUMOKANW@MAIL.HARTFORD.EDU Class Time: Mon 5.45pm – 8.15pm Class Time: Mon 5.45pm – 8.15pm Office Hrs:Office Hrs: Tues Thur 10.50am – 12.10pm, Mon 4-5pm, Wed 11-11.30am Tues Thur 10.50am – 12.10pm, Mon 4-5pm, Wed 11-11.30am Credits: 3 credits Credits: 3 credits Objectives:Objectives: Course deals with design principles and techniques for high Course deals with design principles and techniques for high

performance analog IC’s implemented in CMOS technology. Although analog performance analog IC’s implemented in CMOS technology. Although analog design appears to be much less systematic than digital, course highlights good design appears to be much less systematic than digital, course highlights good design principles to simplify process. design principles to simplify process.

Course Text & Materials: Course Text & Materials: 1. 1. Analog Integrated Circuit Design by Johns & Martin, Wiley 1997Analog Integrated Circuit Design by Johns & Martin, Wiley 19972. CMOS Circuit design layout & Simulation by Baker, Li & Boyce, IEEE Press, 19982. CMOS Circuit design layout & Simulation by Baker, Li & Boyce, IEEE Press, 19983. Specified journal & conference papers3. Specified journal & conference papersGrading Policy and Exam Dates:Grading Policy and Exam Dates: 4 Exams - 4 X 25% = 100 %4 Exams - 4 X 25% = 100 % Laboratory/ Design Assignments (bonus max 10%)Laboratory/ Design Assignments (bonus max 10%) TOTAL 100%TOTAL 100%Spr 2008 Exam Dates: Exam 1 Mon Feb 18 Spr 2008 Exam Dates: Exam 1 Mon Feb 18 Exam 2 Mon Mar 24Exam 2 Mon Mar 24 Exam 3 Mon Apr 21 Exam 3 Mon Apr 21 Exam 4 Mon May 12Exam 4 Mon May 12

TOPICSTOPICS 1. Advanced MOS Modeling1. Advanced MOS Modeling - Short Channel Effects- Short Channel Effects - Sub-threshold Operation- Sub-threshold Operation - Leakage Currents- Leakage Currents 2. Processing and Layout for CMOS Analog Circuits2. Processing and Layout for CMOS Analog Circuits 3. Fundamental Building Blocks of Analog IC’s3. Fundamental Building Blocks of Analog IC’s - MOS Current Mirrors- MOS Current Mirrors - Single Stage Amps- Single Stage Amps - SPICE Simulation Examples- SPICE Simulation Examples 4. Design of the 2 stage CMOS Op Amp: Op Amp I4. Design of the 2 stage CMOS Op Amp: Op Amp I 5. Design of the 2 stage CMOS Op Amp: Op Amp II5. Design of the 2 stage CMOS Op Amp: Op Amp II 6. Additional Analog Building Blocks6. Additional Analog Building Blocks - Comparators - Comparators - Sample and Hold circuits- Sample and Hold circuits - Switched capacitor Circuits- Switched capacitor Circuits 7. Data Converters A-D and D-A7. Data Converters A-D and D-A 8. Design Refinement & Optimization Techniques8. Design Refinement & Optimization Techniques 9.Noise Analysis and Modeling9.Noise Analysis and Modeling