internal architecture of 8086/8088 cpu

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Internal architecture of 8086/8088 CPU. 计算机学院 李征 Tel : 13882153765 Email : [email protected] OICQ: 1340915. Internal Architecture of 8088. Address adder. 20 位. ∑. AH AL. BH BL. CH CL. 8 位. CS. General Register. DH DL. DS. SP. I/O Control. SS. BP. ES. - PowerPoint PPT Presentation

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Page 1: Internal architecture of 8086/8088 CPU

Internal architecture of Internal architecture of 8086/8088 CPU8086/8088 CPU

计算机学院 李征计算机学院 李征TelTel :: 1388215376513882153765

EmailEmail :: [email protected]@cs.scu.edu.cnOICQ: 1340915OICQ: 1340915

Page 2: Internal architecture of 8086/8088 CPU

Internal Internal ArchitectureArchitecture

of 8088 of 8088

1 2 3 4

内部暂存器 IP ES

SS DS CS

I/O

Control System B

us

Execution Control

ALU

Flag Register

AH AL BH BLCH CL

DH DL SP BP SI DI

General Register

Address adder

指令队列 (Instruction Queue)

执行部件 ( EU)

总线接口部件 ( BIU)

16 位

20 位

8 位

8 位

Page 3: Internal architecture of 8086/8088 CPU

EU and BIUEU and BIU

There are two units in 8086/8088 CPU, There are two units in 8086/8088 CPU, which are Execute Unit (EU) and Bus which are Execute Unit (EU) and Bus Interface Unit (BIU).Interface Unit (BIU).

EUEU: Automatically executing the : Automatically executing the instructions in instruction queue.instructions in instruction queue.

Page 4: Internal architecture of 8086/8088 CPU

EU and BIUEU and BIU

BIUBIU: : 1) In instruction 1) In instruction reading cyclereading cycle, reading , reading the instructions from memory to instruction the instructions from memory to instruction queue.queue.

2) In instruction 2) In instruction execution cycleexecution cycle, , operating (read or write) dada in memory operating (read or write) dada in memory cell or I/O port.cell or I/O port.

Page 5: Internal architecture of 8086/8088 CPU

EU and BIUEU and BIU

If the current instruction executed by EU If the current instruction executed by EU do not use system bus, do not use system bus,

BIU can read successive instruction from BIU can read successive instruction from memory synchronously.memory synchronously.

Page 6: Internal architecture of 8086/8088 CPU

EU and BIUEU and BIU

The The reading cyclereading cycle of successive of successive instruction can instruction can overlap overlap the the execution execution cyclecycle of current instruction. of current instruction.

The architecture with EU and BIU is a The architecture with EU and BIU is a simple simple pipelinepipeline ( ( 流水线流水线 ).).

Question:Question:When will the pipeline break? When will the pipeline break? Program transfer

Page 7: Internal architecture of 8086/8088 CPU

BIUBIU

(1) I/O Control Circuit(1) I/O Control CircuitConnected with system busConnected with system bus

Controlled by Controlled by Execution ControlExecution Control

When bus operation occurs, it interacts When bus operation occurs, it interacts with system bus with address, data and with system bus with address, data and control signalscontrol signals

Page 8: Internal architecture of 8086/8088 CPU

BIUBIU

(2) Instruction Queue(2) Instruction Queue

Instructions which BIU read from memory Instructions which BIU read from memory are stored here one by oneare stored here one by one

EU read instructions for execution one by EU read instructions for execution one by one from hereone from here

Page 9: Internal architecture of 8086/8088 CPU

BIUBIU

(3) Address Adder(3) Address Adder

Transform Transform logic addresslogic address of of memory cellmemory cell to to physic addressphysic address

Page 10: Internal architecture of 8086/8088 CPU

Physic addressPhysic address

8086/8088 has 20 address pins, and its 8086/8088 has 20 address pins, and its addressing range is 2addressing range is 22020 bytes (1M bytes). bytes (1M bytes).

The address with 20 bits on the address The address with 20 bits on the address bus is called bus is called physic addressphysic address..

Page 11: Internal architecture of 8086/8088 CPU

Logic addressLogic address

Logic address Logic address only appears insideonly appears inside 8086/8088 8086/8088 CPU.CPU.

Instructions can only use logic addressInstructions can only use logic address..

Segment Base Value (Segment Base Value ( 段基值,段基值, 16 bits) : Offset 16 bits) : Offset (( 偏移量,有效地址,偏移量,有效地址, EA, 16 bits)EA, 16 bits)

Segment Base Address (Segment Base Address ( 段基址,段基址, 20 bits) = 20 bits) = Segment Base Value * 16Segment Base Value * 16

Page 12: Internal architecture of 8086/8088 CPU

Transform logic address to physic Transform logic address to physic addressaddress

Physic Address (20 bits) = Physic Address (20 bits) = Segment Base Value * 16 + OffsetSegment Base Value * 16 + Offset

Page 13: Internal architecture of 8086/8088 CPU

xxxx xxxx

xxxx0

xxxx0

xxxx+

xxxxx16 位偏移量

16 位段基值

20 位段基址

20 位物理地址地址加法器

发送至地址总线

HEX

Page 14: Internal architecture of 8086/8088 CPU

Why not use physic address Why not use physic address directly?directly?

The word length of 8086/8088 CPU is 16 The word length of 8086/8088 CPU is 16 bits.bits.

In other words, the register in CPU is 16 In other words, the register in CPU is 16 bits register.bits register.

However, the address bus has 20 address However, the address bus has 20 address lines.lines.

Page 15: Internal architecture of 8086/8088 CPU

Transform logic address to physic Transform logic address to physic addressaddress

ExampleExample ::Physic AddressMemory cell ( Byte )10000H10001H10002H10003H10004H10005H10006H

SEG=1000H

Logic Address

OFFSET=0004H

Page 16: Internal architecture of 8086/8088 CPU

Execute UnitExecute Unit

(1) Execute Control Circuit: (1) Execute Control Circuit: Automatically read instruction from queueAutomatically read instruction from queue

Decode instruction and generate control Decode instruction and generate control signalssignals

Send control signals based on temporal Send control signals based on temporal logic prescribed by instructionlogic prescribed by instruction

Page 17: Internal architecture of 8086/8088 CPU

Execute UnitExecute Unit(2) ALU (Arithmetic and Logic Unit)(2) ALU (Arithmetic and Logic Unit)Execute arithmetic or logic operation prescribed Execute arithmetic or logic operation prescribed by instructionby instruction

Arithmetic operation: +, -, *, / of integerArithmetic operation: +, -, *, / of integer

Logic operation: and, or, not, xor of boolLogic operation: and, or, not, xor of bool

8088 can only operate integer, can not operate 8088 can only operate integer, can not operate float. (float operation executed by 8087)float. (float operation executed by 8087)

Page 18: Internal architecture of 8086/8088 CPU

Registers in 8086/8088Registers in 8086/8088

(1) Segment Registers(1) Segment Registers(2) Address Pointer Registers(2) Address Pointer Registers(3) Data Registers(3) Data Registers(4) Flag Register(4) Flag Register

Page 19: Internal architecture of 8086/8088 CPU

Segment RegistersSegment Registers

Segment base values are stored in these Segment base values are stored in these registers.registers.

When address transformation (logic to When address transformation (logic to physic) occurs, physic) occurs, segment registersegment register provide provide segment base value to segment base value to address adderaddress adder..

Page 20: Internal architecture of 8086/8088 CPU

Segment RegistersSegment Registers

There are four segment registers in There are four segment registers in 8086/8088 CPU:8086/8088 CPU:

CS (Code Segment)CS (Code Segment)DS (Data Segment)DS (Data Segment)SS (Stack Segment)SS (Stack Segment)ES (Extra Segment)ES (Extra Segment)

Page 21: Internal architecture of 8086/8088 CPU

Segment ManagementSegment Management

Instructions (program) are stored in code Instructions (program) are stored in code segment.segment.

Variables used by program are stored in Variables used by program are stored in data segment.data segment.

Return points (address) of procedure or Return points (address) of procedure or interrupt service routine are stored in stack interrupt service routine are stored in stack segment.segment.

Page 22: Internal architecture of 8086/8088 CPU

Address Pointer RegistersAddress Pointer Registers

Offset (Effective Address) of logic address Offset (Effective Address) of logic address is stored in address pointer registers.is stored in address pointer registers.

Address pointer registersAddress pointer registers can provide can provide offset to offset to address adderaddress adder..

Page 23: Internal architecture of 8086/8088 CPU

Address Pointer RegistersAddress Pointer Registers

There are six address pointer registers in There are six address pointer registers in 8086/8088.8086/8088.

BX (Base Index)BX (Base Index)BP (Base Pointer)BP (Base Pointer)SI (Source Index)SI (Source Index)DI (Destination Index)DI (Destination Index)SP (Stack Pointer)SP (Stack Pointer)IP (Instruction Pointer)IP (Instruction Pointer)

Page 24: Internal architecture of 8086/8088 CPU

Address Pointer RegistersAddress Pointer Registers

BX, BP, SI, DI can store offset or offset element.BX, BP, SI, DI can store offset or offset element.

Generally, DS and ES provide segment base Generally, DS and ES provide segment base value for BX, SI, and DI.value for BX, SI, and DI.

Generally, SS provides segment base value for Generally, SS provides segment base value for BP.BP.

In string operation instruction, SI is only used In string operation instruction, SI is only used with DS, and DI is only used with ES.with DS, and DI is only used with ES.

Page 25: Internal architecture of 8086/8088 CPU

Address Pointer RegistersAddress Pointer Registers

SP and IP store offset, not offset element.SP and IP store offset, not offset element.

Only SS can provide segment base value Only SS can provide segment base value to SP, and to SP, and SP always points to stack SP always points to stack toptop..

Only CS can provide segment base value Only CS can provide segment base value to IP, and to IP, and IP always points to the next IP always points to the next instructioninstruction which BIU will read. which BIU will read.

Page 26: Internal architecture of 8086/8088 CPU

Data RegisterData RegisterThere are four data registers in 8086/8088.There are four data registers in 8086/8088.

Data registersData registers provide binary data for provide binary data for ALUALU..

AX (Accumulator)AX (Accumulator)BX (Base Index)BX (Base Index)CX (Counter)CX (Counter)DX (Data Register)DX (Data Register)

Notice: BX is both address pointer and data register.Notice: BX is both address pointer and data register.

Page 27: Internal architecture of 8086/8088 CPU

Data RegisterData RegisterEach data register can be regarded as two 8-bit Each data register can be regarded as two 8-bit registers.registers.

AX: AH, ALAX: AH, ALBX: BH, BLBX: BH, BLCX: CH, CLCX: CH, CLDX: DH, DLDX: DH, DL

Note: Note: LogicallyLogically AX, AH, and AL are AX, AH, and AL are different different registers, but AX registers, but AX overlapoverlap AH and AL AH and AL physicallyphysically..

Page 28: Internal architecture of 8086/8088 CPU

Flag RegisterFlag Register

Flag register (FR) is a special 16-bit Flag register (FR) is a special 16-bit register.register.

Each bit of this register has individual and Each bit of this register has individual and different meaning, and it is called as different meaning, and it is called as flagflag..

There are two kind of flags in FR, which There are two kind of flags in FR, which are are status flagsstatus flags and and control flagscontrol flags..

Page 29: Internal architecture of 8086/8088 CPU

Status Flags in FRStatus Flags in FR

CF (Carry Flag)CF (Carry Flag)OF (Overflow Flag)OF (Overflow Flag)PF (Parity Flag)PF (Parity Flag)AF (Auxiliary Flag)AF (Auxiliary Flag)SF (Sign Flag)SF (Sign Flag)ZF (Zero Flag)ZF (Zero Flag)

These flags are These flags are affected by ALUaffected by ALU..

Page 30: Internal architecture of 8086/8088 CPU

Status Flags in FRStatus Flags in FR

Instructions do not affect status flags Instructions do not affect status flags directly, directly,

but but arithmeticarithmetic and and logiclogic operation operation instructions often instructions often affect them indirectlyaffect them indirectly..

For example:For example:ADD AL, BL ; FR is affected indirectlyADD AL, BL ; FR is affected indirectly

Page 31: Internal architecture of 8086/8088 CPU

Status Flags in FRStatus Flags in FRArithmetic and logic operation instructions Arithmetic and logic operation instructions writewrite the status flag to represent the status of the status flag to represent the status of operation result.operation result.

Program transfer instructions readProgram transfer instructions read the status the status flag to realize the branch or loop structure in flag to realize the branch or loop structure in program.program.

The status flags are The status flags are necessary hardware necessary hardware support for branch or loop structure in support for branch or loop structure in programprogram..

Page 32: Internal architecture of 8086/8088 CPU

Status Flags in FRStatus Flags in FR

If a status flag is valid, the following conditions If a status flag is valid, the following conditions must be satisfied.must be satisfied.

1) One instruction executed 1) One instruction executed must have affectedmust have affected this flag.this flag.

2) This affection 2) This affection must be validmust be valid..

3) Programmer’s explanation about Operation 3) Programmer’s explanation about Operation data data must be consistentmust be consistent with this flag. with this flag.

Page 33: Internal architecture of 8086/8088 CPU

Carry Flag (CF)Carry Flag (CF)

In most cases, programmer concern CF in In most cases, programmer concern CF in addition or subtraction instructions.addition or subtraction instructions.

Addition or subtraction instructions can Addition or subtraction instructions can provide valid effect to CF.provide valid effect to CF.

Page 34: Internal architecture of 8086/8088 CPU

Carry Flag (CF)Carry Flag (CF)

However, if CF is expected to use,However, if CF is expected to use,

programmer must programmer must regard operation dataregard operation data in last addition or subtraction as in last addition or subtraction as unsigned unsigned numbernumber, ,

except operation data is not integral, except operation data is not integral, and last operation is not the final oneand last operation is not the final one..

Page 35: Internal architecture of 8086/8088 CPU

Understanding Non-integral Understanding Non-integral OperationOperation

Consider a 16-bit addition, when CPU execute it Consider a 16-bit addition, when CPU execute it with two 8-bit addition instruction, it will execute with two 8-bit addition instruction, it will execute lower 8-bit addition first.lower 8-bit addition first.

When CPU process the lower 8-bit code, does it When CPU process the lower 8-bit code, does it know this is not an integral code?know this is not an integral code? NO

Then who knows?

The programmer know it exactly, and this knowledgeis presented in the flag usage in his (her) program.

Page 36: Internal architecture of 8086/8088 CPU

Carry Flag (CF)Carry Flag (CF)

Meaning:Meaning:

In last addition or subtraction, if there is In last addition or subtraction, if there is carry or borrow at the highest bitcarry or borrow at the highest bit (7th (7th bit of byte, or 15th of word), CF=1.bit of byte, or 15th of word), CF=1.

Or else, CF=0.Or else, CF=0.

Page 37: Internal architecture of 8086/8088 CPU

Carry Flag (CF)Carry Flag (CF)

For example:For example:

   1011001110110011+ + 01010001010100011 1 0000010000000100

CF =1CF =1

Page 38: Internal architecture of 8086/8088 CPU

Carry Flag (CF)Carry Flag (CF)

For example:For example:

0011000000110000++ 000011010000110100 0011110100111101

CF=0CF=0

Page 39: Internal architecture of 8086/8088 CPU

Carry Flag (CF)Carry Flag (CF)

For example:For example:

0101010101010101-- 001111100011111000 0001011100010111

CF=0CF=0

Page 40: Internal architecture of 8086/8088 CPU

Carry Flag (CF)Carry Flag (CF)Example of False judgment:Example of False judgment:[-00111110][-00111110] 补补 = 11000010= 11000010

0101010101010101++ 110000101100001011 0001011100010111

CF=1? CF=1? No, this is unsigned number operation, No, this is unsigned number operation, remember?remember?

Page 41: Internal architecture of 8086/8088 CPU

Carry Flag (CF)Carry Flag (CF)

In modern microcomputers, subtraction is In modern microcomputers, subtraction is realized by addition of complementary realized by addition of complementary codes.codes.

However, the generation circuit of CF is However, the generation circuit of CF is not correspondent with this operation.not correspondent with this operation.

Page 42: Internal architecture of 8086/8088 CPU

Application of CFApplication of CF

(1) In last operation which affected CF, if (1) In last operation which affected CF, if the operation data is integral, CF can the operation data is integral, CF can present if there is present if there is overflow of unsigned overflow of unsigned datadata..

(2) In (2) In long data operation (not care what long data operation (not care what data code)data code), CF can join the lower-bit and , CF can join the lower-bit and the higher-bit operation.the higher-bit operation.

Page 43: Internal architecture of 8086/8088 CPU

Application of CFApplication of CF

Important: Important: CF is the physic base for CF is the physic base for long data (longer than CPU word) long data (longer than CPU word) operationoperation..

(3) CF can be used to judge the relation (3) CF can be used to judge the relation between two unsigned code. (<, between two unsigned code. (<, >, =>, =))

(4) In bit shift operation, CF is used to (4) In bit shift operation, CF is used to store the last bit shift out from a cell.store the last bit shift out from a cell.

Page 44: Internal architecture of 8086/8088 CPU

Parity Flag (PF)Parity Flag (PF)

If an arithmetic or logic instruction affected If an arithmetic or logic instruction affected PF, PF,

and and the number of ‘1’ is eventhe number of ‘1’ is even in the lowest in the lowest 8 bits of the operation result, 8 bits of the operation result, PF=1.PF=1.

Or else, PF=0Or else, PF=0..

Page 45: Internal architecture of 8086/8088 CPU

Application of PFApplication of PF

Example:Example:ASCII code of character is 7-bit.ASCII code of character is 7-bit.

The 7th bit can be used as verifying bit.The 7th bit can be used as verifying bit.

Adjust 7th bit of ASCII code, and ensure Adjust 7th bit of ASCII code, and ensure the number of “1” in code is odd. the number of “1” in code is odd. (Odd (Odd Verifying)Verifying)

Page 46: Internal architecture of 8086/8088 CPU

Application of PFApplication of PF

Send this code to another computer with Send this code to another computer with network.network.

The receiver can verify the correctness of The receiver can verify the correctness of this code by following instruction, if the this code by following instruction, if the code is in AL register.code is in AL register.

ADD AL, 0ADD AL, 0

Page 47: Internal architecture of 8086/8088 CPU

Auxiliary Carry Flag (AF)Auxiliary Carry Flag (AF)

AF represent the carry of addition or borrow of AF represent the carry of addition or borrow of subtraction, just like CF.subtraction, just like CF.

However, it However, it represent the carry or borrow at represent the carry or borrow at 3th bit of operation result3th bit of operation result..

So, AF is also called half carry flag.So, AF is also called half carry flag.

Note: Some instruction may provide AF invalid Note: Some instruction may provide AF invalid effect. (effect. (may be changed, but not validmay be changed, but not valid))

Page 48: Internal architecture of 8086/8088 CPU

Application of AFApplication of AF

BCDBCD code: A kind of binary code to code: A kind of binary code to represent decimal datarepresent decimal data

Use 4 bit to represent one single digit of Use 4 bit to represent one single digit of decimal data.decimal data.

Limit the range by 0000~1001 (0~9)Limit the range by 0000~1001 (0~9)

Page 49: Internal architecture of 8086/8088 CPU

Application of AFApplication of AF

AF can represent the carry or borrow from AF can represent the carry or borrow from lower BCD code to higher one (lower BCD code to higher one (also a hex also a hex carry or borrowcarry or borrow).).

01234567

Carry

Borrow

Page 50: Internal architecture of 8086/8088 CPU

Application of AFApplication of AF

If the binary (hex) carry or borrow can be If the binary (hex) carry or borrow can be adjust to decimal, adjust to decimal,

the binary (hex) operation can also be the binary (hex) operation can also be transformed to decimal.transformed to decimal.

AF is necessary for BCD adjustment AF is necessary for BCD adjustment instructionsinstructions..

Page 51: Internal architecture of 8086/8088 CPU

Zero Flag (ZF)Zero Flag (ZF)

If an arithmetic or logic instruction affected If an arithmetic or logic instruction affected PF,PF,

and the operation result is zero, and the operation result is zero, ZF=1ZF=1..

Or else, Or else, ZF=0ZF=0..

Page 52: Internal architecture of 8086/8088 CPU

Application of ZFApplication of ZF

Used by program transfer instructions to Used by program transfer instructions to realize branch and loop structurerealize branch and loop structure

Often used to judge if two binary codes Often used to judge if two binary codes are equal are equal

Often used with other status flags to judge Often used with other status flags to judge more complex relation between two codes more complex relation between two codes (including ‘(including ‘≤’ and ‘≥’≤’ and ‘≥’))

Page 53: Internal architecture of 8086/8088 CPU

Sign Flag (SF)Sign Flag (SF)If an arithmetic or logic instruction affected SF,If an arithmetic or logic instruction affected SF,

and programmer consider operation data as and programmer consider operation data as signed code (signed code (integral codeintegral code or or highest bits of highest bits of codecode))

SF represent the sign of operation result.SF represent the sign of operation result.

Note: Only if the Note: Only if the highest bit is the signhighest bit is the sign of of complementary code, complementary code, SF can be explainedSF can be explained as as the sign.the sign.

Page 54: Internal architecture of 8086/8088 CPU

Problem of SFProblem of SF

SF is always equal to the highest bit of SF is always equal to the highest bit of operation result.operation result.

However, is this sign flag However, is this sign flag always correct?always correct?

Page 55: Internal architecture of 8086/8088 CPU

Application of SFApplication of SF

Along with OF (Overflow Flag), it can be Along with OF (Overflow Flag), it can be used to judge the relation between two used to judge the relation between two signed code.signed code.

Along with OF, it is used by program Along with OF, it is used by program transfer instructions to realize branch or transfer instructions to realize branch or loop structure based on relation between loop structure based on relation between two signed codes.two signed codes.

Page 56: Internal architecture of 8086/8088 CPU

Overflow Flag (OF)Overflow Flag (OF)If an arithmetic or logic instruction affected OF,If an arithmetic or logic instruction affected OF,

and programmer consider operation data as and programmer consider operation data as signed code (signed code (integral codeintegral code or or highest bits of highest bits of codecode))

OF represent if the operation result is out of OF represent if the operation result is out of range.range.

Note: Only if the Note: Only if the highest bit is the signhighest bit is the sign of of complementary code, complementary code, OF is valid.OF is valid.

Page 57: Internal architecture of 8086/8088 CPU

Overflow Flag (OF)Overflow Flag (OF)

Byte range of signed code: Byte range of signed code: -128~127-128~127

Word range of signed code: Word range of signed code: -32768~32767-32768~32767

If the operation result is out of range, OF=1.If the operation result is out of range, OF=1.

Or else, OF=0.Or else, OF=0.

Page 58: Internal architecture of 8086/8088 CPU

OF GenerationOF Generation

Three possible combinations in signed addition Three possible combinations in signed addition or subtraction can appear.or subtraction can appear.

positive + negativepositive + negativepositive + positivepositive + positivenegative + negativenegative + negative

Other combinations can be transformed to Other combinations can be transformed to one of them.one of them.

Page 59: Internal architecture of 8086/8088 CPU

OF GenerationOF Generation

(1) positive + negative (1) positive + negative equivalence: equivalence: positive-positive, negative- negativepositive-positive, negative- negative

No overflow at all, why?No overflow at all, why?

The absolute value of operation result is less The absolute value of operation result is less than the operation data which has greater than the operation data which has greater absolute value.absolute value.

Page 60: Internal architecture of 8086/8088 CPU

OF GenerationOF Generation

(2) positive+positive(2) positive+positive

equivalence: positve-negativeequivalence: positve-negative

If the result is positive, OF=0.If the result is positive, OF=0.

Or else, OF=1.Or else, OF=1.

Page 61: Internal architecture of 8086/8088 CPU

OF GenerationOF Generation

(3) negative+negative(3) negative+negative

equivalence: negative-positiveequivalence: negative-positive

If the result is negative, OF=0.If the result is negative, OF=0.

Or else, OF=1.Or else, OF=1.

Page 62: Internal architecture of 8086/8088 CPU

OF GenerationOF Generation

Does Does missing sign bitmissing sign bit in signed operation is in signed operation is equal to operation equal to operation overflowoverflow??

First, consider the addition of two greatest First, consider the addition of two greatest positive code.positive code.

0111111101111111+ 01111111+ 011111110 100000000 10000000

Yes

Page 63: Internal architecture of 8086/8088 CPU

OF GenerationOF Generation

Then, consider the addition of two smallest Then, consider the addition of two smallest negative code. negative code.

1000000010000000+ 10000000+ 100000001 000000001 00000000

If consider the carry of highest bit, the result If consider the carry of highest bit, the result is correct.is correct.

Page 64: Internal architecture of 8086/8088 CPU

Application of OFApplication of OF

Basically, OF can be used to Basically, OF can be used to judge if there is judge if there is signed overflow in last operationsigned overflow in last operation..

Along with SF, OF is often used to Along with SF, OF is often used to judge the judge the relation between two signed codesrelation between two signed codes..

Based on SF and OF, program transfer Based on SF and OF, program transfer instructions can instructions can realize branch or loop realize branch or loop structure based on signed operationstructure based on signed operation in in program.program.

Page 65: Internal architecture of 8086/8088 CPU

Control Flags in FRControl Flags in FR

Besides the status flags, there are control Besides the status flags, there are control flags in FR, which is flags in FR, which is used to control the used to control the operation mode of CPUoperation mode of CPU..

Unlike the status flags, there are Unlike the status flags, there are instructions which can directly set the instructions which can directly set the control flagscontrol flags..

Page 66: Internal architecture of 8086/8088 CPU

Trace Flag (TF)Trace Flag (TF)

When TF is set to 1, CPU execute When TF is set to 1, CPU execute program step by step, and execute trace program step by step, and execute trace routine after each instruction is executed.routine after each instruction is executed.

The trace routine display CPU register The trace routine display CPU register status on screen for debug.status on screen for debug.

The trace routine will not executed in trace The trace routine will not executed in trace mode.mode.

Page 67: Internal architecture of 8086/8088 CPU

Trace Flag (TF)Trace Flag (TF)

If TF is set to 0, the program is executed If TF is set to 0, the program is executed by CPU continuously.by CPU continuously.

TF is the hardware support to trace TF is the hardware support to trace mode of program debug.mode of program debug.

Page 68: Internal architecture of 8086/8088 CPU

Interrupt enable Flag (IF)Interrupt enable Flag (IF)

When IF is set to 1, after current instruction has When IF is set to 1, after current instruction has been executed, CPU will accept maskable been executed, CPU will accept maskable interrupt sent by interface.interrupt sent by interface.

Or else, CPU will not accept maskable interrupt.Or else, CPU will not accept maskable interrupt.

In programs which is strict with exectution time, In programs which is strict with exectution time, one can disable maskable interrupt with IF.one can disable maskable interrupt with IF.

Page 69: Internal architecture of 8086/8088 CPU

Direction Flag (DF)Direction Flag (DF)

DF is used to control the direction of string DF is used to control the direction of string operation.operation.

In string operation instructions, SI register In string operation instructions, SI register is used to point current byte (or word) in is used to point current byte (or word) in source string, and DI is used to point source string, and DI is used to point destination string.destination string.

Page 70: Internal architecture of 8086/8088 CPU

Direction Flag (DF)Direction Flag (DF)

When DF is set 0, SI and DI are increased When DF is set 0, SI and DI are increased after string operation.after string operation.

Or else, SI and DI are decreased after Or else, SI and DI are decreased after string operation.string operation.

Page 71: Internal architecture of 8086/8088 CPU

Learning flags in FRLearning flags in FR

Learning flags in FR is crucial for CPU Learning flags in FR is crucial for CPU theory and assembler language theory and assembler language understanding, especially status flags.understanding, especially status flags.

Only learning the meaning of flags Only learning the meaning of flags themselves are not enough.themselves are not enough.

The flags can only be understand well with The flags can only be understand well with instructions.instructions.

Page 72: Internal architecture of 8086/8088 CPU

Learning flags in FRLearning flags in FRNote:Note:

In arithmetic or logic operation instructions, learn In arithmetic or logic operation instructions, learn how these instructions affect status flags, and how these instructions affect status flags, and understand the meaning of flags with these understand the meaning of flags with these instructionsinstructions

In program transfer operation instructions, learn In program transfer operation instructions, learn how these instructions use status flags, and how these instructions use status flags, and what transfer instruction can be used in given what transfer instruction can be used in given conditions.conditions.

Page 73: Internal architecture of 8086/8088 CPU

Register Class (1)Register Class (1)

Segment Register (BIU, Address Adder)Segment Register (BIU, Address Adder)

Address Point Register (BIU, Address Address Point Register (BIU, Address Adder)Adder)

Data Register (EU, ALU)Data Register (EU, ALU)

Flag Register (EU, ALU, indirectly)Flag Register (EU, ALU, indirectly)

Page 74: Internal architecture of 8086/8088 CPU

Register Class (2)Register Class (2)

1) 1) General (Universal) RegisterGeneral (Universal) Register: : Registers can provide operation data to Registers can provide operation data to ALU.ALU.

Data registers and most of address Data registers and most of address point registerspoint registers are general registers are general registers (except IP).(except IP).

Page 75: Internal architecture of 8086/8088 CPU

Register Class (2)Register Class (2)

Control RegisterControl Register: Registers can affect the : Registers can affect the program execution flow directly or program execution flow directly or indirectly.indirectly.

IP (affect execution flow directly)IP (affect execution flow directly)FR (indirectly)FR (indirectly)

Segment RegisterSegment Register: provide segment base : provide segment base value to address addervalue to address adder

Page 76: Internal architecture of 8086/8088 CPU

Uniqueness of RegistersUniqueness of Registers

In 8086/8088 CPU, each register is In 8086/8088 CPU, each register is different from others, and has least one different from others, and has least one unique function. unique function.

This is also true in most other CPUs.This is also true in most other CPUs.

For initial learning, remembering their For initial learning, remembering their special function is helpful.special function is helpful.

Page 77: Internal architecture of 8086/8088 CPU

Note for register usage in programNote for register usage in program

(1) implied usage of register in instruction(1) implied usage of register in instruction

The register does not appear in instruction The register does not appear in instruction format, but it is affected by instruction execution.format, but it is affected by instruction execution.

(2) restricted usage of register in instruction(2) restricted usage of register in instruction

In some instructions, only one special register In some instructions, only one special register can be used as a operation data.can be used as a operation data.

Page 78: Internal architecture of 8086/8088 CPU

implied usage of register in implied usage of register in instructioninstruction

Examples:Examples:PUSH AXPUSH AX ;; implied SPimplied SPPOPFPOPF ;; implied FRimplied FRMUL BLMUL BL ;; implied ALimplied AL ,, AXAXLOOP L1LOOP L1 ;; implied CXimplied CX ,, IPIPAAAAAA ;; implied ALimplied AL ,, AHAH

Page 79: Internal architecture of 8086/8088 CPU

implied usage of register in implied usage of register in instructioninstruction

If programmer does not know implied usage of If programmer does not know implied usage of register in instructions, logic errors is easy to register in instructions, logic errors is easy to appear in his (her) programs.appear in his (her) programs.

Logic errors can not be found by assembler Logic errors can not be found by assembler tools.tools.

Only program debug can solve these problems.Only program debug can solve these problems.

Page 80: Internal architecture of 8086/8088 CPU

restricted usage of register in restricted usage of register in instructioninstruction

Examples:Examples:

SHL ALSHL AL ,, CLCL ;; restricted with CLrestricted with CLIN ALIN AL ,, 54H54H ;; restricted with ALrestricted with ALOUT DXOUT DX ,, ALAL ;; restricted with DXrestricted with DX ,, ALAL

False usage in restricted position only False usage in restricted position only cause syntax errors and they can be found cause syntax errors and they can be found by assembler tools.by assembler tools.