Accelerating the next technology

revolution

Copyright ©2012

SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center

and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

Accelerating the next technology revolution

Copyright ©2012

SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center

and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

Sitaram Arkalgud

Sr Director – Interconnect/3D IC

Ph: +1 518 649 1116

Interconnect Opportunities:

A SEMATECH Perspective

Annual SEMATECH Korea Symposium October 24, 2012

Industry challenges for interconnect

High bandwidth

- From Gb/s to Tb/s

Low power

- From mJ/b to pJ/b to fJ/b

High functionality

- Connecting CMOS, MEMs,

optical, bio …

Small footprint

Interconnects consume >80% of Total

Chip Power

Total Chip Power limited to ~200W

D. Miller, Proc IEEE 97, 1166 (2009)

18 October 2012 2

Inter/Intrachip interconnect solutions

• 2D scaling issues

– Rising Cu resistivity

– Poor mechanical properties of porous low k

dielectric

• 3D Interconnect with TSVs

– High bandwidth

– Lower power consumption

– High functionality platform

– Small footprint

• Next generation interconnect

– Optical interconnects, new materials

– Higher bandwidth

– Lower power consumption

18 October 2012 3

2013

3D Interconnect roadmap

2012

memory memory Logic

Si TSV interposer

memory memory

Heat Sink and

TIM

3D Interposer

2015 2020

3D+

memory memory Logic

Si TSV interposer

memory

memory

Heat Sink and TIM

NAND Analog

NGI?

Production

Development

Pre-Development

Courtesy: WWW.Intel.com

Gaps relevant to SEMATECH (3 to 5 years)

- TSV scaling

- Package (Chip to Chip) interconnect scaling

- Package interactions

- Chip Package Pathfinding

- Next Generation Interconnect

18 October 2012 4

Driving forces in 3D stacking

Scaling in 3D will be new industry goal, as first products enter HVM

– TSV diameter scaling

• Drivers: Increased bandwidth, increased TSV redundancy (yield), decreased Keep out Zone/Lower active Si area penalty

• Challenge: Higher aspect ratio TSV driving new equipment and processes (unless die thickness scales)

– Wafer/die thickness scaling

• Drivers: Thinner package height, increased number of dies in stack, lower TSV aspect ratios

• Challenges: Thermo-mechanical issues with handling thinner wafers/die (stress and yield)

– Chip – chip interconnect scaling

• Drivers: Increased bandwidth, interconnect redundancy (yield)

• Challenges: Reliable scaling of solder based systems, CoO of Cu Direct Bonding

18 October 2012 5

3D Program capabilities

300mm Toolset

• Wafer bonding

• Die bonding

• TSV RIE

• TSV clean

• Cu plating

• Wafer backgrind

• TSV reveal (backside)

• 3D metrology

• Temporary bond/debond

Modeling and simulation

Other tools and metrology

from CSR/CCIC and ISMI

Reliability

• TDDB

• Electromigration

• Thermal Cycling

• Package Reliability

Infrastructure

• Reference Flows

• Standards

• Industry Gaps

HVM Readiness

• Cost Modeling

• Eqpt Maturity Assessment

• Pathfinding

Test Vehicles

• Process (underfill, bond)

• Passive daisy chains

• Package (> 2 layers)

• Active (device + TSV)

18 October 2012 6

Scaling of chip to chip interconnects

Bonding Method

C4 FC (Contolled

Collapse Chip

Connect)

C2 FC

(Chip Connect)

TC/LR (Local

Reflow) FC TC FC

Schematic Diagram

Major Bump Pitch Range at

Application > 130 um 140 um ~ 60 um 80 um ~ 20 um < 30 um

Bonding Method

Conventional

Reflow

Reflow with Cu

pillar

Thermal

Compression

with Cu pillar

Thermal

Compression

Bump Metallurgy Solder (SnAg or

SnAgCu)

Cu + Solder

(SnAg or Sn)

Cu + Solder

(SnAg or Sn)

Cap

Cu

Bump Collapse Yes No No No

Underfill Method - Capillary

- No flow

- Capillary

- No flow

- Wafer Level

- No flow

- Wafer Level

- No flow

- Wafer Level

2012 TSV

2014/15 TSV

< ITRS 14nm node

18 October 2012 7

Cu Direct Bond–addressing throughput

• Conventional process (400ºC) has

a throughput of ~0.5 WPH – Vacuum requirement and high bond

temperature impact throughput

• Feasibility of low temperature

(~200ºC, 5 min) process

demonstrated on blanket wafers – Main factors identified

– Process below Pb-free reflow

temperatures introduces compatibility

with all modern packaging materials

• New tool concept proposed to

increase throughput to 30 WPH – 88% reduction in COO

25 April 2012 8

POR

Low T

Process

New Tool

Concept

Cu-Cu bond

Interface

200ºC/10min

2012 Activities: Cu direct bonding

18 October 2012 9

Cu direct bonding of patterned wafers at 245C 5 min

Mechanical test wafer bonded at 195C 5 min

Blanket Cu wafers bonded at 195C 5 min

PVD only

(6 weeks CuO growth)

Plated & Polished

(2 weeks)

XPS studies of Cu surfaces

Grain orientation studies of Cu films

2012 Activities: Thin wafer/die handling

50 um thin wafer

debonded on tape frame

Incoming Inspection of 50

um wafers successfully

debonded (SEMI D5175 )

Shock Sensor Locations

(SEMI D5175)

FEM of thin wafer

debonded on tape frame

(SEMI D5175)

18 October 2012 10

2012 Activities: TSV scaling

20: 1 aspect ratio (2x40 um) TSV test

structures

Dielectric liner integrity

evaluations (5x50 um) for scaling

Barrier/seed step coverage issues

(2x40 um) TSV test structures

18 October 2012 11

3D Enablement Center: chip interoperability

• Program announced by SEMATECH, SIA, and SRC in Dec 2010 :

– Mission: Enable industry-wide ecosystem readiness for cost-effective TSV-based 3D stacked IC solutions

• Key Accomplishments to-date

– Identified technical requirements, key challenges and approaches for 2.5D and 3D assembly flows

– Launched standards dashboard with support from SEMI, JEDEC, IEEE, and Si2 (wiki.sematech.org)

– Leading SEMI 3DS-IC task forces on Thin Wafer Carriers, Bonded Wafer Stacks, and Inspection and Metrology. First SEMI standard approved; 10 more in preparation

– Issued inspection and metrology reports covering bond voids, TSV voids, bonded wafer bow/warp

– Preparing reports on microbump and stacked die inspection

– Delivered landscape reports on assembly materials and bumping/bonding technologies

– Sponsoring research through SRC on 3D reliability and design issues (in progress)

(July 2012)

18 October 2012 12

SEMATECH’s interconnect program timeline

Program 2013 2014 2015 2016 2017

Thin Die/Wafer Handling

C2C Interconnect Scaling

TSV Scaling

Z- Height Scaling

Cu Direct Bond

Limits of < 25 um thick die processing (Eg: 10 – 25 um)

40 um thick Die/wafer readiness

D2W Process Readiness W2W Process Readiness

10 um pitch

• CoO, Equipment Maturity Assessments, landscape reviews, metrology will be addressed

• Collaborations with key suppliers and university/research partners is expanding • CNSE, Binghamton, SRC, GIT, UT-Austin, Fraunhofer, RPI, NCSU and Penn State

• Next Generation Interconnects will be monitored and launched as appropriate

Limits of scaling CuDB technology

2x40 um Technology

evals; yield & basic reliability

<2 um diameter, 15 – 20 AR development Technology evaluations

25 um thick Die/wafer readiness

2x40 um Reliability (EM, TC, TDDB,

package)

W2W CuDB learning D2W/D2D readiness

18 October 2012 13

Stages Cu 2D Cu 3D Optical Graphene CNT

Concept X X X X X

Mechanisms X X X X X

Reference Flow X X X

Materials Selection X X X

Device Feasibility X X X

Module Development X X

Equipment Hardening X X

Infrastructure X X

Reliability X X

HVM X X

C&F

UPD

Module

Interconnect Options

Maturity of interconnect options

Best candidate for

HVM development

Relatively immature for

HVM

14 18 October 2012

Scaling of chip to chip interconnects

Bonding Method

C4 FC (Contolled

Collapse Chip

Connect)

C2 FC

(Chip Connect)

TC/LR (Local

Reflow) FC TC FC

Schematic Diagram

Major Bump Pitch Range at

Application > 130 um 140 um ~ 60 um 80 um ~ 20 um < 30 um

Bonding Method

Conventional

Reflow

Reflow with Cu

pillar

Thermal

Compression

with Cu pillar

Thermal

Compression

Bump Metallurgy Solder (SnAg or

SnAgCu)

Cu + Solder

(SnAg or Sn)

Cu + Solder

(SnAg or Sn)

Cap

Cu

Bump Collapse Yes No No No

Underfill Method - Capillary

- No flow

- Capillary

- No flow

- Wafer Level

- No flow

- Wafer Level

- No flow

- Wafer Level

Maximum Bandwidth/channel > 5Tb/s

Optical

Interconnect

10Gb/s

Optical interconnects promise very high bandwidth at low power

18 October 2012 15

Why silicon photonics?

All components of a Silicon Photonic Interconnect have been demonstrated:

Silicon photonics is a promising technology:

High Bandwidth (>200 THz)

Low Power (<100 fJ/bit)

Compact Devices (< 2mm3)

Compatible with Fiber Optics

Seamless CMOS Integration

Silicon Photonic Circuit

Laser Electro-Optic Modulator Photodetector

Intel/UCSB – III-V Bonded Laser

MIT – Ge Laser Cornell University – Microring Modulator

Intel – Ge Detector

16 18 October 2012

SEMATECH’s Si photonic building blocks

17 18 October 2012

Lasers Modulators Detectors Waveguides

Interconnects Heaters Gratings Switches

SEMATECH has a complete Silicon photonic device library using a 300mm reference flow

SEMATECH has state of the art capabilities for photonics development

Future evolution: Si nanophotonics

18 18 October 2012 SEMATECH Confidential

Nano-Waveguide

SPP Si Light Source Plasmonic Modulator

Nano-Detector

Light Guiding

Light Emission Optical Modulation

Optical Detection

Micro-Photonics (>> mm) Nano-Photonics (≤ mm)

Plasmonics-Enabled Nanophotonics

Building BlocksChallenge for Nano-Photonics:

Size and performance of photonics devices are constrained by the optical diffraction limit.

Solution:Plasmonics enables optical signal to be squeezed into nano-photonics devices, shrinking its / 10.

E-IC: Nano-Scale

P-IC: » Micron-Scale

Summary

• Interconnect is a critical component of today’s integrated circuit

– Power consumption and bandwidth/performance are key bottlenecks

• TSVs and 3D stacking face HVM readiness concerns - Pathfinding tools, cost implications, tool maturity, stack yield

- Thermal/stress management, thin wafer/die handling, package

interactions

• Next Generation Interconnects offer promise of lower power

consumption and higher bandwidth

– Optical Interconnects at the system level: Photonics and nanophotonics

– Novel materials: Graphene, Carbon Nanotubes and nanowires

18 October 2012 19

3D Members and Partners

18 October 2012 20