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Highly Configurable Technology Independent System Validated
Product Brief
Integrated Flash Controller IP
Mobiveil Inc | 920 HillView Court | #250 | Milpitas | CA 95035PH: 408.791.2977 | f: 408.457.0406 | e: [email protected]
www.mobiveil.com
AXI System InterfaceAXI3 Compliant Slave Interface
NAND Flash
Features
IFC IP
AXI3 Compliant Master Interface with descriptor based internal DMA.
Supports ONFi 3.1 (NVDDR2) mode
Supports synchronous Toggle Mode 2.0 NAND interface
OverviewMobiveil's Integrated Flash Controller IP (IFC) is a high qualitydesign, proven till 28nm and targeted for consumer applica-tions like camera, audio players flash based storage drives,networking and communication devices, etc. The IFC is usedto access the external NAND Flash, NOR Flash, EPROM,SRAM and Generic ASIC memories. The controller architec-ture is carefully tailored to provide ease of integration to SoCand chip select to enable the use of memory banks depend-ing on the choice of memory.
The uniqueness of Mobiveil’s IFC is the reference designavailability on top of the core controller that helps customereasily adapt the controller to their SOC target technology.IFC’s AXI system interface makes it easy to be integrated intowide range of applications. IFC leverages Mobiveil’s years ofexperience in Hypertransport, PCI, PCIe and RapidIO technolo-gies and the expertise in creating system validated IPsolutions with RTL, synthesis, simulation, board and softwareelements to offer lowest risk in terms of compliance andinteroperability.
IFC is part of Mobiveil’s Storage and Memory controller familyof IP solutions which also includes DDR 4/3, LPDDR 2/3,UNEXTM , and eSDHC IP cores.
Supports x8/x16 NAND flash interface
BCH code up to 40 bit Error correction per sector
ECC generation/checking optional
Product Package
Documentation
Specifications
About Mobiveil
GPCM
NOR Flash
GASIC
Design Attributes
Mobiveil Inc | 920 HillView Court | #250 | Milpitas | CA 95035PH: 408.791.2977 | f: 408.457.0406 | e: [email protected]
www.mobiveil.com
Mobiveil Inc. reserves the right to change this document without prior notice and disclaim all warranties. It is the recipient's duty to confirm with Mobiveil Inc's Engineering Department specifications before proceeding with a product design. This document is confidential and should not be reproduced without Mobiveil Inc's approval.
Mobiveil, GRIO, GPEX, UNEX, UMMC, RAB, PAB, NVMStor are trademarks of Mobiveil Inc. Patents and Patents pending. ©2014 Mobiveil Inc. Milpitas, CA. All rights reserved.
Detailed Data-sheet, Integration, Synthesis Guide
Verification Guide
RTL Code
HVL based test bench
Test cases
Fully synchronous design
Software control for key features
NAND Flash (Contd. . .)
Flexible timing control to allow interfacing with proprietary NAND devices
Supports asynchronous NOR flash
Synchronous NOR Read support
Data Bus width of x8/16/32 bits
Support for x8/16/32-bit devices
External clock is supported by programmable division ratios
Even/odd parity on data bus supported
Configurable even/odd parity on address/data bus supported
Parity error detection support
Support for x8/16/32-bit devices where address and data sequences are shared on the same bus
Supports GPCM Burst with configurable size, upto 128 beats
Compatible with general-purpose addressable devices (SRAM and ROM)
Support address data multiplexed (ADM) NOR device
Flexible timing control allows interfacing with proprietary NOR devices (write enable controlled writes only)
SLC and MLC flash device support with configurable page sizes of up to 16KB
Support for advanced NAND commands (cache, copy-back and multi-plane programming)
Interrupt for error handling and flash command completion event
Internal SRAM of 18 KB
Flash devices with multiple terabytes of storage
Little endian pin indexing at IFC pin interface for easy connectivity with Memory device
Status
Availability
Language
Synthesis
Simulation Cadence, Synopsys, Mentor
Synopsys DC, Synplify-Pro
Verilog
GOLD
Technology 90nm ASIC or better, FPGA