INF 5460Electronic noise –Estimates and countermeasures

Lecture 13 (Mot 10)

Amplifier Architectures

• When a transistor is used in an amplifier, oscillator, filter, sensor, etc. it will also be a need for passive elements like resistors, capacitors and coils to provide biasing so that the transistor has the correct working point. These passive elements will influence on the noise. In the following we will look at some architectures and how they affect the equivalent input noise.

2

Miller capacitanceBefore we look at the transistor configurations we need a fast repetition of the Miller effect.

• When a capacitor is connected between a signal line and a stable potential the signal line will experience a capacitance according to the standard formula (C=A/t).

• If the potential on the other side are in phase a smaller capacitance will be experienced. If the signal is exactly equal the capacitance will "disappear".

• If the signal is in opposite phase the experienced capacitance will be larger. If it is in opposite phase and exactly equal the capacitance will be double.

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Transistor configurations:

CS/CE has both voltage and current amplification resulting in the highest gain. But it has also the highest input capacitance (due to the Miller effect)

CD/CC has a high current gain but a voltage gain close to one. It has a low input capacitance (from the Miller effect) resulting in a high input impedance. It also has low output impedance.

CG/CB is used to achieve low input impedance and high output impedance.

FET BJT

CS: Common Source

CE: Common Emitter

CD: Common Drain

CC: Common Collector

CG: Common Gate

CB: CommonBase

There are mainly three alternatives for placing a FET/BJT in an architecture:

4

10-2 Common EmitterThe schematic shows a transistor that is biased for low noise operation between 10Hz and 10kHz. The noise values are as follows:

The noise schematic shows a hybrid-model together with passive bias elements.

Note that when VEE and VCC are stable DC-sources that are merged together with ground during noise analysis.

10Hz 10kHzEn 2nV 2nVIn 2pA 0.3pAR0 1000 6700

NF@R0 1.8dB 0.3dB

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The voltage gain Kt:

Kt is the voltage gain from Vs to Vo. The first parenthesis is the voltage gain within the transistor ( is ICE/IBE) while the second parenthesis is the network in front of the base.

The input resistance Zi includes the resistance you can see through the base towards emitter.

The load resistance consists of the collector bias resistance, the transistor internal resistance and the input resistance of the next stage: Ri2.

The emitter impedance consists of a real part and an imaginary part (a resistance and a capacitance in parallel).

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The source impedance is a resistance in series with a capacitor.

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If we assume ignorable loss in biasing, coupling and feedback we can simplify the expression for Kt to:

If Zs ≪ r and ZE ≪ re the expression is simplified to:

If we simplify and ignore the external load we have:

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We will then have the following expression for the equivalent input noise:

In the expression, we recognise the first line (say from section. 7.3). Last term is also known. The second last term, however, need some comments. The voltage over RE will not be EE for higher frequencies, because CE will "attempt to short-circuit" this. We choose to model the thermal noise in RE as a current noise of size IE=EE/RE. The noise current over RE and CE will be:

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Back to the expression for Eni:

From the expression we find that to have low noise:

RD should be large relative to RS.

CC should be large.

Rs should be small.

RE should be small if CE is not large

CE should be large.

Kt should be large.

If the AC-coupling is not needed, we can remove RD and CC. CE (Common Emitter) has the greatest power amplification. Thus noise from stages following the amplifier can probably be ignored.

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Choice of capacitance values

CC is a high pass filter together with the resistances at the transistor gate (I.e. bias resistance in parallel with the transistor input resistance).With regard to noise, 1/(CC) should be much less than RS at the lowest relevant frequency. This is because these are added and determines the contribution of In: In(RS+j/(CC)). Obviously the last term should be tried made small (<1/100) relative to RS. NB! Hence due to noise CC must not be used intentionally for filter functions!

CE should short-circuit the emitter AC-wise to ground. The impedance of CE should be small relative to the internal resistance in the emitter: re. Basically noise in RE has the same weight as the noise in the source (gain=1), however CE will reduce the contribution from RE.

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Common-emitter with one voltage supply

• Here a point A is established supplying a stable DC potential for the base. The point A is AC-wise short circuited to ground through CB.

10Hz 10kHzEn 4.5nV 4.5nVIn 0.3pA 0.1pAR0 10k 45kNF@R0 0.68dB 0.35dBKt 280Ri 780

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The equivalent input noise can be expressed as:

In addition to the known terms, we have now a new term in square parenthesis due to the base bias network. The parenthesis is weighted with the RS/RD ratio.

The DC-voltage at the base is determined by the relationship between RA and RB as follows:

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The contributing noise from the resistors RA and RB should be relatively small. A good starting point is to choose CB so large that the noise in the relevant frequency range satisfies the inequality:

13

Noise in cascaded stagesWe have previously studied the noise figure for cascaded amplifiers. We will now look at the equivalent input noise:

The expression for equivalent input noise can be expressed as follows

Here ro1 is the output resistance of stage 1. Similarly for ro2, ro3 etc.

Kti is as earlier the voltage gain.

As previously if the gain is large enough in the first stage, noise from subsequent stages can be ignored.

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There are three methods one can use for noise analysis of more complex systems such as cascaded network:

• Manual network analysis (hand calculations),

• use a simulator (like LTspice), or

• measure the system after realisation.

Trick for simulation (and measurement): If you are unsure of the impact of noise from a source - simulate with this source only and inspect the simulation results at the output.

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Common-source --- common-emitter couple• CS provides high input

impedance and high voltage gain.

• The example uses a JFET but the considerations does also apply to MOSFETs.

10Hz 10kHzEn 8nV 4nVIn 7fA 7fAR0 1.1M 570kNF@R0 0.03dB 0.015dB

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The voltage amplification for the CS-stage is:

RL1 and ZS1 are given by:

and

The total voltage gain is:

When r2 ≫ RD1 and RC2 ≫ ro2

we have that:

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To reduce the En1-noise contribution from the FET we may consider increasing ID1. But this requires a smaller RD1 which means less total gain.

The expression for the equivalent input noise for this circuit is:

• RG1 must be large compared to RS

• CC1 must be large compared to RS

• CS1 must be sufficient large

• Kt1 should be large and

• Ktc should be large.

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Common-collector --- Common-emitterCC-CE has only a little larger En than a pure CE stage but can offer higher input resistance and lower input capacitance.

First stage has a gain of approx. 1. The total gain is:

Where

The expression for Ktc can be simplified when 1RL1 ≫ (RS+rx1+r1) and r2 ≫ rx2+2ZE2:

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Equivalent input noise is:

K’t1 is the gain in the first CC stage with RE1 as load.

• In CC and CD should the emitter/source resistance be large.

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Common-Emitter --- Common-BaseCE-CB has low input capacitance and high output impedance. Due to the low input resistance of the second stage the voltage gain of the first stage will be low. This reduces the high frequency feedback (Miller effect) through C as discussed before. The input capacitance is thus

much less than for a regular CE step.

Q1 provides power amplification but not voltage gain (i.e. Q1 provides a current gain.) Q2 provides a large voltage gain. RC1 is used to provide extra collector current to Q2 when there is a need for large gain-bandwidth.

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The total power gain can be expressed as:

Where

When RS=0 and RC1 ≫ r/2 we can simplify Ktc to:

The equivalent input noise is:

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10Hz 10kHz 10Hz 10kHz 10Hz 10kHz 10Hz 10kHz 10Hz 10kHz

En 2nV 2nV 4.5nV 4.5nV 8nV 4nV 6nV 5.8nV 1.6nV 1.4nV

In 2pA 0.3pA 0.3pA 0.1pA 7fA 7fA 0.3pA 0.1pA 20pA 1.5pA

R0 1k 6.7k 10k 45k 1.1M 570k 20k 58k 80 930

NF@R0 1.8dB 0.3dB 0.68dB 0.35dB 0.9dB 0.3dB 7dB 1dB

Integrated BJT cascade amplifier

Here Q1 acts as a CE-stage and Q2 as a CB-stage. Q3 is load. The total voltage gain is:

The equivalent input noise is:

Here is Kt1=re2/re1. Since the collector currents are equal is Kt1=1. ZB2 is the impedance to VBB2 (should be low). Since Re2 also is small the contribution from In2 should also be ignorable.

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The noise voltage from Q3 is:

The gain in Q3 is:

With these simplifications and assuming all transistors are equal the expression for the equivalent input noise is reduced to:

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Differential amplifiers – two sourcesThe two input signals V1 and V2can be defined relative to a common value (common-mode) VC, and a difference value VD.

and

We will then have:

and

The figure shows the noise schematic.

The equivalent input noise is:

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Differential connection – one sourceWe assume that the positive and negative input has the same noise characteristics and adds together the En and In-values for the amplifier.

When we add together with the noise from the source resistance, we obtain the equivalent input noise:

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Noise model for the differential amplifierExample of differential stage:

a)

Voltage gain of differential signal:

Here is gm=1/re for each of the transistors.

Assuming identical transistors and RC1=RC2=RC, RE1=RE2=RE andRS1=RS2=RS.

For the typical cases where RE=0 and RS ≪ r we can simplify Kdm to:

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b)Gain for the common voltage signal:

When REE is large we get:

c)Differential voltage gain between outputs with common input signal:

Ideally if the inputs were completely symmetrical Kdc should be 0. When this is not the case one can reduce Kdc say by increasing REE.

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Eni:

Here is EVEE and EVCC noise on the voltage supplies.

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Integrated BJT differential amplifierIt can be relatively large variation in process parameters for integrated circuits from production to production. However between the elements on the same circuit the variation can be made very small. This is exploited by using design strategies based more on the symmetry between the elements than on their actual values.

In integrated circuits the common-mode noise rejection is improved. On the other hand, integrated circuits require compromises that may give more noise than when optimizing a process for a single isolated component. Examples of these compromises are:

• long diffusion insulations,

• active loads, and

• power sources.

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The figure shows the integrated version of the differential amplifier we studied previously.

Equivalent input noise:

Since common-mode rejection is high and all active circuits have approximately the same geometry and noise mechanisms, Eni will be reduced to:

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Parallel amplifier stagesWhat when several amplifiers are placed in parallel? Schematically, we can draw noise sources as in the figure.

We have: and

A new optimal source resistance can be defined as:

Gain is given by:

A significant contribution to the En -noise in a BJT is the base resistance rx. The base resistance can be reduced by placing the base contacts all the way around the emitter and the closest possible on the emitter. In FETs it is determined by the channel resistances, and by gm. Low resistance and high gm can be achieved by having a large W/L ratio. By parallelising both the C’ and the Miller effect is increased.

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