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IMPACT/SPIE Review 3/10/08

IMPACT students have been asked to select and discuss interesting papers seen at the last SPIE conference.

Litho Technology: Simulation, Double Patterning, Inverse Lithography– Lynn Wang– Marshal Miller– Eric Chin– Juliet Rubinstein– Chris Clifford

Design for Manufacturing: Layout context, non-rectangular transistors, MfD– Ning Ma– QianYing Tang

Variability: LER, Global vs. local variability, systematic variability– Kedar Patel– Kun Qian

Model calibration: OPC/Litho model calibration through data mining– Yu Ben– Dekong Zeng

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Litho Technology

• Lynn Wang

• Marshal Miller

• Eric Chin

• Juliet Rubinstein

• Chris Clifford

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Validation and Application of a Mask Model for Inverse LithographyThue H. Dam, Xin Zhou, Dongzue Chen, Anthony Adamov, Danping Peng, and Bob Gleason, Luminescent

Technologies

• As photomask critical dimensions shrink significantly below the exposure wavelength and the angle of off-axis illumination increases, the use of Kirchhoff thin mask approximation cannot capture diffraction and polarization effects that occur at a topographical mask surface.

• Two approaches: (1) spatial domain approach for source-mask-joint optimization [Boundary Layer Model] (2) frequency domain approach for full-chip simulation with fixed optics [vector-formulated Hopkins Equation]

ILT Solution via Panoramic Horizontal CutlineILT Solutions: Kirchhoff vs. FDA

• Promising tool with promising results

Reviewer: Lynn Wang

4

Novel Lithography Rule Check for Full-Chip Side Lobe DetectionT.S. Wu, Elvis Yang, T.H. Yang, K.C. Chen and Chih-Yuan Lu

Macronix International Co. Ltd, No. 16, Li-Hsin Rd., Science Park, Hsinchu 300, Taiwan

• Attenuated PSM has been widely adopted in contact lithography to enhance resolution and process latitude. The main drawback associated with this method is side lobe printing, which yield unwanted resist erosion of area among patterned holes.

• An efficient model-based, side-lobe detection approach was demonstrated in this study, with the use of assistant ring, polygon-based simulation instead of grid-based simulation.

• Demonstrates promising side-lobe suppression results; whether this method is efficient for full-chip simulations is unclear

Conventional Flow

Lobe Detection Implementation

Side Lobe Detection and Suppression

Reviewer: Lynn Wang

5

Massively parallel FDTD simulations to address mask electromagnetic effects in hyper-NA lithography

Jaione Tirapu-Azpiroz, Geoffrey Burr, Alan Rosenbluth, Michael Hibbs, IBM SPIE-08: Optical Microlithography, 6924-33

• For smaller nodes, electromagnetic effects have a larger impact which makes optimization more important

• For EMF effects Leverage High Performance Computing (HPC) for FDTD analysis

• Demonstrated scalability of FDTD using blue gene up to 2048 processors (don’t have exact numbers)– Scaled well for low numbers of processors (ex: 1 to 32 or 64), but in going from

1024 to 2048 CPUs, runtime is not doubled

• Parallelization limited by memory requirements per CPU and fixedamount of serial processes such as communicating boundary conditions become more significant

• Other techniques, such as material averaging can also be used to speed up simulations

• Both parallelization and material manipulation offer speedups with FDTD simulation, but this type of simulation is still slow for large domains

Reviewer: Marshal Miller

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Hybrid Hopkins-Abbe method for modeling oblique angle mask effects in OPCKostantinos Adam and Michael Lam SPIE-08: Optical Microlithography, 6924-49

• For 45nm and below, Kirchhoff mask models are not sufficient

• Rigorous solutions are accurate, but still too slow to incorporate into OPC

• At hyper-NA (>1.0) larger incident angles are seen at the mask

• Scattering coefficients are not constant and higher angle

• Hybrid Hopkins-Abbe (HHA)– Leverages speed of Hopkins with added accuracy from Abbe

– Decompose source into multiple source elements, using Hopkins and a separate mask model with each

• Useful for increasing accuracy and buying time since rigorous simulation is not feasible for large areas

Reviewer: Marshal Miller

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A Comprehensive Comparison between Double Patterning and Double Patterning with Spacer on Sub-50nm Product Implementation

C. F. Tseng*, C. C. Yang, Elvis Yang, T. H. Yang, K. C. Chen and C. Y. LuMacronix International Co. Ltd, No. 16, Li-Hsin Rd.,

Science Park, Hsinchu 300, TaiwanYour Photo

Reviewer: Eric Chin

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Double Patterning (DP)

Reviewer: Eric Chin

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Double Patterning with Spacer (DPS)

Reviewer: Eric Chin

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Double Patterning CD Distribution

P1 & P2 Develop CD

P1 & P2 Final CD

Reviewer: Eric Chin

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Double Patterning CD Distribution

Reviewer: Eric Chin

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Overlay Shift DPS

27nm Shift

Middle of ArrayEdge of Array

Reviewer: Eric Chin

Split and Design Guidelines for Double PatterningVincent Wiaux (Imec),SPIE Optical Microlithography [6924-08] Feb ‘08

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• Guidelines for split and for DP-compliant design to ensure robust stitching are discussed.

• Representative test patterns were designed to test the stitching robustness using a metal process.

Splitting on parallel Stitching of parallel trenches Trench-end shape is trenches increases

• If stitching is needed, then the pitch needs to be relaxed to allow a robust stitching though process variations.

more critical than overlay the pitch

Reviewer: Juliet Rubinstein

Development of Layout Split Algorithms and Printability Evaluation for Double Patterning Technology

Tsann-Bin Chiou (ASML TDC Asia), SPIE 2008

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• The problem of how to split a layout and how to stitch it back together is addressed

• Rule-based pre-fragmentation and model-based OPC and stitching are used. Additionally, design rules for DPT compliance show that changing the layout may be necessary or beneficial.Layout Pre-Fragmentation Model-Based Stitching

Boundary CorrectionDesign Rules for DPTCompliance

• This is a detailed overview of all of the steps involved in a DPT algorithm.Reviewer: Juliet Rubinstein

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Use of EUV lithography to produce demonstration devicesBruno M. LaFontaine (AMD), other authors from ASML, IBM, Mentor, Sony, Toshiba

• Produced a “working testchip” using EUV lithography for the metal-1 layer

• Key finding: It is possible to integrate EUV lithography into a process to create a full chip

Transistors Fabricated in Dresden

• None of the major EUV issues confronted. Wafer had many defects, throughput was low and patterns were too large to challenge resist

Metal One Layer Patterned on EUV Alpha tool at Albany Nanotech

Tested at AMD

NOT ACTUAL I-V CURVE FOR TEST CHIP

Reviewer: Chris Clifford

Major EUV Lithography Roadblocks

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• Source– EUV Source power is currently a few watts– Need ~100 watts

• Resist– Need resist capable of resolving small features– Problem for all lithography options

• Buried Defects in EUV Mask Blanks– Two possible solutions

• Smoothing– Paper from Sematech showed effective defect smoothing possible but it takes a

very long time » ~12 hours » Smoothing time dominated by substrate pits ~10 hours» Paper: Ion-beam deposition for defect-free EUVL mask blanks, P. Kearny, 6921-63

• Compensation– Defects covered by absorber don’t print– More advanced compensation possible– Challenge is knowing where defects are on blank

World’s Largest Hockey Stick, Eveleth, MN

Joke Courtesy of Benjamin G. Eynon, Jr., SEMATECH, Inc.

Reviewer: Chris Clifford

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Design for Manufacturing

• Ning Ma

• QianYing Tang

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Context analysis and validation of lithography induced systematic variations in 65-nm designs

Arjun Rajagopal (Texas Instruments Inc.), SPIE Advanced lithography

• Quantify the amount of systematic variations of CD and timing spread caused by actual design context.

• Restricted design rules for cells in certain design context reduces variations, with some area penalty.

Analysis flow Experiment I Experiment II

Layout

Contour simulation

Analysis

Experimental checks

Extract netlists

Cell Standard cell

Reviewer: Ning Ma

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A routing clear-up methodology for improvement of defect and lithography related yield

Hanno Melzner (Infineon Technologies AG, Germany), SPIE Advanced lithography

• Address both defect and lithography related yield loss in routing layers.

• Insert a clean-up step after routing to replace complicated or problematic configurations with simple shapes by construction.

Methodology Result I Result II

SFF

Creating bricks

Via clustering

Grouping, etc.

• Very relevant research topic. Algorithms described in methodology and ideas proposed in discussion could be a reference for my own research.

Reviewer: Ning Ma

Shaping Gate Channels for Improved DevicesS. Shar, P. Gupta, Blaze DFM Inc., Y. Kim, D. Sylvester, Univ. of Michigan, A. Kahng, UCSD, SPIE 08

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• Transistor-level optimization for superior device delay and leakage– Exploits the unequal on/off current across the channel due to STI

• Gate shaping reduces leakage while keeping Ion and capacitance constant.– Increase gate length at channel edges and decrease gate length at center

Passive/active gate Leakage Improvement Drive and leakage current density

• Post-layout optimization may cause timing issues.

shape perturbation vs. Width

Reviewer: QianYing Tang

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Manufacturing for design: A novel interconnect optimization method

L. Deng, M. Wong, UIUC, K. Chao Intel Corp. SPIE 08

• Interconnect delay has become increasingly important in circuit delay

• Exponential shaped interconnect for reduced delay– Approx. by staircase shape for manufacturability

– Shape optimized by balancing out complexity and performance improvementExponential shape Staircase Approximation

dh

• Serious layout issues for jogs/dense lines. Parasitic cap extraction difficulties. Timing issues for post-layout delay optimization.

Reviewer: QianYing Tang

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Variability

• Kedar Patel

• Kun Qian

Fractal dimension of LWR and its effects on transistor performanceV. Constantoudis (Inst. of Microelectronics, Greece)

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• Thesis– ITRS stipulates LWR for 2um line but typical gate widths (W) are 50-350nm range

and in this regime fractal dimension D (α = 2-D) matters

• Synopsis– Yield is defined as 10% tolerance in Vt

– Yield increases with the fractal dimension

– However, yield decreased for W>200nm and ξ>30nm.

ITRS

Typical Gate widths

2

( )x

A x e

α

ξρ⎛ ⎞

−⎜ ⎟⎝ ⎠=

Auto-correlation function fitted to form,

ξ = correlation lengthα = roughness exponent

Reviewer: Kedar Patel

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Global and local factors of on-chip variation of gate lengthMorimi Osawa (Fujitsu Ltd.), SPIE 2008

• Modeling of global and local variations with EL, DOF, and MEEF conditions

• Variance:

( ) ( )

( )βα

σσσ

σσσσσ

+=

+=+=

++⎟⎠⎞

⎜⎝⎛ ∆

+⎟⎠⎞

⎜⎝⎛ ∆

=

ELV

MEEFVV

MEEFfDOFEL

R

roughnessMEEFRMlocal

MEEFfocusfocusdoseglobal

2222

2220

42

2

2

4342

• Litho layout effects only. Global context (fig 1.a) is not analyzed.

Grating DUT & SRAF Litho sensitivity analysis Descriptive TitleModified: LWR dependent on EL

Global

Local

Reviewer: Kun Qian

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Analysis of Systematic Variation and Impact on Circuit PerformanceShayak Banerjee, Michael Orshansky (UT Austin, IBM), SPIE 2008

• Develop a systematic process variation aware design flow– Use physical models for lithography, contact resistance, stress and etch (each modeled as a function

of process parameter, e.g. dose, focus)

• Simulates a lookup table for each process parameter; predicts yield by assuming Gaussian process parameter variation– Delay histogram for NAND2 in 45nm SOI is non-gaussian.

• Did not deal with random variations. Process variation is not necessarily Gaussian.

Stress dependency on process Delay & process

Litho & RVIA impact

Reviewer: Kun Qian

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Model Calibration

• Yu Ben

• Dekong Zeng

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Customized illumination shapes for 193 nm immersion lithographyM Ling, G Chua,, C Tay, C. Quan, Q Lin (NU Singapore, Chartered Semiconductor)

• Forbidden pitch

• Modify the illumination shape to counter destructive interference, alleviating the forbidden pitch problem

Modified Annular illuminationForbidden pitch Modified Dipole illumniation

• CD variance is reduced from 15.5% to 3%

• CD variation from pitch change

• CD variance is reduced 8.3% to 3.5%

• One example of illumination optimization

Reviewer: Yu Ben

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Intelligent process window OPC for 32-nm node full chip deviceW. Choi, N. Chung, B. Kim, H. Shin, N. Lee (SAMSUNG)

• Introduce multiple resist model to OPC

• Evaluate mask error enhancement factor before OPC

• Successfully applied to full-chip metal line layer of 32-nm nodePWOPC PWOPC with multiple resist modelStandard OPC

Reviewer: Yu Ben

Optical proximity correction with PCRA.X.Gu (UC Berkeley, Professor Zakor’s group), SPIE2008 Advanced lithography 6924-133

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• In model based OPC, masks are systematically modified for non-ideal optical and process effects of litho system. Polygons in the layout are fragmented, and simulations are performed by iteratively moving fragments inward and outward to achieve desired patterns. This is computationally expensive.

• Statistical machine learning techniques are used to predict fragment movements in OPC, thus number of iterations for convergence can be reduced.

Ordinary least squares unstable. Neural Network proposed for fragment movement mapping, and tested on single polygon.Principal component regression is applied for polygon movement prediction and compared with OLS results on different portions of two 90nms layout.Main flow: apply Gaussian LPF with cut-off frequency of 2NA/λ, use incremental concentric square sampling to create feature vectors, select training data that covers all possible fragment movements in a portion of layout, apply PCR regression, evaluate root mean square error.

Reviewer: Dekong Zeng

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Empirical data validation for OPC model buildingA.Kazarian (Synopsys), SPIE2008 Advanced lithography 6922-25

• OPC solutions require stable predictive models. Model built with two main component blocks: knowledge of optical parameters, and empirical CD data on specific test features. Quality of model highly depend on data integrity. CD data is noisy and must be validated.

• Generate clean and smooth dataset to fit OPC model.– Smooth data by curve fitting, limitations of this method is also studied.

– First principle, simulation based characteristic coherence curve to fit measured data.

– Outliers from 1-D & 2-D symmetric test pattern (traditional model calibration) are easy to handle (single CD measurement).

• Comment: This talk did not provide a clear answers, but provided general framework and issues. What about SEM-contour based data (more space coverage for image parameters, each SEM image contains hundreds sets of data), how to choose SEM images that are process sensitive?

Reviewer: Dekong Zeng

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OPC model calibration consideration for data varianceM.S.Bahas (Mentor Graphics Group),SPIE2008 Advanced lithography 6924-142

• OPC models have been improved by modeling more of error sources in the litho system. However, statistical variance of the calibration dataset has been ignored. Empirical datasets are not perfect due to unknown physics, long convergence and stability of fitting model becomes an issue.

• Improve model fitness for primary out-of-spec features in the calibration dataset by data weighting and manipulation.

Data manipulation executed in image-parameters (Imin, Imax,slope and curvature) to control model convergence.

The perturbations are in fractions of nanometers, consistent with the residual variance of statistical valid dataset.

• Comment: Iterations of manipulation can be large. Sensitivity analysis maybe can help to find a test pattern that is highly sensitive to a model parameter. A full OPC test pattern set is not needed, data amount can be reduced prior to manipulation or weighting.

Reviewer: Dekong Zeng

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Validating an improved method for litho model calibrationChris.A.Mack (Lithoguru.com),SPIE2008 Advanced lithography 6925-66

• OPC models that predict process window behavior: line width data vs focus and exposure from different features. The prediction needs a robust method.

• Common standard least-squares regression suffers several issues.– Outlier (measured line width data) rejection is needed and uncertainty in input

variables( focus and exposures) are ignored.

– Total least-squares regression is proposed as a robust approach to outlier and uncertainty in input variable.

– Uncertainty in nominally fixed parameters (line width of features on the mask)• Two standard approaches are not satisfying. ( leaving them fixed or adjusted for best fit).

• Optimum solution is to use Bayesian fitting with a priori estimate of mask feature widths and their uncertainties.

• Comment: This paper addresses outlier and uncertain issues for input and response variable of a OPC model. Robust fitting method is demonstrated for improved capability. Too much focus on mathematical description of fit, lack of description on fitting dataset.

Reviewer: Dekong Zeng