integrated cmp metrology and modeling with respect to...

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Integrated CMP Metrology and Modeling With Respect to Circuit Performance

Runzi ChangDissertation Talk

4/29/2004

Department of Electrical Engineering and Computer ScienceUniversity of California, Berkeley

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Outline

Motivation• Cu CMP process characterization and metrology• Model-based CMP process optimization• Impact of dishing on circuit performance• Conclusion

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Motivation – for IC designers

Interconnect delay is expected to strongly impact IC performance with aggressive scaling efforts– Copper has been

adopted for high performance

– CMP is enabling the Cu process

Source: The International Technology RoadMap for Semiconductors: 2003

250 180 130 90 65 45 32Process technology node (nm)

100

10

1

0.1

Gate delay

M1 delay

Global Delay

Global Delay

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State-of-the-art Copper Interconnect

FEOL

Back-End

BEOL

EPI, Implant, RTP, Etch, CMP,Litho, CVD, Furnace – 1 Pass

CVD, Etch, PVD, ECP, Cu CMP, Litho7-8 passes at 65nm

PVD, Etch – 1 Pass

Cu BEOL Interconnect

ContactTransistor

Metal 9

M7

M8

Al Bondpad

M5M6

M4

M2M3

M1

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Copper Damascene Process

ErosionDishing

ILD

Cap/Low-kDeposition

Damascene Etch

Barrier/Seed

ECP

Cu

Cu CMP

Post-polish topography control (dishing, erosion) is key technical need

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Previous Related Work

• Inter-layer dielectric (ILD) CMP modeling– Preston (1927) – the theory and design of plate glass

polishing machine– Cook (1990) – chemical processes in glass polishing– Boning (1997) – analytic model for ILD thickness variation

in CMP processes– Luo & Dornfeld (2001) – material removal mechanism in

CMP: theory and modeling• CMP metrology

– Applied Materials: ISRM, Interferometry– KLA-Tencor: Scanning Electron Microscopy

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Oxide CMP Metrology - Previous Project

SEM

- 3 - 2 5 - 2 - 1 5 - 1 - 0 5 0 0 5 1 1 5 20

2 0 0 0

4 0 0 0

6 0 0 0

2 1 5 1 0 5 0 0 5 1 1 5 2 2 5 3- 5 0 0 0

0

5 0 0 0

3 2 1 0 1 2 30.9

1

1.1x 10

AFM ScatterometryLibrary-based scatterometry extracted profiles match AFM profiles and SEM pictures with 5nm precision

Reference:X. Niu, Jakatdar, Bao and Spanos, "Specular Spectroscopic Scatterometry," IEEE TED, May 2001.R. Chang and C. Spanos, "Full Profile Inter-Layer Dielectric CMP Analysis, IEEE ISSM, October 2001.

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Previous Related Work (Cont’d)• Copper CMP process modeling

– Steigerwald (1997) – Chemical mechanical planarization of microelectronic materials

– Boning (2001) – Framework for modeling of pattern dependencies in Cu CMP processes

– Gutmann (2002) – Book on Cu damascene process• Interconnect variation analysis

– Lin & Spanos (1998) – Circuit Sensitivity to interconnect variation

– Nassif (2000) – Impact of interconnect variations on the clock skew of a gigahertz microprocessor

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Challenges• Lack analytical CMP models for copper damascene

process– To estimate systematic metal and ILD loss – Copper dishing

• Previous work used polynomial fitting to relate the metal line width to dishing

• Call for accurate, fast and non-destructive CMP metrology to develop, verify / refine the models

• Deep sub-micron scaling and wafer/die size increasing– Need tighter process control at 65nm technology node– Require precise electrical model of BEOL process

variations on circuit performance

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Outline

MotivationCu CMP process characterization and metrology

• Model-based CMP process optimization• Impact of dishing on circuit performance• Conclusion

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Test Pattern Design• Designed E-test structures to measure and study dishing,

where copper line width ranges from 0.4 to 5 microns• Total Line length for each four point structure is about 4mm

– Resistances are on the order of 100Ω depending on line width

Cross-sectionELM Van Der Pauw

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Mask Design (I)

50%35%30%

65%45%40%

70%60%55%

21mm

E-test cellThe difference in the resistance change percentage is a result of both erosion and dishing effects

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Mask Design (II)

• Mask has 7x7 array of E-test cells

• The effective pattern density for each cell is constant

• Resistance change is due to dishing metal loss

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Process Flow• Lithography and

etching done at Berkeley microlab

• PVD and Cu CMP done at RPI Microlab

• About 30 wafers were polished with the planned DOE

substrate nitride

oxide

copper

barrier

dry etch

copper

CMP(2 steps)

CALmicrolab

RPImicrolab

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Experimental Results

1.6µm line

Post-CMP E-test structure

What are the causes of dishing?

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Pad-Wafer Contact Mechanics• Pad has a rough surface

with random asperities• The applied pressure is

shared by pad asperities and the slurry film

• For normal platen speed, the hydrodynamic pressure of the fluid film is small, solid contact analysis is sufficient

wafer

vSlurry

Pad

Pressure

Slurry

Metal

Source:Motorola

200µm200µm

100µm

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Dishing Radius Concept

Rdish

ILD

dh (Dishing)

Cu ILD

w

Dishing Radius

Rdish: effective radius of pad asperity;W: metal wire widthdh: metal non-planarity due to dishing;

• Dishing “radius” is the ‘effective’ radius of pad asperities• Function of asperity size, chemistry, particle size, pressure etc.

Reference: R. Chang, A.Jindal, R. Gutmann andC. Spanos, “Copper CMPProcess Modeling usingthe Dishing Radius Concept,” 8th InternationalCMP Conference, 2003

dishRwdh

4

2=

If w<<Rdish

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Concept Validation

w=0.4

w=2µm line

µm line

w=1.2µm line

An array of cross-sectional SEM pictures qualitatively validated the dishing radius concept

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Concept Validation (Cont’d)

Surface profile of the post-CMP Copper structure (3µm metal line and 1 micron oxide spacing).

-960

-940

-920

-900

-880

-860

-840

-8205 7 9 11 13 15 17

location X (m icron)

heig

ht (A

)

Cu Cu Cu

3µm 1µm 3µm 1µm 3µm 1µm

Scan

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E-test Results

Wide lines R increase suffered most from dishing while narrow ones lost metal in corner rounding

R_expected

R_measured

R_difference / R_expected

0

2

4

6

8

10

0 1 2 3 4 5 6metal linewidth (micron)met

al lo

ss p

erce

ntag

e ( %

)

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Profile Extraction using E-test Data

r

tdt

dishing

r

NNNNN

dre

WaWrdtWtWy

WaWrdtWtWy

WaWrdtWtWy

henceyyyyy

haveweLYyDefineconstareLandBothLtW

RY

tWLR

•−−−−=

•−−−−=

•−−−−=

−−−=••=

••

==••

=

)()4

1(2

......

)()4

1(2

)()4

1(2

.

1

2

222

222

112

111

0

π

π

π

ρρρ

ρ

Assumptions:a. Rounding is linewidth

independentb. Erosion is constant for a

certain E-test structure (enforced by test pattern design)

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Sample Extracted Results

Line width (micron)

Conductance(S)

(normalized

by L)

Broken lines

Shorted lines

( )

⎟⎟⎠

⎞⎜⎜⎝

⎛−

⎟⎟⎠

⎞⎜⎜⎝

⎛−+

−−−

=⋅

−

dishdish

dish

dish

RwR

RwwR

rdttw

Rlength

2sin

21

2

)4

1(2

12

2

2π

ρ

Erosion=0.1µm, Corner rounding=70nm, Dishing Radius=40µm

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Outline

MotivationCu CMP process characterization and metrologyModel-based CMP process optimization

• Impact of dishing on circuit performance• Conclusion

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Identify Key CMP Performance Metrics

• Material Removal Rate (MRR)• Selectivity• Inter-layer dielectric erosion• Metal dishing

• Pressure• Speed• Slurry particle size• Pad type

And the key input parameters:

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Linear Models

25-1-1134

21

Run No.

1

-11

Over-polish Time

15-30sec

W=5µm Dishing

(nm)

Speed60-

100rpm

Pressure(3-6psi)

2011

221-130-1-1

OTVPnoisetEffecttimevEffectspeedPEffectpressureDishDish

*75.0*25.3*75.125.24_*_*_*0

+−−=++++=

∑ −=i

iii MeasuredetTwCost 2)arg(

Similarly build linear modelsfor each performance metric

With known weights, process can be optimized by minimizing the cost function

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Framework of CMP performance Optimization

Identify CMP performance metrics

Specificationrequirements

Design of Experiments

Identify key contributingInput parameters

Model development

Identify Cost function

Set weights formetrics

ProcessOptimization(optimizer)

Converging?

No

Yes

OutputIdentify CMP

performance metrics

Specificationrequirements

Design of Experiments

Identify key contributingInput parameters

Model development

Identify Cost function

Set weights formetrics

ProcessOptimization(optimizer)

Converging?

No

Yes

Output

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Taguchi’s Philosophy

• Use signal to noise ratio to measure and maximize performance

• Run a partial factorial set of experiments using orthogonal arrays– for every two columns

all possible factor combinations occur equal times.

S/N = -10 log [MSD]MSD refers to Mean SquareDeviation of objective function

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Case Study Using Orthogonal Array

-26.053.0-24.62339

-26.851.2-28.91238

-23.555.1-21.63137

-30.148.9-32.01326

-25.153.7-26.03225

-19.155.7-29.82124

-28.348.1-18.13313

-28.950.6-20.02212

-22.952.0-30.91111

50% ILD erosionn”(dB)

Cu MRRn’(dB)

w=5µm Dishingn(dB)

C(slurry particle size 80-160nm)

BS(80-

100rpm)

A

P(2-6psi)

ObservationsColumn (variables)

Run No.

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Effects of Input Parameters

-35.0

-15.0

A1 A2 A3 B1 B2 B3 C1 C2 C3

n =

-20

log

(dis

hing

)

mean-25.8

n = -20 log (Dishing)

45.0

55.0

n' =

20

log

(MR

R)

Pressure

speed

size

mean52.1

n' = 20 log (MRR)

A1 A2 A3 B1 B2 B3 C1 C2 C3

-35.0

-15.0

n" =

-20

log

(ero

sion

)

mean-25.6

n" = -20 log (Erosion)

A1 A2 A3 B1 B2 B3 C1 C2 C3

-35.0

-15.0

A1 A2 A3 B1 B2 B3 C1 C2 C3

n =

-20

log

(dis

hing

)

mean-25.8

n = -20 log (Dishing)

45.0

55.0

n' =

20

log

(MR

R)

Pressure

speed

size

mean52.1

n' = 20 log (MRR)

A1 A2 A3 B1 B2 B3 C1 C2 C3

-35.0

-15.0

n" =

-20

log

(ero

sion

)

mean-25.6

n" = -20 log (Erosion)

A1 A2 A3 B1 B2 B3 C1 C2 C3

provides an intuitive,comprehensive viewof the process

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Optimization Results

The optimization process improves MRR by 10%, and reducesthe erosion and dishing by >15%

16.4(nm)

459nm/min

17.3(nm)

18.8(nm)

426nm/min

20.8(nm)

Real Output

-24.353.3-24.7-25.552.6-26.4Total Mean

-25.652.3-21.9C3-24.753.1-24.8C2C

-21.854.3-27.4B1-27.051.9-25.0B2B

-25.553.1-25.0A3-24.852.8-29.3A2A

ILDErosionMRRDishingsettingILD

ErosionMRRDishingsetting

Optimum ConditionStarting Condition

Inputs

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Outline

MotivationCu CMP process characterization and metrologyModel-based CMP process optimizationImpact of dishing on circuit performance

• Conclusion

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Model-Based Interconnect Performance Simulation• RaphaelTM simulations

were carried out based on experimental results

• RC delay was used as the metric to study the impact of dishing on interconnect performance

GND

h

st

w

w: metal line width;t: line thickness (default=0.5µm);s: line spacing (default=0.5µm);h: dielectric thickness(SiO2,

default=0.5µm).

2D Cross-sectional view and parameterdefinitions of global interconnectstructure (line above one ground plane)

Reference: R. Chang, Y. Cao, and C. Spanos, “Modeling Metal Dishing for Interconnect Optimization,” IEDM 2003

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R, C vs. Linewidth with Dishing

Ctotal=Cground+2*Ccoupling

No DishingRdish =30µmRdish =40µmRdish =60µm

0

5

10

15

20

25

2 4 6 8 10 12Line Width ( µm)

R (Ω

/mm

)

0.0

1.2

1.6

2.0C

total (pF/mm

)No DishingRdish =30µmRdish =40µmRdish =60µm

0

5

0 2 4 6 8 10 12Line Width ( µm)

0.4

0.8

1.2

1.6

2.0

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RC Delay vs. Linewidth with Dishing

The optimal linewidth to achieve the minimumRC delay is around 4µm

0 2 4 6 8 10Line Width (µm)

RC

Del

ay (

fs/m

m2 )

No DishingRdish =30µmRdish=60µm

4

8

12

16

20

Optimal Width

0 2 4 6 8 10Line Width (µm)

RC

Del

ay (

ps/m

m2 )

No DishingRdish =30µmRdish =60µm

4

8

12

16

20

Optimal range

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RC Delay Sensitivity

• With dishing, RC delay becomes less sensitive to linewidth variation around the optimum width

0

1

2

3

4

5

6

7

0 1 2 3 4 5 6 7Linewidth (micron)

|∆R

C| w

/ 20%

W c

hang

e (%

)|∆RC| w/ Rdish= 40µm|∆RC| without dishing

0

1

2

3

4

5

6

7

0 1 2 3 4 5 6 7Linewidth (micron)

|∆R

C| w

/ 20%

W c

hang

e (%

)|∆RC| w/ Rdish= 40µm|∆RC| without dishing

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Efficiency of Process Improvement

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

0 25 50 75 100Rdish(micron)

RC

Diff

eren

ce (%

) w=4µm; t=0.5µmw=4µm; t=1µmOptimizing W is

critical in thisregion

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Line-Splitting in Design

• Line-splitting suppresses dishing, but sacrifices area and increases the fringing capacitance.

wtotal ww=wtotal/N, N is the number of lines; s=smin =0.5µm

swtotal ww=wtotal/N, N is the number of lines; s=smin =0.5µm

s

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RC Delay Gain and Area Penalty

Gain in RC delay drops fast when splitting lines

0

5

10

15

20

25

0 1 2 3 4 5 6 7 8 9 10 11N (Number of split lines)

Extr

a D

elay

due

to D

ishi

ng (%

)

0

10

20

30

40

50Extra A

reaCost(%

)

Optimal Splitting N=2- 4

0

5

10

15

20

25


Extr

a D

elay

due

to D

ishi

ng (%

)

0

10

20

30

40

50Extra A

reaCost(%

)

Optimal Splitting N=2- 4

Wtotal=10µm; Rdish=40µm

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Optimization of Interconnect RC Delay

2

4

6

8

10

12


RC

Del

ay ( f

s/m

m2 )

No DishingRdish=40µm

t=0.5µm

t=1.0µm

Optimal Splitting N=2-4

wtotal=10µm

2

4

6

8

10

12


RC

Del

ay (

ps/m

m2 )

No DishingRdish=40µm

t=0.5µm

t=1.0µm

Optimal Splitting N=2-4

wtotal=10µm

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Outline

MotivationCu CMP process characterization and metrologyModel-based CMP process optimizationImpact of dishing on circuit performanceConclusion

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Conclusions• Designed test patterns and implemented experiments to

develop analytical dishing model, which well captured the systematic component of variations in Cu CMP

• Dishing radius concept was instrumental in process metrology

• Established multi-objective optimization framework in Cu CMP process

• Studied the interconnect performance and tradeoffs with dishing– Process improvement and/or layout modification is required when

Rdish<50µm– Optimum line-splitting number is found to be 2-4 at design stage

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Acknowledgements• Professor Costas Spanos• Prof. Cheung, Dornfeld – Thesis Committee• Doyle, Neureuther, Poolla, Talbot - SFR/FLCC• Dill, Gutmann - Mentors• Berkeley, RPI, UCSB microlabs• BCAM• Family, collaborators and more

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