Polarization Encoded Optical Shadow Casting Logic Units:Design of Trinary Half Subtractor Using

Various Input Coding Scheme.

Abdullah Al Hadi Dept. of Energy Engineering and Management

Instituto Superior Tecnico, IST Lisbon, Portugal

Abdullah.al.hadi.bd@gmail.com abdullah.hadi@ist.utl.pt

Jamal Uddin Ahmed Dept. of Electrical and Electronic Engineering

Ahsanullah University of Science and Technology, AUST Dhaka-1215, Bangladesh

jamaluddinahmedjua@gmail.com

Abstract— In this paper we evolve several input pixel pattern scheme for trinary half Subtractor design. This is a follow-up paper of half adder design of A. A. Hadi et. al. 2012 [1], where various coding scheme were designed only for logic unit design of trinary half adder. Different input coding schemes for half subtractor are calculated in this paper by changing the minterm grouping conditions. New pixel patterns are designed based on the design of R. A. Rizvi et. el. 1991[6], which are more efficient, cost effective and convenient for integrating larger complex design. The POSC [2] modified algorithm is used to design and implement trinary half Subtractor. A set of POSC equation are obtained from the truth table of the desired arithmetic unit. Each design has various merits on other designs.

Keywords- Polarization Encoded Optical Shadow Casting (POSC), Trinary logic design, Optical Computing, Half Subtractor design.

I. INTRODUCTION Faster, smarter and loss less system design is the biggest

challenge in this century for advanced technology . The speed of computers was achieved by miniaturizing electronic components to a very small micron-size scale, but they are limited not only by the speed of electrons in matter (Einstein’s principle that signals cannot propagate faster than the speed of light) but also by the increasing density of interconnections necessary to link the electronic gates on microchips. The optical computer [3] comes as a solution of miniaturization problem. In an optical computer, electrons are replaced by photons, the subatomic bits of electromagnetic radiation that causes light. If we can replace electronic system by photonic system then we should have a computing system thousands of times faster than the electronic system. Moreover, there is no such thing as a short circuit with light, so beams could cross with no problem after being redirected by pinpoint-size mirrors in a switchboard. In a pursuit to probe into cutting-edge research areas, optical technology[4] is one of the most promising, and may eventually lead to new computing applications as a consequence of faster processor speeds, as well as better connectivity and higher bandwidth.

With the advent of mass-produced binary components for computers, trinary components have diminished to a small footnote in the history of computing. However, elegance and efficiency of trinary logic is predicted by Donald Knuth. Possible ways of solving this issue is by the combination of an optical computer with the trinary[5],[6],[7] logic system. The simple way to explain this phenomenon is to compare it with the binary system. Binary system, normally used in electronic computing, has two values 1 or ON and 0 or OFF. A trinary computer could use three values: 0 or OFF, 1 or Semi ON and 2 or Full ON. Although ternary most often refers to a system in which the three digits 0, 1, and 2 are all nonnegative integers are difficult to configure by electronic system. So, the implementation of trinary system should be much easier in optical method. In electronic system there is no such value Semi-ON or Full-ON.

Yet, in optical method light could be either horizontally polarized or vertically polarized to distinguish between Semi-ON and Full-ON. Therefore, the three nonnegative values are represented by 0 or dark, 1 or horizontally polarized, 2 or vertically polarized light.

First Trinary adder and subtractor were designed using POSC scheme by A. A. S. Awwal et. el., 1987[5]. Later on, modification on this design was done by R. A. Rizvi et. el., 1991[6]. In this paper we introduced further improvement and modification in the design with different types of input pixel patterns for trinary half subtractor. Previously we showed the various input coding scheme for trinary half adder [1] and now in this paper we discovered surprizingly much better solution for half subtractor design than R. A. Rizvi et. el., 1991[6]. Here all together four different designs were introduced out of which design 1 was introduced by R. A. Rizvi. Three new various design alternatives will help in integrating larger complex design.

In the next section the shadow-casting setup and consequent design algorithm are elaborated. Then various design examples of trinary half adder are described.

594978-1-4673-6217-7/13/$31.00 c©2013 IEEE

II. POSC METHOD AND ALGORITHM The optical shadow casting system is considered to be

promising for optical digital computing because of the relative ease with which it can be implemented to utilize fully parallel communication and noninterfering interconnection capability of optics. The scope of optical shadow casting was broadened by polarization-encoded optical shadow casting. By Including polarized pixel codes as additional design variables for encoding the input, source, and the decoding mask the capability of optical shadow-casting system has been improved drastically. This improved technique, is called polarization-encoded optical shadow casting (POSC) scheme. In the POSC scheme, the geometry of the system is identical to that of the OSC method. Here, the logical inputs as well as the LED sources can be coded by the sense of polarization. To display the basic features of the POSC scheme, we consider a simple POSC system shown in Fig.1.

LEDs OUTPUT

Figure 1: A Polarization-encoded Optical Shadow-Casting (POSC) system.

A. POSC Algorithm: A POSC design scheme involves determining the encoding

patterns of the input, the source LED pattern and the decoding mask which will produce the desired output of any arithmetic and/or logic unit. An algorithm for the design of POSC logic unit utilizing truth table partitioning is described as follows:

Step 1: The truth table of the to-be-designed logic unit is determined.

Step 2: The truth table is then partitioned into two sections, taking at least two input columns in primary section. The remaining inputs form the secondary section. For multiple output functions, each output is treated separately.

Step 3: The outputs assigned the polarization codes: T/ V for 2 in trinary system, H for trinary 1 and F for trinary 0. The non-zero outputs are thus assigned either V code for 2 or H code for 1. Trinary logical values 1 and 2 are decoded by horizontally polarized H and vertically polarized V masks respectively of a same micro pixel occupying half part of the pixel each. Zero outputs are not usually considered in the

treatment, as they would always occur by default whenever a 1 or 2 is not generated.

Step 4: The overlap of the primary inputs in each row of the truth table is assigned the same code as that of the corresponding output.

Step 5: The overlap of the secondary inputs is assigned a POSC code so that its overlap with the code of the overlap of the primary inputs produce the code for the desired output the overlap of the secondary inputs is thus assigned either T, F, or “don’t care” code. A don’t care means that the variable could have any one of the codes T, V, H, or F for any of its trinary values.

Step 6: The input coding pattern is determined from the solution of the corresponding POSC overlap equations.

Step 7: If more than one output exists, the next output is generated from the existing codes of the primary inputs. If this is not possible, step 4, 5 and 6 are repeated to provide new assignments for the overlap of either primary and/or secondary inputs. This step may increase the size of the input pixel.

Step 8: The POSC overlap equations involving (i) the primary input variables and the code of their overlap and (ii) the secondary input variables and the code of their overlap are solved to provide the codes for all of the inputs.

Step 9: The source LED pattern for each output is determined.

Step 10: The output decoding mask are identified.

The basic overlap (AND) operation is governed by the following set of rules: (a) the overlap of transparent code and an input code leaves the input code unchanged, while the overlap of opaque code destroys all input code resulting in an opaque output. (b) The overlap of orthogonal codes results in opaque output. F is found to be orthogonal to all variables including it. (c) The overlap of any one of the codes of itself results in the same code. The overlap operations are represented by:

x T=x

x F=F

x x=x

V H=F

H V=F

Where indicates the overlap operation, and x may be any one of the codes T, F, V and H. It is to be noted that (a) F and T, and (b) H and V are complementary to each other. A complementary operation is represented by a bar overhead. Complementary pairs are also orthogonal since their overlap produces opaque output. However, while all complementary pairs are orthogonal, pairs are not complementary.

B. Half Subtractor: The truth table for the trinary half Subtractor is

characterized in table 1. Let us consider two trinary input

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variables A and B, each represented by a 2 X 3 spatial matrix and a source plane characterized by a 3 X 2 matrix:

The decoding mask, thus, would be represented by a 4 X 4 spatial matrix:

Output pattern is detected at micro pixels say, D22 and D33, if we are dealing with a combinational logic element having two outputs. It can be seen that the output pattern at D22 is produced from the overlap of L21, L22, L31, and L32 with input pixel subcells {11}, {12}, {21}, and {22} respectively. Likewise at D33, it is generated by the overlap of L11, L12, L21 and L22 with input pixel subcells {12}, {13}, {22}, and {23} respectively. This situation can be represented in terms of an equation called an input-output equation. For D22 and D33 respectively, we can write

Where, represents the overlap of the input pixel subcell, i.e. = Sub cells and can be assigned any values from the POSC variables T, V, H, and F. In the same way, the LEDs in the source plane are also characterized by the POSC code variables. The overlap rules and algorithm summary are already given.

Table 1: Truth Table for Trinary Half-Subtractor:

Condition number

A B D B

1 1 1 0 0 2 0 0 0 0 3 2 2 0 0 4 0 1 2 1 5 1 2 2 1 6 1 0 1 0 7 2 1 1 0 8 0 2 1 1 9 2 0 2 0

(a) (b) Figure 2: Trinary half-subtractor: (a) source plane and (b) decoding mask. The Difference and Borrow outputs are detected at micro pixels D33 and D22 respectively on the decoding mask. The projected trinary logical values 1 and 2 for the difference output are decoded by horizontally polarized (H) and vertically polarized (V) masks respectively i.e. by using a mixed polarized (HV) mask. The left half part of D33 would detect trinary logic 1 and the right half will decode trinary logic 2. As borrow output does not involve trinary logic 2, the only true logical value is 1 that can be detected by a transparent mask; i.e. any transparent, vertically polarized and horizontally polarized input pixel projected at D22 would represent the true output and otherwise false output (F). The input-output equations for DIFFERENCE (D33) and BORROW (D22) are given before. Using Eq. (1) and (2) the procedure starts by writing POSC logic equations, preferably obtaining more than one appropriately chosen true operation from a single pixel. If this causes any problem of emergence of some unwanted input condition or cross-decoding, some of the LEDs in the source plane can be polarized in such a way that cross-decoding does not occur. Different grouping condition in different pixels, we can design different input coding scheme. The designs are described below. Only one input pixel pattern was developed in 1991[2], which is shown below as design 1. We developed three more new possible designs of input pixel pattern shown in design 2, design 3 and design 4.

Design 1: Half Subtractor coding scheme Introduced by R. A. Rizvi et al., 1991.

; ;

;

596 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

Design 2: An alternate design of design 1. , Xij and respectively, represent trinary 0, 1 and 2 of

the ijth pixel subcell of input X. The POSC logic equations are written by grouping conditions 4 and 8 through pixel {12},

As both equations (3) and (4) have orthogonal logical output and L11, L22 is common in both equations, it is kept unpolarized. So, L22, L11 and are kept unpolarized since they are common in both Eq. is made vertically polarized whereas is made horizontally polarized. It yields:

Equation for grouping conditions 7 and 9 through pixel {23},

Similarly, L22 and are common in both equation so it is kept unpolarized, by solving equation (5) and (6) we get,

, = V Equation for grouping conditions 5 and 6 through pixel {22},

The presence of two LEDs in equation (7) means that it projects the overlap input pixel pattern at micropixel and the other at D33. Also in equation (8), the given LEDs project the corresponding input pixel at . We consider the borrow output is detected by and transparent mask, so the micropixel where any input projected code (T or H or V) would represent the borrow output. But to avoid cross-decoding, we require the overlapped input pixel in this equation and make . Therefore the choices of input pixels in equation (7) and (8) becomes easy and given by;

The new half subtractor design is now complete. The coding scheme thus obtained is,

By using same procedure two more possible input coding schemes are shown in design 3 and design 4. Design 3: One more alternate design of design 1.

Design 4: Yet another alternate design of design 1.

The grouping condition of input pixel for design 2, design3 and design 4 are given in figure 3,

4,8 5,6 7,9 4,6 7,9 5,6 7,9 4,8 5,8 (a) (b) (c)

Figure 3: Input pixel grouping condition: (a) design 2, (b) design 3 and (c) design 4.

Design 2, 3 and 4 were nowhere introduced before. Less number of input pixel use is the biggest advantage of design 1, design 2 and design 3 over design 1.In design 2 we found that the LED sources required are also reduced and in this case only four LEDs are used, hence we can make the calculation more faster by using only four LEDs instead of five. One might use this scheme for alternative output pixel position and make more alternate design for half subtractor. Multiple design schemes will help a designer to integrate larger complex design efficiently.

III. DISCUSSION Implementation of trinary logic in a polarization encoded optical shadow casting scheme was designed for only one input pixel pattern. In this paper we used the same method to design three more possible schemes of input pixel pattern. These new schemes are more easy and efficient than previous design. We designed various input coding scheme for half adder [1] and in this paper we evolved new schemes for half subtractor and similarly full adder and full subtractor can also be designed in the future. The calculation of making new input coding schemes is very easy and simple. These different input coding schemes can be used in different applications and can be very helpful to design more complex logic units with more grouping conditions. R. A. Rizvi et. el., 1991[6], made two groups of operational conditions through one pixel for each group and the rest of the conditions by individual pixels and finally he used four input pixel to satisfy all operational conditions. In this paper we designed more dynamically and clearly proved that more group can be made and hence less input pixel can be used which is beneficial for commercial use also. There is a disadvantage in decoding mask with this method that is the horizontally polarized code and vertically polarized codes are detected by the same micro pixel. This can be minimized by using separate decoding output pixel for DIFFERENCE outputs and have to consider different type of

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grouping condition which we did not use in this paper for different type of input coding scheme. The smallest design for half subtractor was published by A.A.S. Awwal et. el., 1987, which is not able to implement an integrated larger complex design because it may, requires alternative coding schemes for the complete functionality and faster computation as well as accurate result. Various alternate designs of input pixel array for this compact scheme is very difficult rather could be impossible. So using this new scheme such design problem is solved. A complex design may need many alternate half subtractor designs to complete the functionality and hence these new designs are the only solutions for the successful design of a large optical system. As we have seen in half adder design output pattern scheme increased by 300% [1] similar improvement has also been observed in this new design of half substractor.

ACKNOWLEDGMENT

We would like to thank the faculty of Electrical and Electronic Engineering (EEE) department of Ahsanullah University of Science and Technology (AUST) to provide us all sufficient components and their kind help to make this work possible. We would like to thank Dr. Kazi Shariful Alam, Vice Chancellor, AUST and Professor Md. Abdur Rahim Mollah, Head of the department of EEE, AUST, for their support that has enabled us to complete our work.

REFERENCES [1] A. A. Hadi, J. U. Ahmed, Md. M. Muntasir, S. I. Chowdhury, T. Aqib,

“Polarization Encoded Optical Shadow Casting Logic Units: Design of Trinary Combinational Arithmetic Units Using Various Input Coding Scheme” Proc. ICECTE 2012 International Conf. for Electrical, Computer and Telecommunication Engineering, PI-0137, RUET, Bangladesh, 2012.

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[3]. Tanida, J., & Ichioka, Y. (1983). Optical logic array processor using shadowgrams. J. Opt. Soc. Am. , 73 (6), 800-809.

[4]. M. A. Karim, A. A. S. Awwal, and A. K. Cherri, “Polarization Encoded Optical Shadow Casting Logic Units: Design,” Appl. Opt. 26, 2720 (1987).

[5]. A. A. S. Awwal, M. A. Karim, and A. K. Cherri, "Polarization- Encoded Optical Shadow-Casting Scheme: Design of Multi- Output Trinary Combinational Logic Units," Appl. Opt. 26,4814 (1987).

[6]. Rizvi, R. A., Zaheer, K., & Zubairy, M. S. (1991). Implementation of trinary logic in a polarization encoded optical shadow-casting scheme. Appl. Opt. , 30 (8), 936-941.

[7]. R. A. Rizvi, K. Zaheer, and M. S. Zubairy, "Separate and Simultaneous Generation of Multioutputs in a Polarization-Encoded Optical Shadow-Casting Scheme: Design of Half- and Full Adders and Subtractors," Appl. Opt. 27, 5176 (1988).

598 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)