Optimization of Micro and Nano Research and Development Fabrication Operations

R. J. Olson, Jr., W. G. Hawkins, P. A. Piacente, R. Frank, J. A. Deluca, L. R. Douglas and G. P. Trant

Micro and Nano Structures Technologies GE Global Research

Niskayuna, NY 12065 USA olsonr@research.ge.com

Abstract— In order to stay competitive in today’s markets, companies are faced with lowering the cost of research and development while increasing technology capacity, reducing research lot cycle times and maintaining process control, and improving quality of numerous technology platforms. This poster will present an overview of the strategy and outcome of a multi year effort to improve the productivity of General Electric’s Global Research Center (GRC) micro and nano systems technology (MNST) semiconductor cleanroom operations. A lean six-sigma approach was used to identify and analyze metrics that would lead to an understanding of factors critical to fab efficiency. Initiatives showed areas of improvement to be centered around: cleanroom equipment, fab lot loading/priority, documentation, and equipment. Further analysis revealed key metrics to analyze and track performance as, throughput, equipment uptime, process time, and process lot queue time. After implementing this lean six sigma approach metric data showed an initial cycle time improvement of more than 3X, a 41% queue time reduction (figure 1) from 2006 to 2009 and a 30% productivity improvement while realizing an overall fab loading increase of 54% from 2006 to 2009.

Figure 1. Overall average micro and nano fab queue time 1Q06 – 4Q09 queue time decreased 41% from 06 –09.

Average Queue Time - Total Fab

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US 978-1-4244-4732-9/10/$25.00 ©2010 IEEE