Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os

Yves Blaquière Département d’informatique

Université du Québec à Montréal Montréal, Canada

Blaquiere.Yves@uqam.ca

Yvon Savaria, Jaouad El Fouladi Département de génie électrique

École Polytechnique Montréal, Canada

savaria@grm.polymtl.ca

Abstract— A technique is required to detect capacitance variation on an integrated circuit I/O using only digital ASIC cells. A ring oscillator based design is investigated to make use of the well known property that its period varies linearly with capacitance. It is shown that a loaded ring oscillator does not behave as expected in some situations. Conditions for linear behavior are established. It is shown that the detection range of capacitance can be considerably improved with a sufficient delay into the ring or by imposing different voltage thresholds on the slowest ring oscillator node, as can be done with a Schmitt-trigger.

I. INTRODUCTION This paper investigates means of detecting capacitance

variations on integrated circuit (IC) I/Os. This would allow detecting if an I/O is electrically connected or not to a PCB trace, to other IC I/O(s) or to connectors on a PCB, where capacitance can reach several picoFarads. The capacitance variation on an I/O due to a PCB trace can be large if compared to the small capacitance seen on a digital IC I/O, which is typically smaller than one or two pF. This new measurement technique could be used during PCB production testing to detect defects on PCB traces.

Several techniques that have been proposed to accurately measure capacitance values or its variation are based on analog or mixed digital/analog circuits. For example, charge-based capacitance measurement techniques have recently been used for process characterization and monitoring in embedded test structures [1-3]. As stated in [4], there exist several sensor interface analog circuits that can be used for accurate capacitance measurement, including conversion from capacitance to frequency, to phase or to voltage. Others have used a capacitance-controlled oscillator to produce pulses with duration proportional to some measured capacitances. These circuits are mostly based on analog modules such as operational amplifiers [4].

This paper proposes a capacitance measurement technique based only on digital ASIC cells, i.e. without any

analog cells or circuits. To get a digital-only solution, a simple ring oscillator was selected. Indeed, the ring oscillator is usually composed of straight inverters, and its period of oscillation is twice the delay around the loop. As the delay of an inverter is directly proportional to its output capacitive load, the ring oscillator was selected as a good candidate to obtain a detector whose frequency would be roughly linear with the output load. Such a detector could then be used to discriminate capacitance values on an IC I/O. The first section shows that this expected linear property does not hold under some specific conditions. After reviewing in Section III the basic ring oscillator theory of operation, the observed non-linear behavior is then analyzed and conditions that lead to a linear relation are determined in Section IV. Finally, it is shown in Section V that a linear behavior can be ensured over a wide range of capacitance value by using a Schmitt trigger based oscillator. Our main results are summarized in Section VI.

II. NON-LINEAR OSCILLATION PERIOD BEHAVIOR OF A SIMPLE RING OSCILLATOR

The CMOS ring oscillator is a de facto standard circuit for delay measurement and process characterization. This circuit is built from an odd number, N, of inverters connected in a circular chain. Its oscillation period is known to be strongly dependant on the capacitance at the output of each inverter. The target application addressed in this paper requires detecting capacitance variations on IC I/Os. Intuitively, an IC I/O could be included in a ring oscillator, as shown in Fig. 1. The oscillation period (Tloaded) could then be measured and compared to the one without load on the IC I/O (Tunloaded). The oscillation period difference, ∆T=Tloaded -

Figure 1 Ring Oscillator Model

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Tunloaded, or ratio = Tloaded/Tunloaded could then be used as a means to discriminate capacitance value seen on the IC I/O, especially if the oscillation period is linearly dependent on I/O capacitance.

An unexpected behavior has been obtained with this simple circuit, where the oscillation period does not vary linearly with CI/O when it is large. As shown in Fig. 2, the oscillation period of a ring oscillator, with N=11 CMOS inverters, simulated with 0.18 µm TSMC CMOS technology, tends to asymptotically saturate as CI/O increases. The discrimination

0

2

4

6

8

10

12

0 1 2 3 4 5

Osc

illat

ion

Perio

dT

(ns)

CI/O (pF)

Figure 2 Non-linear property of the oscillation period of a ring oscillator when only one node is loaded with a

capacitance CI/O.

capability of the circuit is therefore significantly reduced. The next section provides an explanation of this behaviour.

III. REVIEW OF RING OSCILLATOR BEHAVIOR The oscillation period of a ring oscillator is equal to

T=2Ntpd when the stages are identical, where tpd is the average propagation time of the inverter, which could be evaluated by equation (1) [5].

Ldsatpdsatn

DDLpd KC

IIVC

t =⎟⎟⎠

⎞⎜⎜⎝

⎛+=

11η

(1)

IDSAT is the drain saturation current; η is a constant that depends on technology (approximately equal to 4); CL is the total load capacitance of each CMOS inverter that can be modeled from its two main components as

( )ox

oxpn

LL

tLWWa

C

CCCox

ε++=

+=

1

1

(2)

where oxLC represents all tox related capacitance (i.e., gate and

part of overlap capacitance); a is a parameter that depends on Miller and charge partition effects among multiple capacitive devices in the inverter; C1 represents the junction and interconnect capacitances, which are not related to tox; and

Figure 3 Linear dependency of oscillation period T of N inverter ring oscillators with extrinsic capacitance C1.

Wn and Wp are the widths of n and p MOSFET, respectively. Notice that for some given total area of an inverter, i.e. expressed by (Wn+Wp) assuming the transistor length L is fixed at minimum size, tpd is minimized when the ratio

4.1/ ≈≈ pnpn /JJWW , where Jn and Jp are the saturation currents per unit width for n and p MOSFET.

A linear dependency on C1 of the oscillation period T is predicted by equation (1) and this is clearly confirmed in Fig. 3, generated from Hspice simulations with N = 3, 5, 7 and 11 identical sized CMOS inverters. This linear property of the oscillation period T of a ring oscillator, as a function of the extrinsic capacitance, can be exploited to detect capacitance variations on ring oscillator nodes, if the same capacitive load is added to each node and the environmental conditions (oT, VDD, process) do not change.

Unfortunately, in our application, capacitance variations would only appear on one node of the ring oscillator (the one connected to the I/O), while the capacitance on the others does not change. In this case, the oscillation period can be expressed by equation (3)

( )( )( ) ( ) ( )( )

( )( ) I/OI/O1

1I/OI/O1

I/O

2

1

if 2

12

12

KKKCCCNK

CCCKCCKN

ttNtT

ox

oxox

L

LL

pdpd

N

iipd

=++=

++++−=

+−== ∑=

(3)

where KI/O is the constant K of the inverter driving the loaded IC I/O. It can be shown that the detection sensitivity is maximized when ∂T/∂CI/O=KI/O is maximized. In other words, the equivalent resistance of the inverter driving the I/O should be maximized for better sensitivity, which also minimizes the relative contribution to the period of the other inverter delays.

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IV. NONOVERLPAPPING CONDITION FOR LINEAR BEHAVIOR OF RING OSCILLATOR WITH CAPACITANCE The linear dependency of the oscillation period with the

capacitance loading the ring oscillator predicted by equation (3) is valid when all stages are identical. This limit can be expressed according to a condition that we call the non-overlapping condition. The non-overlapping condition can be simply expressed as 2Ntpd > tf + tr for each stage. When this condition is not met, the wave that corresponds to one signal polarity propagating over the inverter chain in the ring will overlap with the one of opposite polarity on one or more stages, which will dampen the oscillations. This condition depends on inverter characteristics and N [6].

It was found that equations (1) and (3) are valid if and only if the non-overlapping condition is met for all the ring oscillator nodes, i.e. when the signal on all inverter output nodes can reach both power rail voltages before the inverter driving that node starts reversing the transition polarity. In the case of a ring oscillator comprising one loaded node, this condition can be expressed as equation (4), where N is the delay of the inverter driving the loaded I/O, as shown in Fig. 1. The loop delay is equal to the sum of all inverter delays in the ring oscillator without the delay of the inverter driving the IC I/O.

Npd

N

iipd ttt >=∆= ∑

−

=

1

1delay loop (4)

Loading one and only one ring oscillator node with a large capacitance can dampen the signal on this loaded node, as shown in Fig. 4. For example, the signal on an IC I/O loaded with a small capacitance CI/O=1fF in Fig. 4 meets the non-overlapping condition (no damping). However, in presence of a large CI/O, as seen with CI/O = 0.1 pF in Fig. 4, large rising or falling times at the output of inverter N in Fig. 1 are observed. These delays can be larger than the sum of all other inverter delays in a short chain. In this case, the signal on the IC I/O oscillates around the threshold voltage of inverter N.

The larger CI/O is, the smaller the slope on IC I/O will be. The attenuation on signal V(N) will also be more severe, as shown in Fig. 5. Effectively, adding a capacitance decreases the single-pole transfer in the inverter gain, which results in a monotonic 20dB/decade gain roll-off. This damping effect is also seen on several successive ring oscillator stages for larger CI/O (e.g. V(1) in Fig. 5 @CI/O>0.6pF). In this case, the delay of inverter 1 in Fig. 1 cannot be predicted by equation (1), because the input signal slope is small [7] and its input signal does not reach power rails at each cycle.

The triangular shape seen in Fig. 4 for the signal with a large CI/O=1pF shows that the inverter behaves as an integrator. In fact, the constant current provided by the velocity saturated transistors implies that the rising or falling time at I/O node is equal to ∆t=CI/O∆V/IDSAT. The loop delay, ∆t, would be constant if all inverters in the ring oscillator had time to reach the power rail VDD=1.8V. This condition

Figure 4 Transient response of the IC I/O signal for

different capacitance C1 on IC I/O.

 

0,0

0,3

0,6

0,9

1,2

1,5

1,8

0

2

4

6

8

10

12

0 1 2 3 4 5 Peak

-to-P

eak

Am

plitu

de (

V)

Osc

illat

ion

Perio

dT

(ns)

CI/O (pF)

V(N) Peak-to-Peak Amplitude

Oscillation Period T

V(1) Peak-to-Peak Amplitude

Figure 5 Ring oscillator period and damping effect of signal on nodes 1 and N on Fig. 1 for different CI/O.

implies that the input signal amplitude times the inverter gain must be large enough to saturate the inverter output signal. If this condition is met for all inverters except the loaded one, the oscillation period, as well as ∆t=CI/O∆V/IDSAT, would be constant and ∆V would decrease in proportion when CI/O increases. However, the large CI/O on node N attenuates V(N) to a critical amplitude, where V(1) does not reach power rails VDD or VSS and the propagation delay of inverter 1 increases.

Notice that the ring oscillator will oscillate, even with very large CI/O, as long as it satisfies the well known oscillation condition, i.e. the circuit’s loop gain at the oscillating frequency that yields a zero phase shift around the loop, must be larger than unity.

V. LINEAR PROPERTY OF A SCHMITT TRIGGER RING OSCILLATOR FOR CAPACITANCE VARIATION DETECTION

The linear property of the ring oscillation period with capacitance is limited to relatively small capacitances on the loaded node. To improve the discrimination for any capacitance, the loaded node can be followed by a simple Schmitt Trigger gate, as shown in Fig. 6.

This circuit behaves as a relaxation oscillator as shown by simulation results in Fig. 7 obtained for a Schmitt-trigger buffer using the topology proposed by [6]. It ensures that the output of the Schmitt-trigger gate changes state only when

0.0

0.4

0.8

1.2

1.6

2.0

0 1 2 3 4 5 6 7 8 9 10Time (ns)

CI/O=1fF 0.1pF

1pF 10pF

Sign

al o

n lo

aded

nod

e (V

)

44

Figure 6 Schmitt-Triggered ring oscillator

V(N) reaches (VH) or (VL) its high and low transition points. Fig. 8 clearly shows that the oscillation period of this Schmitt-trigger based ring oscillator grows linearly with CI/O for any capacitive load. The large delay produced by the slow rising or falling transitions on node N therefore ensure that each inverter in the ring has time to reach the power rails before the next transition. For relatively large CI/O, the sum of delays of each inverter becomes negligible and the oscillation period is dominated by the transition at the output of the gate driving CI/O. Fig.8 confirms this statement where the oscillation period difference for 1 and 11 stage oscillators, caused by the inverter delays, is extremely small. In this case, the transition duration can be predicted from equation (5) and (6) [8].

DSATI/Oosc / ICKt = (5)

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−−

⎟⎟⎠

⎞⎜⎜⎝

⎛=

HDD

LDD

L

Hosc ln

VVVV

VVK (6)

Notice that the transition points of the Schmitt trigger are determined by the supply voltage VDD and the threshold voltages of transistors. These threshold voltages have a strong dependence on process parameters and substrate temperature which can be cancelled out by computing the ratio = Tloaded/Tunloaded for better capacitance discrimination [8].

VI. CONCLUSIONS Two techniques to detect capacitance variation on an integrated circuit I/O using only digital ASIC cells have been analyzed. The ring oscillator was a promising candidate considering its well known property that the oscillation period is linearly dependant on capacitance. We found that when loaded on only one ring node, this linear property is only valid for relatively small capacitances. It was shown that in imbalanced ring oscillators, the discrimination capability degrades as the capacitance grows. It is mainly caused by a limited inverter gain, attenuated by the capacitance at its output, which dampens the signal on this loaded node as well as on its successive nodes. It was proposed to simply add one Schmitt-trigger gate to the ring oscillator to obtain a fully linear dependency of the frequency as a function of the load for any capacitance value on the loaded node. Moreover, this circuit could be reduced to only one stage without any discrimination penalty.

0

0.4

0.8

1.2

1.6

2

0 25 50 75 100

Time (ns)

Sign

al o

n lo

aded

nod

e (V

)

C I/O=0pF 1pF 5pF2pF 3pF

Figure 7 Example of transient responses for different

CI/O with the Schmitt-trigger ring oscillator of Fig. 6 with N=11 inverter stages.

 

0

20

40

60

80

100

120

140

160

0 1 2 3 4 5

Osc

illat

ion

Perio

d T

(ns)

CI/O (pF)

11 stages1 stage

Figure 8 Oscillation period for different capacitances on IC I/O, for N=1 and 11 stage Schmitt-Trigger based ring

oscillators of Fig. 6.

REFERENCES [1] A. Khalkhal and P. Nouet, “On-Chip Measurement of Interconnect

Capacitances in a CMOS Process,” Proc. IEEE 1995 Int. Conf. on Microelectronic Test Structures, vol. 8, March, pp. 145 – 149, 1995.

[2] G.J. Gaston and I.G. Daniels, “Efficient Extraction of Metal Parasitic Capacitances,” Proc. IEEE 1995 Int. Conf. on Microelectronic Test Structures, vol. 8, March, pp. 157-160, 1995.

[3] Chen, J.C.; McGaughy, B.W.; Sylvester, D.; Chenming Hu; An On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement (CBCM) Technique, International Electron Devices Meeting , 8-11 Dec. , pp. 69 – 72, 1996.

[4] Ignjatovic, Z. and M. F. Bocko, "An interface circuit for measuring capacitance changes based upon capacitance-to-duty cycle (CDC) converter." Sensors Journal, IEEE, 5(3), pp.403-410, 2005.

[5] K. Chen, H. C. Wann, P. K. Ko, and H. Chenming, "The impact of device scaling and power supply change on CMOS gate performance," Electron Device Letters, vol. 17, pp. 202-204, 1996.

[6] J.M. Rabaey et al., Digital Integrated Circuits : A Design Perspective, Prentice Hall, Second Edition, p.28, pp. 364-366, 2003.

[7] N. Hedenstierna and K. O. Jeppson, "CMOS Circuit Speed and Buffer Optimization," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 6, pp. 270-281, 1987.

[8] A. Wokhlu, R. V. Krishna, and S. Agarwal, "A low voltage mixed signal ASIC for digital clinical thermometer,", Proc. of Eleventh International Conference on VLSI Design, pp. 412-417, 1998.

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