Hybrid Active Pixel Sensors and SOI-Inspired Option

M. Baranski, W. Kucewicz, S. Kuta, W. Machowski, H. Niemiec, M. SaporUniversity of Mining and Metallurgy, Krakow

K. Domanski, P. Grabiec, M. Grodner, K. Kucharski, B. Jaroszewicz, J. Marczewski, D. Tomaszewski

Institute of Electron Technology, Warszawa

M. Amati, A. Bulgheroni, M. Caccia University of Insubria, Como

Presented by Halina Niemiec

Hybrid Active Pixel Sensors with interleaved pixels

Charge collection and resolution New prototype

SOI monolithic detectors Technology challenges

Test structures and readout prototype

Solutions for future linear collider Vertex Tracker

Hybrid Active Pixel Sensors with Interleaved Pixels -

Motivation

Vertex Tracker for future linear collider should provide:

Single point resolution better then 10 m

Limitations of pixel detectors: Dimensions of readout electronics cell Number of readout channels – power

dissipation, readout speed

Possible solutionHybrid Detectors with Interleaved Pixels

Hybrid Pixel Detector with Interleaved Pixels

Charge carriers generated underneath one of the interleaved pixel cells induce a signal on the capacitively coupled read-out pixels, leading to

a spatial accuracy improvement by a proper signal interpolation.

p+

n

PolyresistorInterleaved pixelReadout pixelreadout pitch = n x pixel pitch

Large enough to house the

VLSI front-end cell

Small enough for an effective

sampling

HAPS - First Prototype

Fabricated by Institute of Electron Technology in Warsaw, Poland

AC coupled, biasing via polysilicon resistors

36 test structures with 17 different configurations:

implant width: 34 – 100 m

pixel pitch: 50 – 150 m

# of interleaved pixels: 0-3

readout pitches in both dimensions: 200 and 300 m

Detector Modeling as Capacitive Network

The expected charge loss depends on the ratio between the interpixel and

backplane capacitance

Cc

Ci

Ci

Cb

Cb- backplane capacitance

Ci - interpixel capacitance

CC- coupling capacitance

Pixel Capacitance Measurements

Measurements with HP 4280 meter @ 1 MHz

3 bias lines were scratched

Capacitance was measured for

each of lines

3 doublets in parallel

1 triplet

Offset in the linear regression for the capacitance versus the number of lines - left-over parasitic contributions after the cable correction

2 independent measurements

Pixel Capacitance Measurements Measurements results were compared with

calculated values (OPERA 3D package) Max charge loss was estimated using time

domain and simply steady-state method

Design OptimizationTime Domain Simulations

Ggnd from 5 to 20 MOhms Increase of CCE by 26%

Increase of Cip by 50 % Increase of CCE by 23%

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Time [ns]

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V]

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d p

ixe

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ixe

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Charge Sharing Studies

Structure under test: 60 m implant width

100 m pixel pitch

200 m readout pitch

Tests with infrared diode: Wavelength: 880 nm (penetration depth

in silicon substrate: 10 m)

Spot size: below 85 m, position controlled by 2D stage with micrometric accuracy

p+

n

Laser light spot Automatic displacement system

The read-out pixels were wire bonded to

the readout electronics chip.

The BELLE experiment amplifiers and readout

chain were used

Test Module

Charge Sharing Studies

Description of charge collection properties: Charge sharing:

= PHR/PHcluster

PHR – pulse height on reference pixel,

PHcluster – cluster pulse height

Charge Collection Efficiency CCE Cluster pulse height normalized to its maximum value, corresponding to a charge release underneath an output node

Charge Sharing Studies

CCE

Max charge loss:

40%

In good agreement with estimated values for capacitive network

Interleaved

Readout

Charge Sharing Studies – Resolution

Resolution: Interleaved pixels (efficient charge sharing): 3 m Readout pixels (min charge sharing): 10 m

parameterization allows a coordinate reconstruction and resolution measurement

function Average resolution Resolution vs. spot position

Resolution – Conclusion

Binary resolution defined by

12/_ pitchimplant

can be improved by about a factor 4 for a configuration where the ratio between the charge carrier cloud r.m.s. and the pixel pitch 0.8

Similar scaling factor can be expected for a minimum ionizing particle detected by a pixel sensor with 20 - 25 m pitch as long as S/N100 and the charge loss is 50%

Hybrid Pixel Detector with Interleaved Pixels – New

Prototype

Pixel pitch – 25 m x 25 m and 25 m x 50

m Better single point resolution Lower backplane capacitance

Punch-through mechanism for pixel biasing Smaller distance between pixels – higher

interpixel capacitance High value of biasing resistance Elimination of polysilicon resistors from

technological process

New Prototype - Topology

PixelBias grid

p+ diffusion dots for punch-trough mechanism

Punch-through Mechanism Simulations

ATLAS and ATHENA software (SILVACO)

Bias line

Pixel electrode

Hybrid Pixel Detector with Interleaved Pixels – New

Prototype

Detectors were fabricated by Institute of Electron Technology, Warsaw

Electrostatic characteristics measurements and charge

collection studies are planned on a short time

scale

SOI Monolithic Detector – Motivation

The SOI Imager project is partially financed by European Commission within 5-th Framework Program

Advantages of SOI monolithic detectors: SOI imager as a monolithic device allows to

reduce total sensor thickness

Performance and radiation tolerance of readout electronics may benefit from reduction of active silicon thickness

SOI solution allows to use high resistive detector substrates

SOI Imager – Main Concept

Detector handle wafer High resistive 300 m thick

Electronics active layer Low resistive 1.5 m thick

Detector: conventional p+-n, DC-coupled

Electronics: preliminary solution – conventional bulk MOS technology on the thick SOI substrate

SOI Substrate for Monolithic Detectors

SOI detectors require high quality handle wafer substrate

Popular SOI production methods base on SIMOX (separation by implantation of oxygen) and Wafer-Bonding (wafer oxidation, bonding and thinning, e.g. BESOI, Unibond®)

Advantages of Unibond® method over SIMOX from SOI imager point of view:

Resistivity of handle (for detector) and donor (for electronics) wafer may be optimized

No silicon inclusions and islands in buried oxide

An order lower dislocation density

SOI Imager – Technology Development

Technology of SOI detectors

– integration of pixel manufacturing technique with typical CMOS polySi gate technology

Challenges: Quasi-simultaneous fabrication of circuits at both

sides of the BOX layer

Electrical connection to the pixel junction

Thermal budget of the whole sequence and technological sequence of high temperature processes

Cross-talk between read-out electronics and detector

SOI Imager – Technology Development

Technological sequence over 100 processes

SOI Imager – Technology Development

Technology DevelopmentExperiments on SOITEC Wafers

The bulk test structures has been used to produce SOI transistors on SOITEC wafers

The technology sequence was similar as it is provided for SOI detectors

The substrate parameters are exactly the same like for future SOI detectors except low resistivity of the handle wafers

Technological experiment was performed to validate and adjust the

technology

Technology DevelopmentExperiments on SOITEC Wafers

The CMOS transistors on thin substrate (SOI) have different doping profiles than the bulk ones. Parameters of well implantation were

changed to get Vth=0.7+/-0.2V at reasonable VBR ( 19 V)

Technology DevelopmentSOI Test Structures

For complete technology characterization special SOI test structure was designed

General technological test structures for parameters extraction, investigation of device mismatches, process control, reliability test

Examples of analogue and digital circuits for comparison simulation and measurements results

Specific test structures for SOI detector applications

Technology DevelopmentSOI Test Structures

Module for extraction of pixels p-n junctions parameters in deep cavities

Reliability test structure: chain of contact windows for pixel detectors and metal1 serpentine over deep detector contact window

Matrices of simple readout channels with contacts to detectors

Dedicated test structures for SOI detector application:

Technology DevelopmentSOI Test Structures

Readout circuits with detector contacts on SOI substrate

Preliminary solution

Technology DevelopmentSOI Test Structures

The SOI test structures will be fabricated by IET,

Warsaw by the end of the year

Readout Circuit DevelopmentPrototyping in Commercial

Technology

In parallel with technology development work on readout circuit prototyping is carried on. First

prototype was designed in 0.8 AMS technology

Row_sel<0>

Column_sel<0>

Column_sel<1>

Column_sel<31>

Reset_rowl<0>

Row_sel<1>

Row_sel<31>

Reset_rowl<1>

Reset_rowl<31>

Sample I-after reset

Sample II-after integration time

Charge integration

Readout sequence

Compatible with external CDS processing

Detector dead time is limited to the reset time of integrating element

Integration time of every channel is well defined

ConclusionTwo paths of active pixel detectors development

were presented:

HAPS with interleaved pixels Prototype detectors have been manufactured Preliminary charge collection studies have confirmed

the validity of this detector concept

Measurements of second prototype (with 25 m) are planned on a short time scale

SOI detectors Concept of detector and technological solutions were

presented Dedicated test structure and readout prototype were

designed and are expected to be fabricated by the and of the year