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Mateusz Baszczyk, Piotr Dorosz, Wojciech Kucewicz, AGH-UST Krakow

Claudio Gotti, Gianluigi Pessina, INFN-Milano Bicocca

Angelo Cotta Ramusino, INFN-Ferrara

CLARO 8ch ASIC: configuration register with Triple Modular Redundancy protection

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Topic• introduction • TMR protected configuration register compatible with the SPI port of the GBT-SCA device • preliminary pad assignment • proposed mixed signal design flow • HDL synthesis with RTL Compiler • preliminary floorplan for analog and digital parts • preliminary P&R of configuration register • extra slides: detailed information

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GBT-SCA, a general-purpose integrated circuit for the monitoring and control of the electronics in HEP experimentsThe Slow Control Adapter (SCA) chip is designed to work in parallel with to the GBT optical link bidirectional transceiver system of which it extends the functionality.

• introduction

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• introduction

(*) GBT-SCA: The Slow Control Adapter for the GBT SystemAlessandro Gabrielli, Kostas Kloukinas, Paulo Moreira, Alessandro Marchioro, Sandro Bonacini, Filipe Sousa

The current CLARO prototype will be upgraded with an SPI-compliant configuration register, so that configuration and monitoring of the upgraded RICH front end electronics will be handled by the GBT-SCA ASIC (*)

The 128bit ( it was 64 at the time of the review) configuration/status register being proposed here is protected by TMR (Triple Modular Redundancy). An “nSEU_detected” CLARO output pin (open drain) activates when bit flip(s) occur in any TMR cell. A pulse on the “SEU correct” CLARO input pin repairs the bit flip and this clears, in turn, the “SEU_detected” flag.The occurrences of “SEU_detected” onsets could be detected, counted and cleared through the GBT-SCA general purpose parallel I/O (PIA) ports.

The current version of CLARO configuration/status register presented here also foresees a self correction circuit for the SEU events. This feature is accompanied by an internal counter for “SEU_detected” events, whose value is read back, along with the TMR-protected configuration bits, on every 128-bit SPI transaction scheduled by the GBT-SCA.

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• TMR protected configuration register compatible with the SPI port of the GBT-SCA device

CLARO configuration block design hierarchy

I/O Shift register connected to the SPI interfaceSPI in SPI out

block diagram of the CLARO configuration block

from I/O shift register

(96+8)bit storage register Ato voter/SEU detect

from voter

from voter

(96+8)bit storage register Bto voter/SEU detect

from voter

(96+8)bit storage register Cto voter/SEU detect

from voter

(96+8)bit majority voter

A

A B C

B C

(96+8)bit SEU detect

A B C

cfg bits to CLARO core

to registers

MUX MUX MUX

16 bit SEU counter

128 bit parallel input port for data to shift out

SEU self correction pulse generatorto storage reg.

from self corr.pulse generator

from self corr.pulse generator

from self corr.pulse generator

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• preliminary pad assignment

agnd

agnd

agnd

agnd

agnd

agnd

TOP VIEW

in1

in2

in3

in4

in5

in6

TEST analog voltage level

in0 in7Input amplifiers

Threshold DACs

Output comparators

Configuration register with SPI interface and

TMR protection

tstp1 (amp 0 output)

amp_bias_current

tstp2 (dac0 output)

SPI_CLK

MOSI

SEU_generation_enable

MISO

SEU_CORRECT_clk

nSEL

nSEU_detected_OC_out TEST_PULSE_IN

out0 out7

dgnd

dvdd

dgnd

dgnd

dvdd

dgnd

out1

out2

out3

out4

out5

out6

avdd avdd

CHAIN_ENABLE_INdvdd

thresh_current

avdd

comp_bias_current

after a few iterations with C. Gotti

dgnd

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HDL Description

RTL Compiler

Report Timing, Hierarchy

Config Files,Attributes,Constraints

Synthesis

RQMTMet?

EncounterAttributes,Constraints

RQMTMet?

Floorplanning Digital Parts

Non-timingPlacement

Pre CTS Flow

Post CTS Flow

Post Route Flow

Encounter/ Virtuoso

Chip Assembly

Mixed Signal Routing

Virtuoso

Simulation

RQMTMet?

Design Check

RTL SimulationRTL Simulation

SIGNOFF

YESNO

YESNO YES

INIT

NO

EncounterFloorplanning

Analog and Digital

Power Routing

Partitioning

VirtuosoFloorplanning Analog Parts

Simulation

Design Flow

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RTL Compiler

Part of Configuration file, which prevents from deleting TMR:set_attribute merge_combinational_hier_instance falsesynthesize -to_generic -csa_effort medium -effort medium # Perform Generic Optimisationsynthesize -to_mapped -effort medium # Perform technology mapping and optimisation

Synthesis

Triple Modular Redundancy

Trzeba odpowiednio skonfigurować program , aby nie wyrzucił redundancji

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Encounter

Digital Part

Analog Parts (define as Black Box with In/Out Pins)

Floorplanning Analog and

Digital

Partitioning

In/Out Pad Ring

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Encounter

TMR modules were defined as Fences then Standard Cells for each module were placed separately, which should prevent from double errors.

Floorplanning Digital Part

Non-timingPlacement

Physical View

Amoeba View

Voter and Registers A

Voter and Registers BVoter and Registers C

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Encounter

Because technology contains four metals – for routing ‚wroute’ command was used. Physical View

Amoeba View

Voter and Registers A

Voter and Registers BVoter and Registers C

Post CTS Flow Post Route Flow

Deafult optimization parameters were change (,optDesign’ command), because Encounter was deleting TMR modules.In Design Optimization some Standard Cells were moved (TMR separation was disturbed), in another case routing ends with DRC violations and timing mismatches (i.e.)

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Encounter Post CTS Flow

Post Route Flow

BuffersClock Buffers

Hierarchical ViewVoters A, B, C

Registers A,B, C

SEU detector

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Encounter Post Route Flow

Clock coinstraints

Design meets timing constraints

Report

WNS parameter is positive

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Detailed Information

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Encounter Post CTS Flow

Hierarchical View

Deleted Voters B and C

Optimization with default parameters deletes TMR modules.

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Encounter Post CTS Flow

Every hierarchical module was define as Fence. Optimization with presented parameters doesen’t delete TMR modules, and enable wrouter routes nets without violations, but it disturbs TMR modules separation.setOptMode -simplifyNetlist false -deleteInst false -restruct false -downsizeInst falseoptDesign -postCTS

Screens present hierarchical modules placement – they are selected in red

SEU Detector

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Encounter Post CTS Flow

Voter C

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Encounter Post CTS Flow

Registers C

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Encounter Post CTS Flow

Voter B

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Encounter Post CTS Flow

Registers B

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Encounter Post CTS Flow

Voter A

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Encounter Post CTS Flow

Registers A

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Encounter Post CTS Flow

TMR output