hcal tpg and readout
DESCRIPTION
HCAL TPG and Readout. CMS HCal meeting at Rochester Oct. 19-20 Oct 2001 Tullio Grassi, Drew Baden University of Maryland Jim Rohlf Boston University. Level 1 Trigger. Detector Front End. Readout Crates. Online Controls. Event Manager. Event Builder. Level 2/3 Filter Units. - PowerPoint PPT PresentationTRANSCRIPT
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 1
HCAL TPG and Readout
CMS HCal meeting at Rochester Oct. 19-20 Oct 2001
Tullio Grassi, Drew BadenUniversity of Maryland
Jim RohlfBoston University
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 2
CMS TriDAS Architecture
• Data from CMS FE to T/DAQ Readout Crates
• Level 1 “primitives”– Crossing determined
– Summing
– Tx to Level 1 Trigger
– Data is pipelined waiting decision
• Level 1 accepts cause– Tx raw data to
concentrators
– Buffered and wait for DAQ readout
• System communication via separate path (TTC)– Clock, resets, errors, L1
accepts…
Event BuilderEvent
Manager
Level 1Trigger
Detector Front End
OnlineControls
Computing Services
ReadoutCrates
Level 2/3 FilterUnits
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 3
HCAL Contribution to T/DAQ
• Includes:– Receiver cards ( including fiber input receivers and deserializers)
– Cables to Level 1 Trigger system
– Concentrators
– VME crate CPU module
– VME crates and racks
• Everything between but not including:– Fibers from QIE FEs
– DAQ cables
Level 1Trigger
HCAL DataQIE Fibers Level 2
and DAQ
CMSHCAL
Trigger/DAQ Front End Readout Crate - Level 1 Buffer - Level 2 Concentrator - Crate CPU
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 4
HCAL FE/DAQ Overview
Shield Wall
CPU
DAQRUI
HPD
FE MODULE
DAQ DATASLINK64 [1 Gbit/s]
18 HTRs perReadout Crate
FRONT-ENDRBXReadout Box (On detector)
READ-OUT Crate(in UXA)
Trigger Primitives
Fibers at 1.6 Gb/s3 QIE-channels per fiber
QIE
QIE
QIE
QIE
QIE
QIE
CC
A
GOL
DCC
TTC
GOL
CC
A
HTR
HTR
HTR
CAL
REGIONAL
TRIGGER
32 bits@ 40 MHz
16 bits@ 80 MHz
CC
A
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 5
Readout Crate Components
• “BIT3” board – Commercial VME/PCI Interface to CPU– Slow monitoring
• FanOut board– FanOut of TTC stream– FanOut of RX_CK & RX_BC0
• HTR (HCAL Trigger and Readout) board– FE-Fiber input– TPs output (SLBs) to CRT– DAQ/TP Data output to DCC– Spy output
• DCC (Data Concentrator Card) board– Input from HTRs– Output to DAQ– Spy output
DCC
20 m CopperLinks 1 Gb/sDAQ
Calorimeter Regional Trigger
BIT3
Gbit Ethernet @ 1.6 Gb/s
FanOut
HTR
Front End Electronics
HTR
DCC
HTR
HTR ...
TTC fiber
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 6
HCAL TRIGGER and READOUT Card
• I/O on front panel: – Inputs: Raw data:
• 16 digital serial fibers from QIE, 3 HCAL channels per fiber = 48 HCAL channels
– Inputs: Timing (clock, orbit marker, etc.)• LVDS
– Outputs: DAQ data output to DCC• Two connector running LVDS
• TPG (Trigger Primitive Generator, HCAL Tower info to L1) via P2/P3– Via shielded twisted pair/Vitesse– Use aux card to hold Tx daughterboards
• FPGA logic implements:– Level 1 Path:
• Trigger primitive preparation• Transmission to Level 1
– Level 2/DAQ Path:• Buffering for Level 1 Decision• No filtering or crossing determination necessary• Transmission to DCC for Level 2/DAQ readout
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 7
HTR – “Dense” scheme
P1
DeSDeSDeS
DeS
DeS
DeS
DeS DeS
OPTICALRx
(8 LC)
P2LVDS Tx
LVDS Tx
P3
SLB -PMC
SLB -PMC
SLB -PMC
SLB -PMC
SLB -PMC
SLB -PMC
Trig
ger o
utp
ut
48 Trig
ger T
ow
ers
9U Board
DeSDeSDeS
FPGAXilinx
Vertex-2
DeS
DeS
DeS
DeS DeS
8 FE fibers24 QIE-ch’s
to DCC
OPTICALRx
(8 LC)
8 FE fibers24 QIE-ch’s
to DCC
FPGAXilinx
Vertex-2
Throughput: 17 Gb/sLatency: + 2 TCK
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 8
“Dense” HTR
• Strong reasons to push to dense scheme– Money
• Fewer boards!
– Programmable logic vs. hardware• Avoid hardware MUXs• Maintain synchronicity
– Single FPGA per 8 channels• Both L1/TPG and L1A/DCC processing• Xilinx Vertex-2 PRO will have deserializer chips built in!
– Saves $500/board– Many fewer connections– ~20 DeS->FPGA connections replaced by 1 1.6 GHz line– Challenges:
» Layout of 1.6 GHz signals» Schedule implications for final production may have to slip ~6 months to wait for Vertex-2 PRO
• What do we give up?– Each board much more epensive– More difficult layout– Need transition board to handle TPG output
• So does ECAL – common solution will be used
– Need 2 DCC/crate (but half the number of crates!)
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 9
Changes from HTR Demo to Final
• Front-end input– From 800MHz HP G-Links to 1600MHz TI Gigabit ethernet
• Timing– TTC daughterboard to TTC ASIC
• Core logic– Altera to Xilinx
• Trigger output– Moved to transition board
• Form factor– 6U to 9U
Output to DCC? Unchanged!!!
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 10
Status
• Front-end emulator HTR demonstrator DCC S-Link CPU– Successful operation of each individual link
• Integration underway - Tullio goes to Boston next week
• Pre-prototype board layout– Complete, board is now being stuffed– Will have only 1 FPGA with full complement of associated parts
• Will use the TI Deserializers – not the Vertex 2 PRO
– Internal use only
• Prototype layout– Should be complete in November
• Some changes from pre-prototype, but minor
• Maryland activity is in prep for source tests and 9U board design– Preparation for testbeam summer 02 not yet started– Trying hard to meet March 02 deadline for decision on which HTR to use
for testbeam
• Energy filters still undefined
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 11
Current HTR Timeline
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 12
DATA CONCENTRATOR CARD
Motherboard/daughterboard design:– Build motherboard to accommodate
• PCI interfaces (to PMC and PC-MIP)
• VME interface
– PC-MIP cards for data input• 3 LVDS inputs per card
• 6 cards per DCC (= 18 inputs)
• Engineering R&D courtesy of D– 1 PMC cards for
• Buffering:
– Transmission to L2/DAQ via CERN S-Link Tx
• http://hsi.web.cern.ch/HSI/s-link/D
ata
fro
m 1
8 H
TR
car
ds
6 P
C-M
IP m
ezz
ani
ne
car
ds
- 3
LV
DS
Rx
pe
r ca
rd
CERN S-LinkInterface with DAQ
To DAQ
PMC Logic BoardBuffers 1000 Events
PCI Interfaces
P2
P0
P1
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 13
Project Status Details DCC@BU
• VME Motherboard– Two prototypes working; 5 more
boards being built
• Link Receiver Board (LRB)– 10 second-generation boards
working
• DCC Logic Board– PCB Design complete; being
fabricated– FPGA coding underway
• Test Stand Hardware Complete– Pentium/Linux computer, TTC
System Working– Link Transmitters to simulate HRC
working– S-Link cards available
Companion LVDS Serial Link Transmitter
(for testing only)
DCC Logic Board
TTCRx
Xilinx VirtexII XC2V1000
2Mx32 DDRSDRAM
S-Link Source Card (optical fibre to DAQ)
3-Channel LVDS Serial Link Receiver
(6 used in final DCC)
PC-MIP PCI standard
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 14
• Fanout of TTC info:– Both TTC channels fanout to each HTR and DCC– Separate fanout of clock/BC0 for TPG synchronization
• “daSilva” scheme
• Single width VME module
HCAL TIMING FANOUT Module
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 15
Current Project Timeline
2001 2002 20032000
Prototype
New I/Os
Simple Algorithms
Pre-Prod
Corner cases, HF heavy ions
Production
Test bench
Slice Test I
FNAL source calib.
Cern Test
Beam
2004
Slice Test II
Pre-prod too short: not usefulTest bench before production ?Slice Test I with pre-production ?Vertex-2 PRO?
Demonstrator
Requirements
Resources
Links
6U board
STILL SOME UNCERTAINTIES…
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 16
Manpower
• All Engineering/technical identified and on board.
Drew BadenPhysicist
University of MarylandLevel 3 Manager
Drew BadenPhysicist
University of MarylandHTR Task
Jim RohlfPhysicist
Boston UniversityDCC Task
Mark AdamsPhysicist
Univ. of Ill, ChicagoHRC Task
Weiming QianEngineer
Univ. of Ill, ChicagoFull-time
Eric HazenSenior Engineer
BU50%
Shouxiang WuSenior Engineer
BU100%
Chris TullyPhysicist
Princeton University
Sarah EnoPhysicist
UMD
Suichi KunoriPhysicist
UMD
Salavat Abdoulinne
UMD
Post-Doc
Silvia Arcelli
UMD 30%
Post-Doc
Rob BardSenior Engineer
UMD50%
John GigantiSenior Engineer
UMDPart-time
Hans BredenEngineer
UMD
Rich BaumEngineer
UMD
Jack TouartEngineer
UMD
Tullio GrassiEngineer/Integration
UMD
Hardware Simulation
USCMS/Rochester. Oct 20, 2001 HCAL TriDAS 17
Project Status Summary• HTR (Maryland):
– 6U Demonstrator built and under test
• 800 Mbps G-Links works fine• Integration with FEE and DCC
underway
– 9U pre-Prototype layout done– 9U Prototype layout underway
• Still a few issues to decide– 1.6 Mbps link– FPGA choice (Vertex-2 vs Vertex-
2 PRO)– Link to Level 1 trigger
• Plan to have this board on the test bench by Dec ’01
• “HRC”– UIC engineer onboard April ‘01– Requirements have decreased,
card will be easy to complete
• DCC (BU)– DCC 9U motherboard built and
tested finished• PCI meets 33MHz spec• Card is done!
– Link Receiver Cards built and tested
• Done
– PMC logic board• First version complete• FPGA and etc. underway