hardware-defined software: concepts & architecture
TRANSCRIPT
Grenoble, October 14th 2009 2A708 SoftSOC page 1
SOFTSOC
SoftSoC Workshop â Grenoble, October 14th 2009
Christian FABRE â LETI â [email protected]
Eugenio VILLAR â Univ. of Cantabria â [email protected]
Emmanuel VAUMORIN â MAGILLEM â [email protected]
Hardware-defined Software:Concepts & Architecture
2
SOFTSOCPlan
1.HW/SW and SW/SW basic dependencies1.SW Taxonomies2.Case studies3.Basic SW Dependencies Conclusions
2.Layered Hardware-dependant-Software1.Introduction to HdS Stack2.Linux3.WinCE4.HdS Stack Conclusion
3.IP Xact & HdS
3
SOFTSOCLets Focus on BinaryâŚ
⢠SW IP can be delivered in source or binary form
⢠Source code is more abstract â Source code is actually a mean to shield from some hardware dependencies
⢠Binary only delivery won't go away anyway: binary-only-deliveries, specialized compute intensive code, etc
⢠In this part of the talk, software will mean binary software
4
SOFTSOC What a piece of software doesvs. what a piece of software is
⢠Software for what it does. Keywords areâ Signal processing, Video compression, Codecs,
Baseband radio, UMTS layers, CRC algorithms, etc.
⢠Software for what it is. Keywords areâ ARM binary, Libraries, intel ABI, POSIX API,
Instruction Set, x86 IS, DSP IS, VxWorks, eCos, etc.
5
SOFTSOCSW for ÂŤ What it does Âť
⢠Provides a business function taxonomyâ FFT, IFFT, CRC, dithering, etc.
⢠Provides relevant information to build systems from functions
⢠Answers the questionâ What function do I have to write/reuse/buy to
develop my application?
6
SOFTSOC
⢠Details the dependencies of (binary) software towardsâ Hardware
⢠Processor: instruction set, register set⢠Memory: Memory map, cache sizes & parameters⢠IP: registers banks, interruption
â Software⢠Compiler tool chain: ABI (appl. binary interface)⢠Other software: API (appl. programming interface)
â Operating system:⢠Driver framework
⢠Basis for assembly rules of SW dedicated on a given hardware
SW for ÂŤ What it is Âť
7
SOFTSOC
⢠IP-Xact is all about structural description of HW IPâ So should be its extensions for software
⢠We need first to express the necessary information required to decide if and how software can be assembledâ That's structural description of softwareâ Such description are mute about the business
functions implemented by a piece of software
Structure Before Business
8
SOFTSOCPlan
1.HW/SW and SW/SW basic dependencies1.SW Taxonomies2.Case studies3.Basic SW Dependencies Conclusions
2.Layered Hardware-dependant-Software1.Introduction to HdS Stack2.Linux3.WinCE4.HdS Stack Conclusion
3.IP Xact & HdS
9
SOFTSOC
⢠Software that compute cosine(x)â The software exported API is named
âmycosine.hââ Exports a single function âdouble
mycosine(double);â
⢠The SW IPâ Is named âmycosineââ Is compiled for ia32 with SSE instructions
A Simple Software IP (1/2):User Documentation
10
SOFTSOC
⢠Dependency towards the processorâ Requires a ia32 processor with SSE instructions
⢠Dependency towards the calling protocolâ Export its API through ABI v3.3 of GCC for ia32
⢠Dependency towards API descriptionsâ Is an implementation of âmycosine.hâ
A Simple Software IP (2/2):Detailed Dependencies
11
SOFTSOC
⢠The software exported APIâ Is named âmyfft.hââ Exports a single function
âdouble[] myfft(double[], size_t n);â
⢠The software binary implementationâ Is named âmyfftâ
⢠Requires another SW IPâ mycosine
⢠Is compiled for ia32 with SSE instructions
Another Simple Software IP (1/2):User Documentation
12
SOFTSOC
⢠Dependency towards the processorâ Requires a ia32 processor with SSE instructions
⢠Dependency towards the calling protocolâ Obeys ABI v3.3 of GCC for ia32
⢠Dependency towards API descriptionsâ Is an implementation of âmy-fft.hâ
⢠Depends on âmy-cosineâ
Another Simple Software IP (2/2):Detailed Dependencies
13
SOFTSOC
⢠A never-ending countdown (9 to 0) made of
⢠Hardwareâ A 386 processorâ A HW IP: 7 segment decoder for LCD display
⢠Named â7-seg-lcd-decoderâ⢠Exports a single 8 bit register with bits 0-6 writeable
â The register is mapped at 0x00000140⢠Software
â Closed softwareâ No operating systemâ No RTC: Calibrated software loops
HW IP-dependent SW IP (1/3):User Documentation
14
SOFTSOC
⢠Dependency towards the processorâ Requires a ia32 processor
⢠Dependency towards the calling protocolâ Obeys ia32 ABI v3.3
⢠Dependency towards API descriptionsâ <none>
⢠Dependency towards the HW IPâ One instance of hardware IP â7-seg-lcd-
decoderââ The memory map has it at 0x00000140
HW IP-dependent SW IP (2/3):Detailed Dependencies
15
SOFTSOC
⢠âOne instance 7-seg-lcd-decoderâ, means :â The SW IP shall drive the IP through registers
whose format is defined by the IP
⢠âThe memory map has the decoder at 0x0140ââ The register is memory mappedâ The SW IP code shall have the rights to access itâ Its address is known and constant at 0x0140
⢠These are strong dependencies on the way the software is architectured/built
HW IP-dependent SW IP (3/3):More Detailed Dependencies
16
SOFTSOC
⢠A Processor access several Memory Banks⢠Each Memory Bank is accessed at a single Base
Address⢠A Memory Bank is made of several Memory Cells⢠A Register is a Memory Cell⢠A HW IP exports several Memory Cells
Model of DependenciesII. Hardware IP & Processor
17
SOFTSOCPlan
1.HW/SW and SW/SW basic dependencies1.SW Taxonomies2.Case studies3.Basic SW Dependencies Conclusions
2.Layered Hardware-dependant-Software1.Introduction to HdS Stack2.Linux3.WinCE4.HdS Stack Conclusion
3.IP Xact & HdS
18
SOFTSOCSummary of SW/SW dependencies
⢠Automatic assembly is based on structural dependenciesâ Not easy: Move progressively from simple to
more complex casesâ Otherwise the README file will strike back
⢠Structural dependencies of HdS areâ Not only about dependencies over HW IPsâ But also about deeper SW dependencies
⢠Processors⢠Compilers ABI⢠Memory map⢠Boot ordering
19
SOFTSOCPlan
1.HW/SW and SW/SW basic dependencies1.SW Taxonomies2.Case studies3.Basic SW Dependencies Conclusions
2.Layered Hardware-dependant-Software1.Introduction to HdS Stack2.Linux3.WinCE4.HdS Stack Conclusion
3.IP Xact & HdS
20
SOFTSOC
CPU Interconnect
HW IP Prog. unit
Memory IO
Hardware DependentOS
Dep
ende
nt
Har
dwa r
e A
bst r
actio
n
OS Abstraction
HdS:The HW IP case
Hardware platform
Operating SystemHardware
Dependent Software
Application and Middleware SoftwareApplication â Platform
Interface
Hardware â SoftwareInterface
21
SOFTSOC
⢠More complex architecturesâ More complex HdSâ More complex HdS modelsâ Increased dependencies w.r.t. OS, HW,
ÂľProcessorâŚ
â Current âhand-writtenâ approach no longer valid
HdS:The HW IP case
22
SOFTSOC
MEMmodel
Ethernetmodel
I2C/BT656model
uProcessormodel
Platform Model
VideoEncoder(H264)
BUS
EthernetI2C/
BT656MEMuProcessor
SW H264
HdS:An structured approach
⢠Objectivesâ Automate the HdS generationâ Automate the HdS model generationâ Capsulate dependencies w.r.t. OS, HW,
ÂľProcessorâŚ
VideoEncodermodel
IP-XACT
OS HdS HdS
SWmodel
OSmodel
HdSmodel
HdSmodel
H264
23
SOFTSOC
HW PlatformuProcessor H264
HdS1 - iowr, iord
Application SWApplication SW
HdS:The Linux case
24
SOFTSOC
⢠Depends on:â Specific HW (H.264 HW component)â uProcessor (only if assembler code)â OS (through its register access functions)
⢠Objectives:â Basic functionalityâ Support low-level accesses to HW platform
⢠iord read request⢠iowr write request
HdS1:The Linux case
25
SOFTSOC
HdS2dev_init, dev_exit, dev_open,
dev_close, dev_read, dev_write,dev_ioctl, dev_irq_handler[n]
open, close, read, write, ioctl
OS
mem_reqrequest_irqScheduler
âŚ
Boot
OS API
HW PlatformuProcessor H264
HdS1 - iowr, iord
Application SWApplication SW
HdS2:The Linux case
26
SOFTSOC
⢠Depends on:â OS/RTOS (Linux in example)â Specific HW (H.264 HW component)â HdS1
⢠Objectives:â Establishes communication with OS/RTOSâ Defines OS/RTOS specific access functionsâ Provides services through OS/RTOS general
access functions
HdS2:The Linux case
27
SOFTSOC
HdS2dev_init, dev_exit, dev_open,
dev_close, dev_read, dev_write,dev_ioctl, dev_irq_handler[n]
open, close, read, write, ioctl
OS
mem_reqrequest_irqScheduler
âŚ
Boot
OS API
HW PlatformuProcessor H264
HdS1 - iowr, iord
Application SWApplication SW
HdS3:The Linux case
HdS3 API config, reset, encode
28
SOFTSOC
⢠Depends on:â Specific HW (H.264 HW component)â HdS2
⢠Objectives:â Defines specific functions according to HW
capabitiliesâ Encapsulate complex functionality in specific
functionsâ Provides abstraction from HW platform
HdS3:The Linux case
29
SOFTSOC
HdS2dev_init, dev_exit, dev_open,
dev_close, dev_read, dev_write,dev_ioctl, dev_irq_handler[n]
open, close, read, write, ioctl
OS
mem_reqrequest_irqScheduler
âŚ
Boot
OS API
HW PlatformuProcessor H264
HdS1 - iowr, iord
Application SWApplication SW
Middleware:The Linux case
HdS3 API config, reset, encode
GStreamer Plug-in CORBA Plug-in âŚ
TS
E
Sensor
30
SOFTSOC
⢠Depends on:â HW platform capabilitiesâ HdS3
⢠Objectives:â Adapts HdS3 to libraries and specific softwareâ Allows to merge HW platform capabilitiesâ In example: camera with H.264 video-encoded
streaming⢠Sensor + H.264 encoder + TSE
â Provides full abstraction from HW platform⢠Only performance-dependent
Middleware:The Linux case
31
SOFTSOC
HW PlatformuProcessor H264
OS
HdS2XXX_Init, XXX_Deinit, XXX_Open,
XXX_Close, XXX_Read, XXX_Write,XXX_IOControl, XXX_Init
mem_reqrequest_irqScheduler
âŚ
Boot
OS API Open, Close, Read, Write, IOControl
GStreamer Plug-in CORBA Plug-in âŚ
TS
E
Sensor
Application SW
HdS3 API config, reset, encode
HdS1 - INREG, OUTREG
HdS:The WinCE case
32
SOFTSOC
⢠The HdS structured approachâ Identification of the different componentsâ Maximization of the reusability
⢠OSâ Linux & WinCE are very similarâ Opportunities for HdS standardizationâ Facilitates the development of tools
⢠Simulation,⢠Synthesis,⢠Verification, âŚ
HdS Stack Conclusions
33
SOFTSOC
⢠IP-XACTâ Current IP-XACT is the âlevel 0â layer
⢠Only describes the HW platform
â SoftSoC opens IP-XACT to ânâ levels of abstraction
â Easy identification of IP services at different levels
â Higher level less knowledge of concrete services
HdS Stack Conclusions
34
SOFTSOCPlan
1.HW/SW and SW/SW basic dependencies1.SW Taxonomies2.Case studies3.Basic SW Dependencies Conclusions
2.Layered Hardware-dependant-Software1.Introduction to HdS Stack2.Linux3.WinCE4.HdS Stack Conclusion
3.IP Xact & HdS
SOFTSOC
35
Extensions in IP-XACT for HDS
⢠New schemaâ Structured and standardized electronic documentation
dedicated to HDS structure (layers)â in relation with HW platform in IP-XACT schema (level 0)
⢠Description of SW blocks and structure assemblyâ Dependencies with HW processors, compilers, OS, etc.â Interfaces: SW-SW, inter layers, SW-HW + definition of servicesâ Specificities for HDS1, 2, 3, middleware ?â Views for several implementations
⢠Extensions of existing IP-XACTâ Reference to several driversâ Description of performances (power, timing)â Provided services toward the SW layers (list of standard
services?)
SOFTSOC
36
Solutions and tooling for HDS
Design environment (base on IP-XACT)⢠SW architecture assembly (hierarchical) in a reuse and multi site
context⢠Manage though a comon cockpit the heterogenity of tools, methods
and languages⢠Automate the HW/SW codesign and mapping
Tools and engines⢠Import/export to/from IP-XACT
â UML description of HDL layersâ Doc generation
⢠Design Verificationâ Required services available on HW platform?â Verify the access of HW registers by SW (though buses, bridgesâŚ)
⢠EtcâŚ