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Signal Technologies

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Gunning Transceiver Logic (GTL) Gunning Transceiver Logic (GTL) -- evolutionevolution

Evolved from BTL, the backplane transceiver logic, which in Evolved from BTL, the backplane transceiver logic, which in turn evolved from ECL (emitterturn evolved from ECL (emitter--coupled logic)coupled logic)Setup of an open collector bus system using BTL devicesSetup of an open collector bus system using BTL devices

•• A reduced voltage swingA reduced voltage swing•• An open collector output stageAn open collector output stage•• The falling signal edge is actively generated by the driver and The falling signal edge is actively generated by the driver and rising rising

edge is generated by the passive pulledge is generated by the passive pull--up networkup network•• The resistor R in the passive pullThe resistor R in the passive pull--up network is matched to the up network is matched to the

resistance of the loaded backplaneresistance of the loaded backplane

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Gunning Transceiver Logic Gunning Transceiver Logic Open collector bus system using GTL devicesOpen collector bus system using GTL devices

GTL has a fast edge rate and reduced voltage output levels from GTL has a fast edge rate and reduced voltage output levels from BTLBTLThe GTL driver has an open collector output, but the diode in thThe GTL driver has an open collector output, but the diode in the open e open collector output that is found in BTL is not present in GTLcollector output that is found in BTL is not present in GTLThe receiver as with BTL is designed as a differential amplifierThe receiver as with BTL is designed as a differential amplifier, , guaranteeing stable threshold voltages at the receiverguaranteeing stable threshold voltages at the receiverA pullA pull--up resistor R at the line end is matched to the loaded trace up resistor R at the line end is matched to the loaded trace impedance to avoid line reflectionsimpedance to avoid line reflections

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Gunning Transceiver Logic Plus (GTLP)Gunning Transceiver Logic Plus (GTLP)HighHigh--speed, highspeed, high--performance backplane transceiversperformance backplane transceiversOperate like the GTL family except for two major differences:Operate like the GTL family except for two major differences:•• Optimized with slower edge rates for the distributed loads foundOptimized with slower edge rates for the distributed loads found in in

multimulti--slot backplanes,slot backplanes,•• Supports live insertion applications with internal preSupports live insertion applications with internal pre--charge circuitrycharge circuitry

•• GTLP is commonly designed with two ports, an LVTTL/TTL I/O GTLP is commonly designed with two ports, an LVTTL/TTL I/O which is referred to as the A Port or a GTLP I/O which is referrwhich is referred to as the A Port or a GTLP I/O which is referred to as ed to as the B Portthe B Port

•• Both ports are bidirectionalBoth ports are bidirectional

Simplified partial schematic of a typical GTLP devicesSimplified partial schematic of a typical GTLP devices

to PCBto PCB

to backplaneto backplane

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GTLP Device Features (1)GTLP Device Features (1)Controlled edge ratesControlled edge rates•• Incorporates output edge control (OEC) circuitry to address the Incorporates output edge control (OEC) circuitry to address the

output switching noise problem with highoutput switching noise problem with high--speed devicesspeed devices•• Edge control incorporates waveEdge control incorporates wave--shaping techniques that optimize shaping techniques that optimize

GTLP devices for driving backplanesGTLP devices for driving backplanes•• Control the output level transition to minimize switching noise Control the output level transition to minimize switching noise and and

EM interface and reduce signalEM interface and reduce signal--settling timesettling timeGTLP transition waveformGTLP transition waveform

•• The area of the output transition are addressed by the GTLP outpThe area of the output transition are addressed by the GTLP output ut control circuitrycontrol circuitry

•• The ability to vary rise and fall times allows adjusting for varThe ability to vary rise and fall times allows adjusting for various farious far--end loadsend loads

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GTLP Device Features (2)GTLP Device Features (2)Bushold (A port)Bushold (A port)•• Designed to tolerate floating input conditionsDesigned to tolerate floating input conditions•• hold an undriven datahold an undriven data--bus line in a valid logic statebus line in a valid logic stateSimplified schematic diagram of bushold circuitrySimplified schematic diagram of bushold circuitry

•• Uses a low drive inverters in the device input Uses a low drive inverters in the device input stage that provides feedback to the input of the stage that provides feedback to the input of the device and the busdevice and the bus

•• When the signal driving the input is removed, When the signal driving the input is removed, the inverter will maintain the last received valid the inverter will maintain the last received valid signal level on the device input and bus line until signal level on the device input and bus line until it is overdriven by the next incoming signalit is overdriven by the next incoming signal

VoltageVoltage--in versus currentin versus current--in sweep of bushold devicein sweep of bushold device•• III(HOLD)I(HOLD) is the bushold input minimum drive. is the bushold input minimum drive. This is the minimum amount of current the circuit This is the minimum amount of current the circuit is capable of supplyingis capable of supplying

•• III(OD) I(OD) is the bushold input overis the bushold input over--drive current to drive current to change state. This is the minimum amount of change state. This is the minimum amount of current that is necessary to overcome the bushold current that is necessary to overcome the bushold circuit and cause the input to change statescircuit and cause the input to change states

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GTLP Backplane Design ConsiderationsGTLP Backplane Design ConsiderationsTermination resistor should match the backplane impedance for beTermination resistor should match the backplane impedance for best st signal integritysignal integrityThe impedance is a function of natural trace impedance (ZThe impedance is a function of natural trace impedance (Z00), stub ), stub length, connector impedance, device impedance, and card spacinglength, connector impedance, device impedance, and card spacingCloser spacing reduces the effective impedance and requires a smCloser spacing reduces the effective impedance and requires a smaller aller termination resistortermination resistorRRTT vs. slot spacing with GTLP vs. slot spacing with GTLP

medium and high drive devicesmedium and high drive deviceswaveform with matched vs. overwaveform with matched vs. over--

matched and undermatched and under--matched terminationmatched termination

!!

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GTLP BackplaneGTLP BackplaneTypical GTLP backplaneTypical GTLP backplane

•• The bus is pulled high to the termination voltage (VThe bus is pulled high to the termination voltage (VTTTT=1.5V) through the =1.5V) through the termination resistance (Rtermination resistance (RTTTT=22 Ohm) when the GTLP driver=22 Ohm) when the GTLP driver’’s open drain s open drain output stage is off and pulled low when GTLP driveroutput stage is off and pulled low when GTLP driver’’s open drain output s open drain output stage is onstage is on

•• The advantage of the open drain backplane is that there is no buThe advantage of the open drain backplane is that there is no bus contention, s contention, it is simple to implement and there is less power consumptionit is simple to implement and there is less power consumption

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Low Voltage Differential

Signalling (LVDS)

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IntroductionIntroductionLVDS allows data transmission at hundreds and even LVDS allows data transmission at hundreds and even thousands of megabits per secondthousands of megabits per secondIts low swing and its currentIts low swing and its current--mode driver outputs create mode driver outputs create low noise and provide low power consumption across low noise and provide low power consumption across large range of data rateslarge range of data ratesLVDS drivers can transmit signal over long tracesLVDS drivers can transmit signal over long tracesLVDS devices usually require controlledLVDS devices usually require controlled--impedance impedance circuitcircuit--board traces, connectors, and cables to maintain board traces, connectors, and cables to maintain signal integritysignal integrity

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Scope of LVDS ApplicationsScope of LVDS Applications

•• The highThe high--speed and low power/noise/cost benefits of LVDS speed and low power/noise/cost benefits of LVDS broaden the scope of LVDS applications far beyond those for broaden the scope of LVDS applications far beyond those for traditional technologies. The following table provides some traditional technologies. The following table provides some examples of LVDS applications. examples of LVDS applications.

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LVDS Principle of Operation (1)LVDS Principle of Operation (1)Simplified diagram of an LVDS driver and receiver connected via Simplified diagram of an LVDS driver and receiver connected via 100Ohm 100Ohm differential impedance medium differential impedance medium

(a)(a) Current flowing from Current flowing from the driverthe driver’’s true output s true output down through the down through the 100Ohm termination 100Ohm termination resistor; resistor;

(b)(b) Current flowing from Current flowing from the driverthe driver’’s inverted s inverted output up through the output up through the 100Ohm termination 100Ohm termination resistor resistor

Current source boosts PSRR

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LVDS Principle of Operation (2)LVDS Principle of Operation (2)

•• LVDS outputs consist of a current source (nominal LVDS outputs consist of a current source (nominal 3.5mA) which drives a differential trace or line. The 3.5mA) which drives a differential trace or line. The basic receiver has high dc input impedance, so the basic receiver has high dc input impedance, so the majority of the driver current flows across the 100 Ohm majority of the driver current flows across the 100 Ohm termination resistor, generating about 350mV across the termination resistor, generating about 350mV across the resistor and receiver inputresistor and receiver input

•• When the driver switches, it changes the direction of When the driver switches, it changes the direction of current flow across the resistor, thereby creating a valid current flow across the resistor, thereby creating a valid ““oneone”” or zeroor zero”” logic statelogic state

•• Commutation of a Commutation of a single_current_sourcesingle_current_source current to current to make it flow in both directions gives LVDS power make it flow in both directions gives LVDS power advantageadvantage

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LVDS Principle of Operation (3)LVDS Principle of Operation (3)Voltages generated across the LVDS terminating resistor assumingVoltages generated across the LVDS terminating resistor assuming no losses no losses or distortion over the interconnect between the driver and termior distortion over the interconnect between the driver and terminating resistor nating resistor at the receiver at the receiver

VVODOD: differential output voltage: differential output voltageVVOLOL/V/VOHOH: : ““singlesingle--endedended”” voltages because they voltages because they

are measured with respect to ground are measured with respect to ground VVOSOS: halfway between V: halfway between VOLOL and Vand VOHOH

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LVDS Principle of Operation (4)LVDS Principle of Operation (4)SingleSingle--ended and differential LVDS waveforms generated when switching ended and differential LVDS waveforms generated when switching from high to low and back to high. from high to low and back to high.

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LVDS LVDS Principle of OperationPrinciple of Operation (5)(5)LVDS receivers can tolerate +/LVDS receivers can tolerate +/-- 1V of common1V of common--mode voltage difference mode voltage difference between the driver and receiverbetween the driver and receiver

This is useful in situations where there might be up to 1V ofThis is useful in situations where there might be up to 1V of difference difference between the driversbetween the drivers’’ ground and receiverground and receiver’’s ground due to resistive voltage drops s ground due to resistive voltage drops over long backplane or cable distances, or due to ground potentiover long backplane or cable distances, or due to ground potential variations from al variations from one chassis to anotherone chassis to another

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LVDS Configurations (1)LVDS Configurations (1)PointPoint--toto--point configuration. This provides the best signal quality due tpoint configuration. This provides the best signal quality due to the o the clear path.clear path.

Bidirectional halfBidirectional half--duplex configuration allows bidirectional communication duplex configuration allows bidirectional communication over a single twisted pair. Data can flow in only one direction over a single twisted pair. Data can flow in only one direction at a time. at a time.

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LVDS Configurations (2)LVDS Configurations (2)

MultiMulti--drop configuration connects multiple receivers to a driver. Thidrop configuration connects multiple receivers to a driver. This s configuration is useful in data distribution applications. In thconfiguration is useful in data distribution applications. In this is configuration, stub lengths must be as short as possible, althouconfiguration, stub lengths must be as short as possible, although gh acceptable stub lengths are always dependent upon the applicatioacceptable stub lengths are always dependent upon the application.n.

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LVDS SummaryLVDS Summary

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LVDS Summary LVDS Summary (continued)(continued)

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High-Speed Transceiver Logic (HSTL)

Stub-Series Terminated Logic (SSTL)

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IntroductionIntroduction

HSTL and SSTL families are used primarily forHSTL and SSTL families are used primarily forMemory chip interfacesMemory chip interfacesParallel data in/out interfaces for Parallel data in/out interfaces for SerDesSerDes devices devices

Single ended or differential interfaces that operate at Single ended or differential interfaces that operate at frequencies above 200MHzfrequencies above 200MHz

HSTL accepts minimal input swing from 0.65V to HSTL accepts minimal input swing from 0.65V to 0.85V (nominally) with the output swing typically 0 0.85V (nominally) with the output swing typically 0 to 1.5Vto 1.5V

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Single HSTL Circuit

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HSTL I/O LevelsHSTL I/O Levels

Specification includes both dc and ac levelsSpecification includes both dc and ac levelsDevices switches state after crossing the ac threshold and Devices switches state after crossing the ac threshold and does not switch back as long as the input stays beyond the dc does not switch back as long as the input stays beyond the dc thresholdthreshold

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HSTL Output BuffersHSTL Output Buffers

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SSTLSSTLSSTL are particularly intended for single and Double SSTL are particularly intended for single and Double Data Rate (DDR) SDRAMS and support frequencies Data Rate (DDR) SDRAMS and support frequencies above 333MHzabove 333MHzIdeal for main memory applications with long Ideal for main memory applications with long transmission line stubs due to trace routing of Dual Inline transmission line stubs due to trace routing of Dual Inline Memory Modules (Memory Modules (DIMMsDIMMs) ) Long stubs are isolated from buses using an external stub Long stubs are isolated from buses using an external stub resistorresistor

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SSTL DDR Memory SystemSSTL DDR Memory System

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Emitter Coupled Logic (ECL)

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IntroductionIntroduction

““Emitter coupledEmitter coupled”” refers to the fact that emitters of a refers to the fact that emitters of a driver stage constitute an output connecting to the next driver stage constitute an output connecting to the next stagestageA differential amplifier provides high impedance inputs A differential amplifier provides high impedance inputs and voltage gain with the circuitand voltage gain with the circuitEmitter follower output restores the logic levels and Emitter follower output restores the logic levels and provides low output impedance for strong line driving and provides low output impedance for strong line driving and high fanhigh fan--outoutPositive and negative supply voltages required for Positive and negative supply voltages required for standard ECLstandard ECL

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Applications and UsesApplications and UsesBoardBoard--level applications:level applications:•• Clock and data distribution, backplane transmission, Clock and data distribution, backplane transmission,

multiplexing, translation (voltage level shifting and multiplexing, translation (voltage level shifting and interfacing to other logic families), state machinesinterfacing to other logic families), state machines

System applications:System applications:•• HighHigh--speed test equipment, optical networking speed test equipment, optical networking

equipment, ultra highequipment, ultra high--speed terabit routers, network speed terabit routers, network attached storage devices, OC192 SONET, 10Gigabit attached storage devices, OC192 SONET, 10Gigabit Ethernet, enterprise computing servers, and highEthernet, enterprise computing servers, and high--performance workstationsperformance workstations

Differential uses: Differential uses: •• Clock distribution and interfacingClock distribution and interfacingSingleSingle--ended uses:ended uses:•• Logic circuitsLogic circuits

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Basic Device Operation (1)Basic Device Operation (1)ECL typical emitter follower output, termination and input ECL typical emitter follower output, termination and input

structurestructure

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Basic Device Operation (2)Basic Device Operation (2)Circuit OperationCircuit Operation

•• The driverThe driver’’s output stages are emitter follower circuits. They s output stages are emitter follower circuits. They provide level shifting from the differential amplifier to ECL ouprovide level shifting from the differential amplifier to ECL output tput levels and provide a low output impedance for driving levels and provide a low output impedance for driving transmission linestransmission lines•• The emitter follower outputThe emitter follower output’’s transistors operate in their active s transistors operate in their active regions with dc current flowing at all times. This increases regions with dc current flowing at all times. This increases switching speeds and helps maintain fast turnswitching speeds and helps maintain fast turn--off timesoff times•• The ECL output impedance is low, typically on the order of The ECL output impedance is low, typically on the order of 44--8 Ohm, which provides superior driving capability8 Ohm, which provides superior driving capability•• ECL input circuit is a current switching differential ampliECL input circuit is a current switching differential amplifier fier with high input impedance. In order to provide adequate input with high input impedance. In order to provide adequate input stage headroom, the commonstage headroom, the common--mode voltage is around (Vcc mode voltage is around (Vcc –– 1.3V)1.3V)

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ECL Standards (1)ECL Standards (1)Most ECL family devices adhere to one of two standards, Most ECL family devices adhere to one of two standards,

the 10K standard or the 100K standardthe 10K standard or the 100K standard•• The terms 10K and 100K specify whether the devices The terms 10K and 100K specify whether the devices adhere to the adhere to the ““10K10K”” or the or the ““100K100K”” input and output dc input and output dc electrical characteristics (i.e., the signaling levels)electrical characteristics (i.e., the signaling levels)

Five kinds of ECL family outputsFive kinds of ECL family outputs•• 10K/ 100K dc signaling levels (~800mV)10K/ 100K dc signaling levels (~800mV)•• CML dc signaling levels (~800mV, but also 400mV)CML dc signaling levels (~800mV, but also 400mV)•• Reduced swing output levels (~400, but also 200, 600mV)Reduced swing output levels (~400, but also 200, 600mV)•• VendorVendor--specific variable, adjustable, or selectable output specific variable, adjustable, or selectable output levels (~0 to 800mV)levels (~0 to 800mV)Note: output voltage values listed in parentheses are peakNote: output voltage values listed in parentheses are peak--toto--peak differential signal voltagespeak differential signal voltages

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ECL Standards (2)ECL Standards (2)10K is not temperature compensated

100K is temperature compensated

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ECL InterfacesECL InterfacesStandard (a) singleStandard (a) single--ended ECL interconnect, (b) differential ECL ended ECL interconnect, (b) differential ECL interconnect, and (c) differential driver with independent singinterconnect, and (c) differential driver with independent singlele--ended receivers ended receivers

A typical ECL circuit interface may be defined as a differentialA typical ECL circuit interface may be defined as a differentialdriver device sending two complementary signals over a pair of driver device sending two complementary signals over a pair of standard, controlled impedance lines to an ECL differential recestandard, controlled impedance lines to an ECL differential receiver iver device, as in (b). device, as in (b).

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Advantages and Disadvantages of Advantages and Disadvantages of Standard InterfaceStandard Interface

•• Advantage of singleAdvantage of single--ended (SE) interconnects are decreased ended (SE) interconnects are decreased board routing and reduced system power demandboard routing and reduced system power demand

•• Disadvantages of SE include higher jitter, phase error, and Disadvantages of SE include higher jitter, phase error, and duty cycle skew, high noise sensitivity, critically narrow duty cycle skew, high noise sensitivity, critically narrow voltage margins, poor receiver sensitivity and higher EMI voltage margins, poor receiver sensitivity and higher EMI emissionemission

•• Differential interconnect advantages include high commonDifferential interconnect advantages include high common--mode noise rejection, wide signal interface windows, high mode noise rejection, wide signal interface windows, high receiver sensitivity and low EMI emissionreceiver sensitivity and low EMI emission

•• Differential interconnect disadvantages include increased Differential interconnect disadvantages include increased board routing and increased system power dissipation board routing and increased system power dissipation

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Differential Interface (1)Differential Interface (1)

Differential signals are used in most ECL interfacing and Differential signals are used in most ECL interfacing and clock distribution applications because of their low skew clock distribution applications because of their low skew and high noise immunityand high noise immunityThe timing of 0The timing of 0--toto--1 or 11 or 1--toto--0 transition does not depend 0 transition does not depend critically on device voltage thresholds which may change critically on device voltage thresholds which may change with temperature or between deviceswith temperature or between devicesThe differential definition of logical 0 and 1 provides an The differential definition of logical 0 and 1 provides an outstanding noise immunity, since noise created by outstanding noise immunity, since noise created by power supply variations or coupled from external power supply variations or coupled from external sources tends to be a commonsources tends to be a common--mode signalmode signal

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Differential Interface (2)Differential Interface (2)A standard differential driver signal is characterized by a A standard differential driver signal is characterized by a receivedreceived signal signal swingswingReceiver sensitivity is specified by data sheets as the peakReceiver sensitivity is specified by data sheets as the peak--toto--peak (peak (VppVpp) ) input swing voltageinput swing voltage

Input swing greater than the allowed maximum may cause degraded Input swing greater than the allowed maximum may cause degraded frequency performance and increase the input propagation delayfrequency performance and increase the input propagation delayInput swings less than the specification minimum will cause dimiInput swings less than the specification minimum will cause diminished nished receiver output amplitude and possible errorsreceiver output amplitude and possible errors

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Differential Interface (3)Differential Interface (3)Differential input high noise immunity is illustrated in the folDifferential input high noise immunity is illustrated in the following figurelowing figure

Each input signal to a differential receiver is characterized byEach input signal to a differential receiver is characterized by a Vin high a Vin high voltage (Vvoltage (VIHIH) level and a Vin low voltage (V) level and a Vin low voltage (VILIL). Proper operation is achieved ). Proper operation is achieved when the Vwhen the VIHIH level falls within spec limits, Vlevel falls within spec limits, VIHCMRIHCMR (voltage input high (voltage input high commoncommon--mode range) minimum to maximum mode range) minimum to maximum

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Curent Mode Logic (CML)

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IntroductionIntroduction

CML is ECL technologies that are being implemented in CML is ECL technologies that are being implemented in many of the newest highmany of the newest high--speed devicesspeed devicesCML serial signaling rates typically range from 1Gbps to CML serial signaling rates typically range from 1Gbps to over 10Gbps and higher and the data rate that CML can over 10Gbps and higher and the data rate that CML can support depends upon the manufacturing process support depends upon the manufacturing process technologytechnologyCML applications include: output/input stages of SERDES CML applications include: output/input stages of SERDES transceivers, pointtransceivers, point--toto--point configurations, SDH/SONET point configurations, SDH/SONET transmission equipment, hightransmission equipment, high--speed backplane speed backplane interconnects, highinterconnects, high--speed serial links and othersspeed serial links and others

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CML Output StructureCML Output Structure

•• Consists of a commonConsists of a common--emitter emitter differential transistor pair with 50 Ohm differential transistor pair with 50 Ohm collector resistors, which can supply collector resistors, which can supply source termination when driving 50 source termination when driving 50 Ohm transmission linesOhm transmission lines

•• The driverThe driver’’s constants constant--current sink current sink sinks the same current regardless of the sinks the same current regardless of the load placed upon the outputs or the load placed upon the outputs or the values of pullvalues of pull--ups or termination ups or termination resistors used (within limits)resistors used (within limits)

•• The constant current sink in CML The constant current sink in CML structure creates less switching noise structure creates less switching noise so output rise and fall times of less so output rise and fall times of less than 100ps are possible than 100ps are possible

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CML Input StructureCML Input Structure

•• As shown in this figure, the As shown in this figure, the CML input structure has a internal CML input structure has a internal 50 Ohm input impedance for ease of 50 Ohm input impedance for ease of terminationtermination•• Some devices do not have such Some devices do not have such internal termination resistors and internal termination resistors and allow external termination resistor allow external termination resistor to be used for greater flexibility to be used for greater flexibility

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A CML Specification ExampleA CML Specification ExampleThe table lists key specifications The table lists key specifications

for a typical vendorfor a typical vendor’’s implementations implementation•• VVTRTR and Vand VCPCP specify the singlespecify the single--ended ended true and complement voltage of the true and complement voltage of the driver outputdriver output•• |V|VODOD| is the driver| is the driver’’s differential s differential output voltage magnitudeoutput voltage magnitude•• VVOSOS is the driveris the driver’’s commons common--mode mode voltagevoltage•• RRTT is the termination resistoris the termination resistor•• VVID(min)ID(min) the receiverthe receiver’’s differential s differential input threshold voltage input threshold voltage

Switching levels for a CML Switching levels for a CML 800mV differential output example800mV differential output example

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AC/DCAC/DC––Coupled CML (1)Coupled CML (1)AC AC -- coupled CML circuit with two termination resistor pulled up to coupled CML circuit with two termination resistor pulled up to VVTT

DC DC -- coupled CML circuit with termination resistors pulled up to Vcoupled CML circuit with termination resistors pulled up to VCCCC

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AC/DCAC/DC––Coupled CML (2)Coupled CML (2)DC DC -- coupled CML circuit with all resistors internal to the chips coupled CML circuit with all resistors internal to the chips

DC DC -- coupled CML circuit with opencoupled CML circuit with open--collector drivercollector driver

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AC/DCAC/DC––Coupled CML (3)Coupled CML (3)

•• CML output waveforms for AC and DC coupling (a) ACCML output waveforms for AC and DC coupling (a) AC--coupled, loaded with internal 50 Ohm collector resistor and coupled, loaded with internal 50 Ohm collector resistor and (b) DC(b) DC--coupled, loaded with 25 Ohm equivalent, internal coupled, loaded with 25 Ohm equivalent, internal 50Ohm collector resistor in parallel with 50 Ohm termination 50Ohm collector resistor in parallel with 50 Ohm termination resistorresistor

(a) (a) (b)(b)

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Difference Between CML and ECLDifference Between CML and ECL

•• The main difference between ECL and CML is that ECL The main difference between ECL and CML is that ECL contains emitter follower circuits in the output stage and CML contains emitter follower circuits in the output stage and CML does not. It results in the dc voltage level (commondoes not. It results in the dc voltage level (common--mode dc mode dc voltage) of the ECL outputs to be lower than the CML outputs voltage) of the ECL outputs to be lower than the CML outputs by approximately one diode voltage drop plus another 100mV by approximately one diode voltage drop plus another 100mV to 200mVto 200mV

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Emphasis and EqualizationEmphasis and Equalization

Transmission media generally have a lowTransmission media generally have a low--pass frequency pass frequency response, cause the distortion of signals at receive sideresponse, cause the distortion of signals at receive sideA means of improving the signal quality is to transmit the A means of improving the signal quality is to transmit the highhigh--frequency components with a larger amplitude than the frequency components with a larger amplitude than the lowlow--frequency componentsfrequency componentsOne method by which higher frequencies are amplified One method by which higher frequencies are amplified more prior to transmission is called premore prior to transmission is called pre--emphasis/deemphasis/de--emphasis and sometimes, transmit equalizationemphasis and sometimes, transmit equalizationAmplification of the higher frequencies of a signal can also Amplification of the higher frequencies of a signal can also be done at the receiver to open up the eye of the received be done at the receiver to open up the eye of the received signal. The process is called equalization, or sometime as signal. The process is called equalization, or sometime as receive equalization receive equalization

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PrePre--Emphasis/DeEmphasis/De--Emphasis Emphasis

Driver output voltages plotted as singleDriver output voltages plotted as single--ended and referenced ended and referenced to ground illustrating both preto ground illustrating both pre--emphasis and deemphasis and de--emphasis emphasis

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Adaptive Equalization Example Adaptive Equalization Example Adaptive cable equalizer consists of CML input/output buffer Adaptive cable equalizer consists of CML input/output buffer