GRP Machine Details

Memory

Registers

r11

r0

r1

r2

r3

r4

r10

ALU

..

..

0

8

16

24

32

..

..

Load from Memory

Store to Memory

Load reg from mem

Load reg from mem

Add reg to reg into reg

Store reg in mem

Our programmer

needs to do this !

6. Onto the bus wires as signals

5. Memory stores these as bits

4. Instructions in memory are just numbers

Programs are Numbers

0 65

8 43

16

24

32

0 1 1 0 0 1 0 1

0 1 0 0 0 0 1 1

2. High Level Language

3. Assembler Instructions

load reg from mem add reg to reg into reg

w = x + y

1. Application

Let’s consider a spreadsheet cell which

adds two numbers x + y. This cell and its instruction

is in memory. But it is REPRESENTED in

different ways

Let’s build a Computer

Let’s take a RISC. What do we need ?

• Memory

• Registers

• ALU

• Control Circuits

• A programming language

• A good Name - Simple Although Meaningful

What’s needed to build Sam-4 ?

PC

Code Memory

Code Memory – to store the program

Arithmetic – Logic Unit to do the maths

business

Registers to hold results of computationsX

Y

W

Y

W

r1

r2

r0

X

Data Memory

0

1

7

mar

mdr

Data memory to hold source and results of

our work

Program Memory

PC = 4

12

8

4

0

Code Memory

add

halt

store

load

add

Memory stores program instructions at a sequence of byte addresses. Each instruction is 32 bits, so the addresses increment by 4 bytes.

Here the Program Counter input address 4 to the memory which reads out the data word (32 bits) at address 4. This is the inst- ruction ‘add’

Address in

Data out

Registers, Registers1. Registers Store data at addresses. Yep, that’s Memory !

3. Multiport Registers have an input port (W) where data is send to be written into the register file.

2. There are TWO read ports (X and Y) where data can be simultaneously read out of the reg file.

4. The addresses for the read ports (X and Y) and the write port (W) come in here.

X

Y

W

Y

W

r1

r2

r0

X

Data Memory

0

1

7

mar

mdr

Here’s the memory

The Memory Data Register (MDR) is a parking place for data coming and going from the memory.

The Memory Address Register holds the address of the data location selected for read or write e,g, 7

7

Here’s Sam

Data Memory

Instruction reg

Code Memory

ALU

r1

r2

r0X

Y

W

X Y

W

0

1

7mar

mdr

The Instruction Register

010110 00010 00001 00011 unusedCode Memory

Add r2,r1,r3

add 2 1 3

312

Loaded with the instruction, the IR decodes this into bits which drive the

CPU digital logic circuits

add

Electronic Wires

Instruction Encoding Example

add rd rs rt unused

rd <- rs + rt

e.g. add r3, r1, r2 means r3 = r1 + r2

010110 00011 00010 00001 unused

All Sam’s instructions take up 32 bits.

Sam’s instructions start with the opcode then the destination reg- ister then the source register

opcode

destination

Source regs

First 6 bits for the opcode.

3 2 1

6 5 5 5Nr of Bits 11

Fetch-Execute Cycle

1. Fetch instruction from memory

2. Decode the opcode and read any

registers

3. Do any ALU operations

5. Write back results to registers

add r3,r2,r1

Get contents of address 1

4. Do any Memory Access

ALU <- r1 ALU <- r2

ALU add

None needed

r3 <- ALU

Example

ld r0 , [1]

ld r1 , [2]

add r2,r1,r0

st r2 , [7]

Load r0 with data at address 1

Load r1 with data at address 2

Add r0 and r1. Put result in r2

Store r2 in memory address 7Note each of these instructions

runs through 5 steps of its own F-E Cycle

1. Instruction Fetch

Ld r0,[1]

Code Memory Data

MemoryALU

r1

r2

r0

Ld 0 1

PC = 0

X

Y

W

X Y 0

1

7mar

mdr

2. Decode, Reg Ops

Data Memory

+

Code Memory

ALU

r1

r2

r0Ld r0,[1]

Ld 0 1

PC = 4

1

X

Y

W

X Y 0

1

7mar

mdr

3. ALU Operation

Code Memory Data

MemoryALU

r1

r2

r0Ld r0,[1]

Ld 0 1

PC = 4

1

1

1

X

Y

W

X Y 0

1

7mar

mdr

4. Memory Access

Code Memory Data

MemoryALU

r1

r2

r0Ld r0,[1]

Ld 0 1

PC = 4

1

1

0

7

X

Y

W

X Y 0

1

7mar

mdr

5. Register Write

Code Memory Data

MemoryALU

r1

r2

r0Ld r0,[1]

Ld 0 1

PC = 4

1

0

7

X

Y

W

X Y

mar

mdr

W

1. Instruction Fetch

Data Memory

Code Memory

ALU

r1

r2

r0X

Y

W

X Y

W

0

1

7

add r2,r0,r1

add 2 0 1

PC = 4 mar

mdr

PC = 8

2. Decode, Reg Ops

Y

Data Memory

+

Code Memory

ALU

r1

r2

r0X

W

X Y

W

0

1

7

add r2,r0,r1

add 2 0 1

mar

mdr

3. ALU Operation

Data Memory

Code Memory

ALU

r1

r2

r0X

Y

W

X Y

W

0

1

7

add r2,r0,r1

add 2 0 1

PC = 8 mar

mdr

4. Memory Access

Data Memory

Code Memory

ALU

r1

r2

r0X

Y

W

X Y

W

0

1

7

add r2,r0,r1

add 2 0 1

PC = 8 mar

mdr

5. Register Write

W

Data Memory

Code Memory

ALU

r1

r2

r0X

Y

W

X Y 0

1

7

add r2,r0,r1

add 2 0 1

PC = 8 mar

mdr

Control Path

001010 00010 00001 00011 unused

000101 00010 00001 00011 unused

add r2, r1, r3

sub r2, r1, r3

ALU

ALU

+

+

-

-

The add instruction is decoded and produces digital signals which select the + function in the ALU

Add !

Subtract !

The sub function decoded produces different digital signals

r1 r3

r1 r3

Sam and MIPS are 32 bit

001010 00110 01001 00011 unused

001010 101001111110010101011011111

001010 00010 00001 0101001111111011

opcode rd rs rt unused

opcode rd rs 16-bit address

add rd,rs,rt

ldr rd,[rs+c]

ldr rd,[c]

opcode 26-bit address

32 bits wide

Other Arithmetic Instructions

sub rd rs rt unused

rd <- rs - rtopcode

destination

Source regs

Same coding applies to other arithmetic instructions

sub r3,r2,r1 and r2,r1,r0 or r5,r1,r2

6 5 5 5Nr of Bits

unused

A simple ‘Load’ instruction‘Load into rd the contents of memory at address which is in reg rs.’ Simple!

7

696

2315

1154

1453

2

1

0

ldr r9 , [r1]

3145r9

145

rsrdld

opcodedestination

Single source reg

1. Let’s say have already

loaded r1 with 3

2. Get data from mem at addr r1

(=3)

2. Load the data into r9

memory

A more complex ‘Load’

constant crsrdldr

opcodedestination

Source

Load register rd with the contents of memory which you find at address r1 + c.

7

696

2315

1154

1453

2

1

0

ldr r9 , [r1 + 2]

3 + 2

5

231r9

231

The mem

address is

formed as a sum

memory

… and a ‘Store’ instruction

constant crsrdstr

opcode destination

Source

Note here the data is moved from destination to store. Confusing? Mm.

7

696

1965

1154

1453

2

1

0

str r9 , [ r1 + 2 ]

3 + 2

5

196r9

196

1. Get data from r1

2. Write it to memory

What’s this?

‘Load Immediate’

Constant Crdldi

opcodedestination

In load immediate we get the constant C immediately following the opcode into the reg.

ldi r9 , 5

5

5r9

All reference to memory has gone!

Load ‘5’ straight into r9

A Summary So Far …

Example

add r3,r1,r1add rd,rs,rt

str r6,[r1 + 1]str rd, [rs + c]

str r0, [r1]st rd, [rs]

ldr r2,[r3 + 4]ldr rd, [rs + c]

ldr r2,[4]ld rd, [rs]

ldi r0,3ldi rd,C

Now it’s time to move on and look in detail at the hierarchy of computer languages – to see the influence

on the ISA.

Electronics

Assembling a Spreadsheet

ld r0, [ g ]

ld r1, [ h ]

add r2,r0,r1

st r2, [ f ]

Main() {

int f,g,h;

f = g + h;

}

Excel Applicatio

n

HLL Imple-mentation

ISA Assembler

The Great Idea here is that the ISA we need at

the bottom must serve the grand master at the

top, the Application.

The ISA must support the HLL implementation

Arrays (= Tables)

How do we sum the array of numbers in column B?

1. We would use the instruction ld r1,[r0 + B] where B=3, the start address of the array

2. Then we load r0 with 0 then 1, then 2, … to scan down the array

Ld r0 , 0

Ld r3 , 0

Ld r1, [r0 + 3]

r0 (=0) +3 = 3

Arrays (= Tables)

How do we sum the array of numbers in column B?

Inc r0

Ld r1, [r0 + 3]

add r3,r3,r1

Get next cell, lad its value and add it

to the sum, in r3

1. Increment r1 to get the next data value inc r1 (0 + 1 = 1)

2. ld r2,[r0 + B] where B=3, the start address of the array but now r- contains 0

Making Decisions

if(c == 10) b = b + 2;

Let’s say we want to add 2 to a number B if

another number C is equal to 10

You mean, ‘If C = 10, then add 2

to B’

Yep

Here’s how we would do

it in C…

addi r3,r3,2

bne r2,r1,36

…

…

ldi r1,10

36

32

28

24

20

16

Branch around the

addBranch if not equal r1 r2 to addr 36

What about SAM?

First load the test number

10

Loops

ldi r2 , 0

ldi r1 , 4

ldi r0 , 0

8

4

0

bne r0,r1,12

addi r0 , r0 , 1

addi r2 , r2 , 3

20

16

12

Let’s say we want to make the sequence 0,3,6,9,12 and stop.

0

1

2

3

4

0

3

6

9

12

We take 4 steps and each step add

3 x = x + 3

So we need a register to

keep track of the number of steps (r0)

And a register to hold the

sum at each step

r0 r2Branch

unless r0 = r1 = 4

Accumulator Architecure

Memory

ALU

..

..

0

8

16

24

32

..

..

Get 3 from Memory and ADD !

2

4

8

1. Assume 8 is already in the accumulator. The programmer writes

Accumulator

3

8 Add 3

2. The ALU does 3 + 8 = 11 and writes the result back into the accumulator

3