Faults and fault effects in NMOScircuits—impact on design for testability

N. Burgess, B.Sc, M.Sc, A.M.I.E.E., R.I. Damper, M.Sc, Ph.D., D.I.C.,C.Eng., M.I.E.E., M.lnst.P., S.J. Shaw, B.A., M.Sc, A.M.I.E.E.,

and D.R.J. Wilkins, B.Sc, C.Eng., M.I.E.E.

Indexing terms: Circuit theory and design, Modelling, Semiconductor devices and materials, Simulation, Verylarge-scale integration

Abstract: VLSI circuits currently being designed are so complex that it is now extremely difficult to test themadequately to determine whether or not they have been processed correctly. Design for testability (DFT) tech-niques are often used in an attempt to ease this problem by identifying and redesigning potentially 'difficult-to-test' parts of the circuits. The 'testability' of the circuit is usually evaluated in terms of the stuck-at fault model.However, there have been growing doubts over the ability of this model to cover certain common faults thatcan occur in MOS processing (at present, the dominant VLSI technology). The paper describes software simula-tions of faults in simple NMOS logic circuits showing that not all fault effects in NMOS circuits are modellableas 'stuck' nodes. An improved fault model which would better reflect MOS fault effects has yet to be defined.Until such an improved model is available, DFT rules for MOS circuits are best regarded as provisional. Wetherefore conclude with a discussion of ad hoc 'physical design for testability' techniques that exploit currentunderstanding of the relation between MOS faults and their fault effects.

1 Introduction

Recent developments in silicon processing technology haveresulted in the integration of complex systems onto singlechips (for example, 32-bit microprocessors, 1 Mbit RAM).However, the problem of determining whether or not thechips have been correctly manufactured is now proving tobe so difficult that design for testability (DFT) is beginningto be used to assist VLSI testing [1]. Obviously, DFTshould take into account the ways in which the chip canfail, but VLSI failure modes are not yet fully understood.Therefore, design for testability techniques generally con-sider widely understood but physically unrealistic 'stuck-at' faults only. 'Hard-to-test' stuck-at faults are presumedto present potential testing difficulties, which are avoided,as far as possible, by redesigning parts of the chip. It isinstructive therefore to consider the origins and sub-sequent use of the stuck-at fault model for logic testing, asthis clarifies the relationship between it and the faults thatcan occur in modern VLSI chips.

The stuck-at fault model [2] was originally proposed asa means by which logic circuits could be tested without theneed to apply every possible input (so-called exhaustivetesting). The model postulated that, in the presence of afault, one logic variable would become permanently 'stuck-at-1' or 'stuck-at-0'. The test input sequence could then bereadily generated so that each test vector would producea functionally incorrect output value should the nodeunder test be 'stuck'. Furthermore, the input sequencecould be evaluated for effectiveness ('fault coverage') bydetermining the percentage of stuck-at faults tested for bythe sequence.

Although the stuck-at fault model most readily model-led faulty electromagnetic relay armatures that hadbecome permanently stuck, the model proved to be bothefficient and cost-effective for testing logic circuits made upof discrete components mounted on a PCB. The com-ponents (transistors, diodes, resistors) would be tested indi-vidually before assembly, and the board checked for

Paper 3763G (E10, El, E3), first received 3rd September 1984 and in revised form22nd January 1985

Mr. Burgess and Dr. Damper are with the Department of Electronics & Informa-tion Engineering, University of Southampton, Southampton SO9 5NH, UnitedKingdom, and Mr. Shaw and Mr. Wilkins are with the British Telecom ResearchLaboratories, Martlesham Heath, Ipswich IP5 7RE, United Kingdom

connectivity. The assembled board would then betested in the almost certain knowledge that any faults onthe board would have been introduced by the assemblyprocess. In this way, the logic circuit could be adequatelytested using a test input sequence whose length was con-siderably less than that of an exhaustive test set. Thestuck-at fault model was successful in this application fortwo main reasons:

(i) Several assembly-related faults did produce stucknodes; for example, a solder splash bridging a track to apower rail, a floating input to a DTL gate ('stuck-at-1'), ora shorted-output transistor in a DTL gate ('stuck-at-0')

(ii) Other faults (broken leads, components inserted withwrong orientation) would have such catastrophic effectsthat any test sequence would be almost certain to uncoverthem.

Furthermore, the stuck-at fault model still proved to beadequate when SSI and MSI TTL integrated circuitsbecame available, provided that tests for bridging faults[3] on both the board and the chips were included in thetest sequences. (As with DTL circuits, a floating input to aTTL circuit is effectively a 'stuck-at-1' node, and an outputtransistor open-circuit will also produce a stuck node.) Thestuck-at fault model thus became widely used as it wasconceptually simple, reflected many of the possible failuresin logic circuits and, when Roth [4] developed the D-algorithm, formed the basis of many automatic testing-related activities.

Major testing problems have arisen, however, with theadvent of VLSI technology:

(a) Testing may not be performed in stages because theindividual components and their interconnections are nowintegrated on a single chip

(b) Access to the components on the chip has beengreatly reduced as a result of the limited pin-out, andbecause one component is often only accessible via asecond component

(c) The physical faults that can occur on-chip are quitedifferent from the faults introduced by PCB assembly, asthey derive from new integrated circuit processing tech-niques, and are not fully understood.

In the absence of a detailed understanding of the waysin which VLSI circuits can fail, many manufacturers arecontinuing to use testing procedures derived from the

82 IEE PROCEEDINGS, Vol. 132, Pt. G, No. 3, JUNE 1985

stuck-at fault model without any guarantee that they arevalid for the new technology. In particular, the appropri-ateness of the stuck-at fault model for MOS VLSI circuittesting is being called into question for two interrelatedreasons:

(i) The stuck-at model operates on the gate-level rep-resentation of a circuit, which is not topologically equiva-lent to the layout of the circuit in silicon

(ii) There is no reason to expect that the majority of thepossible physical faults on a silicon chip will produce stucknodes on an equivalent gate-level schematic diagram.

The following example illustrates these points [5]. Fig. 1shows an NMOS circuit implementing the logic function

OD

Z = (A*B)(C*D)

Fig. 1 Example of an NMOS circuit containing a fault that does notproduce a stuck-node fault-effect

Z' = (A + B){C + D). Only two test input vectors(ABCD = 0110 and 1001) would detect m open circuit as aresult of an incorrect logic value appearing on the outputnode. However, the two vectors 1010 and 0101 coverexactly the same stuck node faults on the gate-level rep-resentation as the test vectors 0110 and 1001. There is noway of deciding, from examination of the gate diagramalone, which pair of test vectors will in fact uncover mopen circuit. (This kind of fault is sometimes referred to as'alteration of logic function'.) The problem is that the gate-level diagram has obscured the paths that actually exist inthe transistor layout. Thus a real fault on the chip may notbe readily inserted in the gate-level diagram, the level ofabstraction at which the stuck-at fault model operates,either as a stuck fault or as an interconnection fault (openor short circuit).

2 Investigation of faults and fault effects in NMOScircuits

2.1 Faults in NMOS circuitsTo date, the logical fault effects of physical failures inMOS chips have received little attention. This is partly dueto the difficulties of failure analysis and the availability ofsuitable test structures on which to perform this work, andpartly because silicon chip processing and logic circuittesting have traditionally been perceived as being unre-lated activities. Galiay et al. [6] and Banerjee and

Abraham [7] have, however, performed important investi-gations into the relationship between faults in MOS cir-cuits and their associated logical fault effects. Their workhas shown that common MOS faults exist that canproduce faulty behaviour not modellable as stuck nodeson a gate diagram. However, neither of these pieces ofwork considers all the reported common MOS faults, par-ticularly those that affect the behaviour of the MOSFETsthemselves.

The following list of MOS faults was drawn up afterperforming an extensive literature survey, and after dis-cussions with process and reliability engineers at BritishTelecom and the University of Southampton [8]:

(a) Open and short circuits (more correctly, abnormallyhigh and low ohmic resistances, respectively) in the layersof interconnect, and excessively high resistance contactwindows

(b) Excessive drain/source-substrate reverse diodeleakage currents

(c) Large threshold voltage shifts(d) Transconductance degradations(e) Gate oxide breakdowns(/) Excessive subthreshold leakage currents(g) Device length and width variations.

Each of these faults may occur randomly across a chip,owing to localised physical or chemical phenomena (e.g.dirt on wafer surface, substrate imperfections etc.) Further-more, the relative incidences of these faults vary widelywith manufacturer, circuit complexity and type, and pro-cessing technology (wet or dry etching etc.). Nevertheless,all the listed faults are commonly found in MOS VLSIcircuits, and all are likely to be present in any one manu-facturer's chips. A means of inserting these faults into anMOS VLSI circuit now had to be found, so that the effectsof these analogue faults on the operation of a digital MOScircuit could be investigated.

2.2 Fault insertion in NMOS circuitsThe faults were inserted into an NMOS circuit on a soft-ware simulator, rather than by introducing them onto anLSI component directly. This approach was taken becauseof the difficulty of introducing faults into an LSI com-ponent in a controlled manner during the processing of thechip. In addition, a circuit simulator more accuratelymodels on-chip MOSFET behaviour than a circuit madeup of discrete components could ever do, because of theenormous differences between the characteristics(transconductance, substrate currents etc.) of discrete andintegrated components.

The SPICE circuit simulator [9] was chosen—eventhough it was not originally designed to simulate faultydevices—for the following reasons:

(i) Functional- and logic-level simulators operate at toohigh a level, i.e. they do not have the facility to specify theabove set of faults at the required analogue circuit level

(ii) A set of SPICE parameters describing a 3 ^mprocess was readily available from other work at theBritish Telecom Research Laboratories

(iii) SPICE is widely used throughout industry, and isnowadays a recognised standard.

The faults were inserted singly into a chain of six inver-ters, and DC and transient analyses were subsequently per-formed on the chain. The chain length was set at six fortwo reasons:

(1) Using SPICE's transient analysis facility, it proved tobe very difficult to specify accurately an input waveform tothe faulty inverter that exactly matched a fault-free inver-

1EE PROCEEDINGS, Vol. 132, Pt. G, No. 3, JUNE 1985 83

ter's output waveform. In the event, a step input (with zerorise-time) was applied to the chain and the fault was insert-ed into the first inverter in the chain whose fault-freeoutput waveforms exactly matched its predecessor's outputwaveforms. This turned out to be the fourth inverter in thechain

(2) Two inverters followed the faulty inverter in thechain, so that the impact of the fault on a following inver-ter that was itself driving an inverter could be evaluated ifnecessary.

The faults were inserted either by adjusting one of theSPICE MOSFET model parameters, or by adding anextra component (see Table 1).

Table 1 : Fault insertion using SPICE

Fault Means of insertion

1 Open and short circuits etc.

2 Drain/source-substrateleakage current

3 Threshold voltage shift4 Transconductance degradation5 Gate oxide breakdown

6 Subthreshold leakage current7 Width and length variation

Resistor connected ontoMOSFET terminalsSPICE parameter JS

SPICE parameter VTOSPICE parameter KPResistor connectedbetween MOSFETterminalsSPICE parameter ETASPICE parameters W and L

Care was needed in choosing the appropriate modelparameter because some parameters are used more thanonce within SPICE to model separate effects in theMOSFET. Furthermore, if certain parameter values areuser-specified, other non-user-specified parameter valuesmay be recalculated by the software and used to overwritethe expected default values. To check these points, fault 3was simulated a second time by placing a voltage sourceon the MOSFET gate terminal. No appreciable differencesbetween the two sets of simulations were found. Fault 2was also simulated a second time by connecting diodesbetween the substrate terminal and the source and drainterminals. Differences were noticed in this case becauseSPICE models the reverse leakage current as a lineardependence on the applied voltage, rather than using theclassical diode equation. Since the former equation moreclosely models results obtained from experiments than the

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latter equation [10], the parameter JS was used to simu-late this fault. The particular values of resistance, thresholdvoltage, leakage current etc. chosen for the simulations arenot significant in terms of device physics, but were chosento cover a wide range of abnormal behaviour, often up tothe occurrence of a stuck-at fault effect.

The gate propagation delay and the high and low noisemargins were used to investigate the fault effects. Thevoltage at which a normal inverter's input and output volt-ages were identical was defined as VlNV. The propagationdelay was then defined as the time between VINV beingapplied to the inverter and V[NV appearing at the output(Fig. 2a). The two points on the transfer characteristicwhere the slope equalled — 1 were used to define the par-ameters VOH, VOL, VIH and VIL, which, in turn, defined thehigh and low noise margins (Fig. 2b). The high noisemargin was defined as {VOH — VIH) and the low noisemargin as (VIL- V0L).

These figures of merit (propagation delay and noisemargins) were chosen because they represent concepts fam-iliar to digital design engineers, and thus a 'feel' for thefault effects may be readily obtained. However, these defi-nitions of the noise margins in terms of the slope valuesand the propagation delay in terms of VINV are rather arbi-trary. This means that, in the final analysis, the precisevalues of the 'figures of merit' under fault conditions areless important than the gross changes in inverter behav-iour, reflecting the fault effects.

2.3 ResultsFig. 3 shows typical results of the simulations, selected tohighlight important trends. In the presence of a fault, oneor both of the chosen figures of merit tends to deviate fromnormal values; propagation delays are, for the most part,increased, and the output voltage levels are shifted,resulting in at least one of the noise margins beingdecreased. The magnitude of these effects depends, asexpected, on the severity of the fault. In extreme cases, thefault effects usually manifest themselves as stuck nodes.For example, the depletion transistor drain- VDD power railcontact window failure displays both voltage shifts (Fig.3d) and dramatically increased propagation delays (Fig.3b), whereas the reverse diode leakage failure produces amuch lower VOH (Fig. 3e) and little alteration in the propa-gation delay (Fig. 3g). Conversely, the buried contact

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84

Fig. 2 Derivation of figures of merit from a fault-free inverter's transfercharacteristica Transfer characteristic b High and low noise margins

IEE PROCEEDINGS, Vol. 132, Pt. G, No. 3, JUNE 1985

5

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free I SPICE parameter ETA | SPICE parameter JSs subthreshold source-drain reverse diode leakage

leakage enhancement deviceenhancement device

IEE PROCEEDINGS, Vol. 132, Pt. G, No. 3, JUNE 1985 85

1000

600

300

100

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TB.TR. 'F

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Fig. 3 Noise margins and propagation delays calculated from SPICEsimulations of faulty invertersTR and TF indicate rising and falling outputs, respectively

failure (Fig. 3/) produces no change in the DC character-istics of the inverter, but increases the 0—> 1 propagationdelay enormously. For more complete results, see Burgessetal. [11].

The question now arises: are these fault effects physi-cally realistic and representative of failures in real NMOScircuits? In an attempt to answer this, we examined failedintegrated circuits from the University of Southampton'sown silicon processing facility. Test chips ('drop-ins') areincluded on every wafer processed in the facility tomonitor the processing. The NMOS drop-ins containcontact chains, Van der Pauw sheet resistance tests, indi-vidual transistors, isolation and continuity tests for the dif-ferent conducting layers, and minimum geometry inverters.

Some of the faulty inverter transfer characteristicsobtained from the drop-ins are shown in Fig. 4. Resultsfrom the SPICE simulations that closely match the drop-incharacteristics have been superimposed on the same dia-grams. It is, of course, impossible to determine from thedrop-in transfer characteristics the faults present in theinverters. However, subsequent investigation of the drop-incircuits using a transistor curve tracer confirms that thesame fault mechanism is indeed implicated in both. Thusthe simulations presented above can be considered realis-tic, and nonstuck faults are confirmed as forming a signifi-cant subset of all failures.

3 Impact on design for testability

Design for testability techniques currently employed toease the problems of testing VLSI circuits typically use thestuck-at fault model to identify nodes on a chip under testthat are likely to prove 'hard to test'. Areas of the chip thatcontain any such hard-to-test nodes may then beredesigned so that the effort (man/computer hours) neededto test the circuit is reduced. However, our work hasshown that not all MOS faults produce stuck nodes, andthus current design for testability activities cannot beexpected to identify and remove all the hard-to-test faultsthat can occur in MOS VLSI circuits.

To date, our work has identified three areas of concern:(i) timing degradations, (ii) noise sensitivity problems and(iii) short circuits (bridging faults) and open circuits.

Clearly, however, there may be other areas of concern

that this work has not identified, because the figures ofmerit chosen to evaluate the fault effects do not cover allpossibilities. Further consideration is given to this point inSection 4.

We shall now discuss the essentially ad hoc techniquesto make MOS VLSI circuits more testable. These tech-niques aim to increase the testability of a circuit, either byreducing the probability of nonstuck faults occurring or bytrying to ensure that potentially nonstuck faults onlymanifest themselves as stuck nodes.

Timing analysis of LSI circuits has long been recognisedas difficult [12], even without taking into account thetiming degradations introduced by faults in the chip. Forthis reason there has been a trend towards the use of syn-chronous circuit design techniques for VLSI circuits. Suchdesign techniques will also aid testing [13], as slow-to-switch nodes should manifest themselves as stuck nodes,because the well defined clock phases limit the time avail-able for switching to occur.

A node that has been made noise-sensitive as a result ofa fault in a chip is likely to display an 'intermittent' faulteffect: sometimes the node will switch correctly, while atother times it will not. A node that is 'floating' as a resultof an open circuit will also be susceptible to this kind offault effect, as it may be controlled by signal pickup froman adjacent track. This problem has been studied for afault-tolerant train controller chip where the designerswanted to be sure that only stuck node faults could occur[14]. Simulations of parallel wires—one floating and onecarrying a signal—were performed, and the designersfound that, if parallel wires were at least two track pitchesapart, then a transition on one track would not cause thefloating node to switch. Noise injection from the powerrails is also a recognised problem [15], and so the separa-tion between ordinary signal-carrying tracks and thepower rails ought perhaps to be larger than currentlyaccepted design rules suggest.

Increasing the separation between adjacent paralleltracks on the same layer of interconnect will also decreasethe likelihood of those two tracks shorting together, andproducing a nonstuck fault. One way of preventing shortcircuits between tracks on different layers of interconnect isshown in Fig. 5, where the oxide isolation is put down intwo stages. This prevents defects (pinholes etc.) in one or

86 IEE PROCEEDINGS, Vol. 132, Pt. G, No. 3, JUNE 1985

other of the oxide layers from shorting different layers ofinterconnect together.

never be pulled to ground. Although Figs. 1 and 6 are elec-trically identical in fault-free conditions, under potentially

. 3 "

1 -

1 -

Fig. 4 Comparison of simulation results with faulty inverter character-istics obtained from the University of Southampton's silicon processingfacility

drop-inSPICE

a Excessively high source contact window resistanceb Increase in leakage current to substrate (SPICE parameter JS increased)c Increase in threshold voltage of enhancement transistor (SPICE parameter VTOincreased)d Increase in source-drain leakage current in the enhancement mode transistor(SPICE parameter ETA)

The problems caused by the open circuit shown in Fig.1 may be resolved by laying out the circuit slightly differ-ently, as shown in Fig. 6. Now, open circuits a-d may bemodelled as input stuck-at-Os, since they permanently dis-connect the relevant transistor either from ground or fromthe output node Z. Similarly, open circuit e may be modelled as node Z stuck-at-1, because the output node can

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Fig. 5 Elimination of short circuits between different layers ofinterconnect

1EE PROCEEDINGS, Vol. 132, Pt. G, No. 3, JUNE 1985

V : . . V

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faulty conditions a piece of interconnect effectively becomesa component, since the topology of the circuit has gainedcritical importance. This technique of laying a circuit outto avoid faults that are 'hard to test' because they do notexhibit stuck nodes is called 'physical design for testability'[16]. A set of rules needs to be developed to prevent thesehard-to-test faults from occurring, thus making MOS cir-cuits more testable, by ensuring that the stuck-at faultmodel retains its validity for MOS circuit testing.

Recently, Tamir and Sequin [17] have performed thiskind of analysis for the possible faults in a PLA, and havedeveloped a set of layout rules that ensures that totallyself-checking two-rail checkers implemented as PLAsremain self-checking in the presence of common MOSfaults. These rules include increasing the spacing betweenadjacent lines, and increasing the size of pull-down tran-sistors, to ensure that bridging faults may be modelled aswired-AND functions, thus avoiding intermittent faults.

4 Future work

Before a more rigorous investigation into the area ofphysical design for testability can be undertaken, morework on the relationship between faults and fault effects inMOS VLSI circuits needs to be done.

87

Firstly, larger, more complex circuits than a string ofinverters need to be studied, so that the effects of bridging

DD

Fig. 6 Example of an NMOS circuit laid out so that open circuits a-eare modellable as stuck nodes

faults between adjacent signal-carrying paths and of singlenoncatastrophic faults on a large circuit may be studied.Furthermore, pass transistors are widely used in NMOScircuits to simplify and reduce the size of NMOS VLSIcircuits; however, since pass transistors introduce voltagedegradations into a circuit even under fault-free condi-tions, they are certain to exacerbate the fault effectsdescribed in this paper. Therefore, simulations to evaluateeffects in circuits containing pass transistors also need tobe performed. Secondly, the effects of fan-in/fan-out and oftemperature on the fault effects should be examined.Thirdly, the use of a single resistor to model contactwindow failures is possibly oversimplified, as results fromthe drop-ins at Southampton suggest that contactwindows fail in the following ways:

(a) High resistance (maximum of approximately 15-20 kQ, but also displaying capacitance effects)

(b) Open circuit (also showing capacitance effects)(c) Rectifying behaviour [18].

Thus, additional simulations should be performed thatmore accurately reflect the ways in which contact windowsfail. Fourthly, experience shows that reducing a chip'spower supply voltage uncovers faulty behaviour not seenat normal supply voltage levels [19]. The precise effects oflowering the power supply voltage on a circuit's behaviourshould therefore be investigated to see if and how thereduction in supply voltage converts nonstuck-node faulteffects into stuck fault effects in a circuit. Preliminaryresults of this work are shown in Fig. 7 for VDD = 4.3 V forboth a 'nearly stuck-at-0' inverter and a 'nearly stuck-at-l'inverter. Only VOH of the 'nearly stuck-at-l' device isaffected by the change in VDD, and the transfer character-istics of the 'nearly stuck-at-0' device remains more or lessunchanged. The reason for this is that the depletion modeload transistor saturates once VDS across it exceeds 2 V. If

Vout < 2.3 V, the transistor is saturated for both normaland reduced values of VDD, resulting in all but identical

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transfer characteristics for the two values. It is not imme-diately clear from these results how reducing the powersupply voltage induces faulty (if not stuck node) behaviourin a circuit. Therefore transient analyses and further DCanalyses need to be performed before this effect is properlyunderstood. Finally, the work to date has been done onstatic NMOS; the faults described above will be present innewer MOS VLSI technologies (dynamic NMOS, staticand clocked CMOS, and domino and n — p CMOS).However, the fault effects may well be different from thosefound in static NMOS circuits because of the differentcircuit components and layouts that are used in the newertechnologies. These fault effects will need to be determinedif physical design for testability rules for these new MOSVLSI technologies are to be found.

5 Acknowledgments

The work described here was supported by the UKScience & Engineering Research Council in collaborationwith British Telecom. We are grateful to the Director ofResearch, British Telecom for permission to publish this

IEE PROCEEDINGS, Vol. 132, Pt. G, No. 3, JUNE 1985

paper. We also acknowledge the permission of Prof. H.A.Kemhadjian and Mr. C.M.K. Starbuck of the Departmentof Electronics and Information Engineering, University ofSouthampton to publish the drop-in data included in Fig.4. Finally, we express our gratitude to Prof. G.T. Wright ofthe Department of Electronic & Electrical Engineering,University of Birmingham, and to Dr. CM. Dyson, Stan-dard Telecommunication Laboratories, Harlow for valu-able advice on fault simulation using SPICE.

6 References

1 WILLIAMS, T.W., and PARKER, K.P.: 'Design for testability—asurvey', Proc. IEEE, 1983, 71, pp. 98-112

2 ELDRED, R.D.: 'Test routines based on symbolic logic statements',J. Assoc. Comput. Much., 1959, 6, pp. 33-36

3 MEI, K.C.Y.: 'Bridging and stuck-at faults', IEEE Trans., 1974,TC-23, pp. 720-727

4 ROTH, J.P.: 'Diagnosis of automata failures: a calculus and amethod', IBM J. Res. & Dev., 1966,10, pp. 278-281

5 COURTOIS, B.: 'Failure mechanisms, fault hypotheses, and analyti-cal testing of MOS LSI circuits', in GRAY, J.P. (Ed.): 'VLSI 81'(Academic Press, 1981), pp. 341-345

6 GALIAY, J., CROUZET, Y., and VERGNIAULT, M.: 'Physical vs.logical fault models for MOS LSI circuits: impact on their testability',IEEE Trans., 1980, TC-29, pp. 527-531

7 BANERJEE, P., and ABRAHAM, J.A.: 'Generating tests for physicalfailures in MOS logic circuits'. Proceedings of IEEE test conference,1983, pp. 554-559

8 BURGESS, N., and DAMPER, R.I.: 'The inadequacy of the stuck-atfault model for testing MOS LSI circuits: a review of MOS failure

mechanisms and some implications for computer-aided design andtest of MOS LSI circuits', Software & Microsystems, 1984, 3, (2), pp.30-36

9 VLADIMIRESCU, A., and LIU, S.: 'The simulation of MOS integ-rated circuits using SPICE2'. ERL memorandum, University of Cali-fornia, Berkeley, February 1980

10 LYCOUDES, N.E., and CHILDERS, C.C.: 'Semiconductor instabil-ity failure mechanisms review', IEEE Trans., 1980, TR-29, pp.237-248

11 BURGESS, N , WILKINS, D.R.J., DAMPER, R.I., and SHAW, S.J.:'Fault effects in MOS circuits and their implications for digital circuittesting', IEE Conf. Publ. 232, 1984, pp. 83-91

12 BENING, L.C., LANE, T.A., and SMITH, J.E.: 'Developments inlogic network path delay analysis'. Proceedings of 19th IEEE designautomation conference, 1982, pp. 605-615

13 GRIERSON, J.R.: 'Gate arrays—computer aids, automation and theUK5000', IEE Conf. Publ. 232, 1984, pp. 1-4

14 MASUDA, I., UENO, M., and TASHIRO, K.: 'A fault-tolerantMOS-LSI for train controller applications'. IEEE ISSCC digest oftechnical papers, 1983, pp. 138-139

15 LI, R.Y., DIEHL, S.C., and HARRISON, S.: 'Power supply noisetesting of VLSI chips'. Proceedings of IEEE test conference, 1983, pp.366-369

16 EL-ZIQ, Y.: 'Classifying, testing and eliminating VLSI MOS failuremodes', VLSI Des., 1983,4, pp. 30-35

17 TAMIL, Y., and SEQUIN, C.H.: 'Design and application of self-testing comparators implemented with MOS PLAs', IEEE Trans.,1984, TC-33, pp. 493-506

18 VIEUJOT-TESTAMALE, E., PALAU, J.M., ISMAIL, A., and LAS-SABATERE, L.: 'Properties of the contact on ion cleaned n- andp-type silicon surfaces', Solid-State Electron., 1983, 26, pp. 325-331

19 HUNGER, A., and GAERTNER, A.: 'Functional characterisation ofmicroprocessors'. Proceedings of IEEE test conference, 1984 (to bepublished)

N. Burgess received his B.Sc. in physics/music from Keele University in 1980, andhis M.Sc. in electronics from the Universityof Southampton in 1982. He is currentlyworking for his Ph.D. on faults and faultmodels for MOS logic circuits at the Uni-versity of Southampton, and will completethe project in the summer of 1985. Hisother research interests include design fortestability, VLSI design and fault-tolerantcomputing.

S.J. Shaw obtained his first degree in com-puter and communication engineering fromthe University of Essex in 1971, and anM.Sc. degree in digital system design fromthe University of Aston in Birmingham in1973. He joined the Development Depart-ment of the then Post Office and workedon System X development, withresponsibility for ensuring testability andmaintainability. In 1981 he moved to theBritish Telecom Research Laboratories and

became involved with test generation for BTRL's custom LSIdevices.

R.I. Damper holds an M.Sc. in physics anda Ph.D. in electrical engineering, both fromthe University of London. At present he isa lecturer in electronics at the University ofSouthampton. He has wide researchinterests, including microprocessor-basedaids for the disabled, speech input/output,computational linguistics and VLSI testing.

D.R.J. Wilkins graduated from the HatfieldPolytechnic in 1975 in electrical and elec-tronic engineering. He joined the then PostOffice Research Centre as an executiveengineer working on regenerators forcoaxial cable and optical fibre transmission.More recently, he has been involved indeveloping computer-aided design systemsfor VLSI, with emphasis on aspects of test-ability, built-in test and circuit simulation.

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