evaluation of testability of path delay faults for user-configured programmable devices

A.KrasniewskiEvaluation of Testability of Path Delay Faults for User-Configured Programmable Devices - 1FPL’03

Evaluation of Testability of Path Delay Faultsfor User-Configured Programmable Devices

Andrzej Krasniewski

Institute of TelecommunicationsWARSAW UNIVERSITY OF TECHNOLOGY


MOTIVATION

Why delay faults (and not static faults)?

Increasingly more problems with timing of ICsbecause of• larger size and complexity• higher clock frequency• new phenomena in submicron technologies

If you look for a single fault model, this should be some kind of delay model

[T.M. Mak (Intel), panel discussion at IOLTS’03]


MOTIVATION (cont.)

Why testing user-configured device (and not relying on manufacturer’s test)?

• some timing problems caused by effects specific for the system environment (noise/interference)

• only a small fraction of all possible inteconnection patterns can be exercised by the manufacturer

Xilinx offers testing FPGA devices programmed with user-defined function (reduction of test costs by 80%)

[I. Bolsens (Xilinx), keynote at IOLTS’03]


MOTIVATION (cont.)

Why evaluation of testability (and not test pattern generation)?

• extremely difficult to generate deterministic patterns that account for different reasons for delay faults [Krstic&Liou, ITC’01]

• for FPGAs, BIST at no circuitry overhead or performance penalty

Random testing is likely to be a preferred test strategy for FPGA delay faults


PROBLEM

Analysis of timing-related faults in FPGAs - not easy to handle using “conventional” methods

conventional circuits(simple gates)

FPGAs(LUT-based)

static faults

dynamic faults(delay faults) ???

Specific features of FPGAs e.g. nonexistence of controlling values for many inputs

to basic logic components - LUTs


OUTLINE

Propagation delays and paths delay faults in FPGAs

Evaluation of testability of path delay faults – key factors

Observations and practical guidelines

• testability measures• type of tests• fault model (set of target faults)• restrictions on the set of input pairs


PATH DELAYS IN FPGAs

original path

configuration inputs

a g

fLUT1 LUT2

clk

clk

b hn

p

m

c j

d0

0

11

11e0

k

a (b c) g h+h’ j

Active Logic Component (ALC):after programming, output depends on two or more inputs

ALC-based modela

g

ALC1ALC2 ALC3

bf

cj

d

e

k

a (b c) d eg f’+ f j


PATH DELAYS IN FPGAs (cont.)

ASSUMPTIONS

• delays are assigned to both ALCs and connections

• delays of ALCs and connections may depend on the polarity of signal transitions

• delays of programmable ALCs may depend on their specific user-defined functions [Girard et al., IOLTS’03]

• for a multiple-destination connection, different delays may be assigned to its different branches

network of ALCs - model of a combinational section of an FPGA with a minimal number of components necessary for an analysis of path delays


LOGICAL PATHS & CORRESPONDING FAULTS

logical path = path (physical) + path transition pattern

e.g. cdfk

logical path must comply with ALC functions e.g. cdfk is not a logical path

is a pseudological path

path delay (fault) logical path

ag

ALC1ALC2 ALC3

bf

cj

d

e

k

a (b c) d eg f’+ f j

feasible logical path path transition pattern produced by some functional input pair


LOGICAL PATHS & CORRESPONDING FAULTS (cont.)

unknowndelay assignment

YES

redundant path

NO

sensitizable (true) under

some DA

logical path

set of feasible logical paths

never determines the speed of the network

DA

irredundant path

disturbancesin the fabrication

The speed of the network can only be affected by propagation delays (delay faults) associated with delay-essential logical paths [Krasniewski, DDECS’03]


LOGICAL PATHS & CORRESPONDING FAULTS (cont.)

Ideal fault model set of target faults associated with delay-essential paths

No knowledge of network timing is necessary to identify the set of delay-essential paths

examination of s-sensitizability of multipaths is necessary

irredundant

feasible

delay-essential

all logical paths

all pseudological and logical paths


OUTLINE






susceptability of network to testing

efficiency of test procedure

TESTABILITY EVALUATION

EVALUATION OF TESTABILITY OF DELAY FAULTS

MODEL OF NETWORKAND

PROPAGATION DELAYS specific for FPGAs

TESTABILITYMEASURES

TYPEOF TESTS TEST

SEQUENCE

SET OF TARGET FAULTSclass of logical paths

set of critical paths

RESTRICTIONSON INPUT SET

DEFINING TEST. MEASURES FOR PHYSICAL PATHS


TESTABILITY MEASURES & TYPES OF TESTS

TESTABILITY MEASURES• susceptbility of network to testing fault testability• quality of test sequence fault coverage

TYPES OF TESTS• weak non-robust (WNR)• strong non-robust (SNR)• robust (R)

Examples of testability measures:fault testability for robust tests (R-testability)fault coverage for weak non-robust tests (WNR-coverage)






MODEL OF NETWORKAND


TESTABILITYMEASURES

TYPEOF TESTS TEST

SEQUENCE






SET OF TARGET FAULTS

defined by a class of logical paths

SNR-testable

irredundant

feasible

delay-essential

R-testable

WNR-testable

all logical paths



SET OF TARGET FAULTS SELECTION - EXAMPLE

19 physical paths102 pseudological paths 90 logical paths

d e fb

h j

b (c d) c (a’+e’)a+b

d’ h+e

b’+h+n’ f m

f jg’ h

input register

output register

networkof ALCs

g

km

n

qp

ca


SET OF TARGET FAULTS SELECTION - EXAMPLE

fault testability fault coverage target paths

no. of paths WNR R WNR R

all pseudolog. & logical 192 35.9 26.0 12.0 6.3

all logical 90 76.6 55.6 25.6 13.3

feasible 74 75.7 67.6 29.7 16.2

irredundant 70 80.0 71.4 31.4 17.1

delay-essential 58 96.6 86.2 37.9 20.7

WNR-testable 69 100.0 72.5 33.3 17.4

SNR-testable 56 100.0 89.3 39.3 21.4

R-testable 50 100.0 100.0 42.0 24.0

„Exact” values of testability measures reasonably well approximated if the set of target faults associated with

irredundant and SNR-testable logical paths


SET OF TARGET FAULTS – CRITICAL PATHS

critical (physical) path

critical paths = longest paths, identified by structural or timing anlysis

more logical pathssensitization requirements more difficult to satisfy

lower values of testability measures






MODEL OF NETWORKAND


TESTABILITYMEASURES

TYPEOF TESTS TEST

SEQUENCE






TESTABILITY MEASURES FOR PHYSICAL PATHS

delay faults logical paths of a certain class

a physical paths with many logical paths (of a certain class) has a significantly higher impact on testability measures than a physical path with few logical paths

TESTABILITY MEASURES DEFINED FOR LOGICAL PATHS

simplest idea:a physical path has a certain testability-oriented property, e.g. is delay-essential or is R-covered by some test sequence, if at least one logical path associated with has this property

TESTABILITY MEASURES DEFINED FOR PHYSICAL PATHS


TESTABILITY MEASURES FOR PHYSICAL PATHS

fault testability fault coverage target paths - LOGICAL


all logical 90 76.6 55.6 25.6 13.3

irredundant 70 80.0 71.4 31.4 17.1

delay-essential 58 96.6 86.2 37.9 20.7

WNR-testable 69 100.0 72.5 33.3 17.4

R-testable 50 100.0 100.0 42.0 24.0

fault testability fault coverage target paths - PHYSICAL


all physical 19 94.7 84.2 73.7 42.1

irredundant 18 94.7 88.9 77.8 44.4

delay-essential 17 100.0 94.1 82.4 47.1

WNR-testable 18 100.0 94.1 77.8 44.4

R-testable 16 100.0 100.0 81.3 50.0






MODEL OF NETWORKAND


TESTABILITYMEASURES

TYPEOF TESTS TEST

SEQUENCE






RESTRICTIONS ON INPUT SET

networkof ALCs

CLKCLK

restricted set of input pairs- system function- sequential nature of subcircuit

Restrictions on the set of input pairs affect the relevant classes of logical paths (sets of target faults)

[Krasniewski, IOLTS’03]


RESTRICTIONS ON INPUT SET

SNR-testable

irredundant

feasible

delay-essential

R-testable

WNR-testable

all logical paths


restrictionson the set

of input pairsapply

Restrictions on the set of input pairs must be accounted for when calculating testability measures


OUTLINE






OBSERVATIONS AND PRACTICAL GUIDELINES

The values of path delay fault testability measures strongly depend on assumptions taken when calculating these values

Example network

from 13.3 % (6.3 %) coverage of faults corresponding to

all logical paths (pseudological and

logical paths) by R-tests

Coverage of the path delay faults, calculated for the

considered test sequence varies

to 82.4 % coverage of faults corresponding to

SNR-testable physical paths by WNR-tests


OBSERVATIONS AND PRACTICAL GUIDELINES (cont.)

Selection of the class of logical paths that defines the fault model poses an accuracy-complexity trade-off

• exact values, corresponding to the set of delay-essential logical paths - very difficult to calculate

• easy-to-calculate approximations - unacceptably inaccurate• sets of target faults corresponding to irredundant and SNR-

testable logical paths provide reasonably accurate estimates

Selection of critical paths only - questionable

reasonable if the set of critical paths is a small subset of the set of all paths - usually not the case for speed-optimized circuits


OBSERVATIONS AND PRACTICAL GUIDELINES (cont.)

Defining testability measures for physical paths - attractive

especially in the case when the rising and falling delays of individual components can be assumed equal or, at least, not significantly different

Restrictions on the set of vector pairs that occur at the input of the network in normal operation should be considered when defining the set of target faults

especially in the case when the fault coverage is calculated for a test sequence that has been developed taking into account these restrictions


CONCLUSION

Evaluation of testability of delay faults for user-configured FPGAs - difficult, both conceptually and computationally

Whenever the value of any measure of path delay fault testability for an FPGA is reported, a detailed explanation on what is reported should be given

In many publications, the presented values are claimed to represent “the coverage of path delay faults by robust tests” or sometimes even “the coverage of path delay faults”

uncertainty about the meaning of the results (test quality)

Obvious? NO!

examplecoverage of 50% of path delay faults- excellent test quality if R-coverage of delay-essential logical paths - poor test effort if coverage of R-testable logical paths by WNR tests

evaluation of testability of path delay faults for user-configured programmable devices

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