fall 09, aug 19 elec 5200-001/6200-001 lecture 2 (from prof. nelson's and prof. stroud's...

Fall 09, Aug 19Fall 09, Aug 19ELEC 5200-001/6200-001 Lecture 2 ELEC 5200-001/6200-001 Lecture 2

(from Prof. Nelson's and Prof. Stroud's course material)(from Prof. Nelson's and Prof. Stroud's course material) 11

ELEC 5200-001/6200-001ELEC 5200-001/6200-001Computer Architecture and DesignComputer Architecture and Design

Fall 2009 Fall 2009

Review of VHDLReview of VHDL

Nitin Yogi

08/19/2009



HDLs in Digital System DesignHDLs in Digital System Design

Model and document digital systemsModel and document digital systems– Hierarchical modelsHierarchical models

System, RTL (Register Transfer Level), gatesSystem, RTL (Register Transfer Level), gates

– Different levels of abstractionDifferent levels of abstractionBehavior, structureBehavior, structure

Verify circuit/system design via simulationVerify circuit/system design via simulation

Synthesize circuits from HDL models Synthesize circuits from HDL models



Hardware Description LanguagesHardware Description LanguagesVHDL = VHSIC Hardware Description Language VHDL = VHSIC Hardware Description Language (VHSIC = Very High Speed Integrated Circuits)(VHSIC = Very High Speed Integrated Circuits)– Developed by DOD from 1983 – based on ADADeveloped by DOD from 1983 – based on ADA– IEEE Standard 1076-1987/1993/200xIEEE Standard 1076-1987/1993/200x– Based on the ADA languageBased on the ADA language

Verilog – created in 1984 by Philip Moorby of Verilog – created in 1984 by Philip Moorby of Gateway Design Automation (merged with Gateway Design Automation (merged with Cadence)Cadence)– IEEE Standard 1364-1995/2001/2005IEEE Standard 1364-1995/2001/2005– Based on the C languageBased on the C language– IEEE P1800 “System Verilog” in voting stage & will be IEEE P1800 “System Verilog” in voting stage & will be

merged with 1364merged with 1364



Other VHDL StandardsOther VHDL Standards

1076.11076.1–1999: VHDL-AMS (Analog & Mixed-–1999: VHDL-AMS (Analog & Mixed-Signal Extensions)Signal Extensions)1076.21076.2–1996: Std. VHDL Mathematics –1996: Std. VHDL Mathematics PackagesPackages1076.31076.3-1997: Std. VHDL Synthesis Packages-1997: Std. VHDL Synthesis Packages1076.41076.4-1995: Std. VITAL Modeling Specification -1995: Std. VITAL Modeling Specification (VHDL Initiative Towards ASIC Libraries)(VHDL Initiative Towards ASIC Libraries)1076.61076.6-1999: Std. for VHDL Register Transfer -1999: Std. for VHDL Register Transfer Level (RTL) SynthesisLevel (RTL) Synthesis11641164-1993: Std. Multivalue Logic System for -1993: Std. Multivalue Logic System for VHDL Model InteroperabilityVHDL Model Interoperability



Anatomy of a VHDL modelAnatomy of a VHDL model

““Entity” describes the Entity” describes the externalexternal view of a view of a design/componentdesign/component

““Architecture” describes the Architecture” describes the internalinternal behavior/structure of the componentbehavior/structure of the componentExample: Example:

1-bit full adder1-bit full adder A

B

Cin

Sum

Cout

Full Adder



Entity Inputs/OutputsEntity Inputs/Outputs

External view comprises input/output signals External view comprises input/output signals (“ports”)(“ports”)

A “port” is defined by its signal name, direction A “port” is defined by its signal name, direction and type: and type:

port_name: direction data_type;port_name: direction data_type;– direction:direction:

in - driven into the entity from an external source in - driven into the entity from an external source

out - driven from within the entityout - driven from within the entity

inout - bidirectional – drivers within the entity and externalinout - bidirectional – drivers within the entity and external

– data_type:data_type: any scalar or aggregate signal type any scalar or aggregate signal type



Built-in Data TypesBuilt-in Data Types

Scalar (single-value) signal types:Scalar (single-value) signal types:– bit - values are ‘0’ or ‘1’bit - values are ‘0’ or ‘1’– boolean – values are TRUE and FALSEboolean – values are TRUE and FALSE– integerinteger

Aggregate (multi-value) signal types:Aggregate (multi-value) signal types:– bit_vector – array of bitsbit_vector – array of bits

signal b: bit_vector(7 downto 0);signal b: bit_vector(7 downto 0);signal c: bit_vector(0 to 7);signal c: bit_vector(0 to 7);



IEEE Standard 1164 Data TypesIEEE Standard 1164 Data Types

Type Type std_logicstd_logic data values: data values:

‘‘U’, ‘X’ – uninitialized/unknownU’, ‘X’ – uninitialized/unknown‘0’, ‘1’ – strongly-driven 0/1‘0’, ‘1’ – strongly-driven 0/1‘L’, ‘H’ – weakly-driven 0/1 (resistive)‘L’, ‘H’ – weakly-driven 0/1 (resistive)‘Z’, ‘W’ - strong/weak “floating”‘Z’, ‘W’ - strong/weak “floating”‘-’ - don’t care‘-’ - don’t care

Type std_logic_vector is array of std_logicType std_logic_vector is array of std_logic

Include package:Include package:library IEEE;library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;



User-Defined Data TypesUser-Defined Data Types

Any abstract data type can be createdAny abstract data type can be created

Examples:Examples:

type mnemonic is (add,sub,mov,jmp);type mnemonic is (add,sub,mov,jmp);

signal op: mnemonic;signal op: mnemonic;

type byte is array(0 to 7) of bit;type byte is array(0 to 7) of bit;

signal dbus: byte;signal dbus: byte;



entity formatentity format

entity entity_name is

generic (optional)(generic_name: type :=default_value;…generic_name: mode signal_type);

port(signal_name: mode signal_type; …signal_name: mode signal_type);

end entity entity_name;



entity example entity example (1-Bit Full Adder)(1-Bit Full Adder)

entity full_add1 isentity full_add1 is port (port ( -- I/O ports -- I/O ports

a: in bit; -- a inputa: in bit; -- a input b: in bit; -- b inputb: in bit; -- b input cin: in bit; -- carry inputcin: in bit; -- carry input sum: out bit; -- sum outputsum: out bit; -- sum output cout: out bit); -- carry outputcout: out bit); -- carry output

end full_add1 ;end full_add1 ;

A

B

Cin

Sum

Cout

Full Adder



architecture formatarchitecture formatarchitecture architecture_name of entity_name is

-- data type definitions (ie, states, arrays, etc.)

-- internal signal declarations

-- component declarations

-- function and procedure declarations

begin-- behavior of the model is described here using:

-- component instantiations

-- concurrent statements

-- processes

end architecture architecture_name;



architecture examplearchitecture example(behavioral)(behavioral)

architecture dataflow of full_add1 isarchitecture dataflow of full_add1 is

beginbegin

sum <= a xor b xor cin after 1 ns;sum <= a xor b xor cin after 1 ns;

cout <= (a and b) or (a and cin) or cout <= (a and b) or (a and cin) or

(b and cin) after 1 ns;(b and cin) after 1 ns;

end;end;



Example using an internal signalExample using an internal signal

architecture dataflow of full_add1 isarchitecture dataflow of full_add1 is signal x1: bit;signal x1: bit; -- internal signal-- internal signalbeginbegin

x1x1 <= a xor b after 1 ns; <= a xor b after 1 ns;sum <= sum <= x1x1 xor cin after 1 ns; xor cin after 1 ns;

cout <= (a and b) or (a and cin) or cout <= (a and b) or (a and cin) or (b and cin) after 1 ns;(b and cin) after 1 ns;

end;end;



Event-Driven Simulation ExampleEvent-Driven Simulation Example

a <= b after 1ns;a <= b after 1ns;c <= a after 1ns;c <= a after 1ns;

Time a b cTime a b c T ‘0’ ‘0’ ‘0’T ‘0’ ‘0’ ‘0’ T+1 ‘0’ ‘1’ ‘0’ - external event on bT+1 ‘0’ ‘1’ ‘0’ - external event on b T+2 ‘1’ ‘1’ ‘0’ - resulting event on a T+2 ‘1’ ‘1’ ‘0’ - resulting event on a T+3 ‘1’ ‘1’ ‘1’ - resulting event on cT+3 ‘1’ ‘1’ ‘1’ - resulting event on c



architecture example (Structural )architecture example (Structural )architecture structure of full_add1 isarchitecture structure of full_add1 is

component xor iscomponent xor is -- declare component to be used-- declare component to be usedport (x,y: in bit;port (x,y: in bit;

z: out bit);z: out bit);end component xor;end component xor;signal x1: bit;signal x1: bit; -- signal internal to this component-- signal internal to this component

beginbeginG1: xor port map (A, B, X1);G1: xor port map (A, B, X1); -- instantiate 1-- instantiate 1stst xor gate xor gateG2: xor port map (X1, Cin, Sum); -- instantiate 2G2: xor port map (X1, Cin, Sum); -- instantiate 2ndnd xor gate xor gate

… …add circuit for carry outputadd circuit for carry output……end;end; A X1

SumCin



Example: D flip-flopExample: D flip-flop

entity DFF isentity DFF is port (Preset: in bit; port (Preset: in bit;

Clear: in bit;Clear: in bit; Clock: in bit;Clock: in bit; Data: in bit;Data: in bit; Q: out bit;Q: out bit; Qbar: out bit);Qbar: out bit);

end DFF;end DFF;

Data

Clock

Q

Qbar

Preset

Clear



7474 D flip-flop equations7474 D flip-flop equations

architecture eqns of DFF isarchitecture eqns of DFF issignal A,B,C,D: bit;signal A,B,C,D: bit;signal QInt, QBarInt: bit;signal QInt, QBarInt: bit;

beginbeginA <= not (Preset and D and B) after 1 ns;A <= not (Preset and D and B) after 1 ns;B <= not (A and Clear and Clock) after 1 ns;B <= not (A and Clear and Clock) after 1 ns;C <= not (B and Clock and D) after 1 ns;C <= not (B and Clock and D) after 1 ns;D <= not (C and Clear and Data) after 1 ns;D <= not (C and Clear and Data) after 1 ns;Qint <= not (Preset and B and QbarInt) after 1 ns;Qint <= not (Preset and B and QbarInt) after 1 ns;QBarInt <= not (QInt and Clear and C) after 1 ns;QBarInt <= not (QInt and Clear and C) after 1 ns;Q <= QInt;Q <= QInt;QBar <= QBarInt;QBar <= QBarInt;

end;end;



4-bit Register (Structural Model) 4-bit Register (Structural Model)

entity Register4 isentity Register4 is

port ( D: in bit_vector(0 to 3);port ( D: in bit_vector(0 to 3);

Q: out bit_vector(0 to 3);Q: out bit_vector(0 to 3);

Clk: in bit;Clk: in bit;

Clr: in bit;Clr: in bit;

Pre: in bit);Pre: in bit);

end Register4;end Register4;D(3)

Q(3)

D(2) D(1) D(0)

Q(2) Q(1) Q(0)

CLKPRECLR



Register ArchitectureRegister Architecture

architecture structure of Register4 isarchitecture structure of Register4 iscomponent DFF iscomponent DFF is -- declare library component to be used-- declare library component to be used port (Preset: in bit; port (Preset: in bit;

Clear: in bit;Clear: in bit; Clock: in bit;Clock: in bit; Data: in bit;Data: in bit; Q: out bit;Q: out bit; Qbar: out bit);Qbar: out bit);

end component DFF;end component DFF; signal Qbar: bit_vector(0 to 3); signal Qbar: bit_vector(0 to 3); -- dummy for unused FF output-- dummy for unused FF outputbegin begin -- Signals connected to ports in order listed above-- Signals connected to ports in order listed above

F3: DFF port map (Pre, Clr, Clk, D(3), Q(3), Qbar(3));F3: DFF port map (Pre, Clr, Clk, D(3), Q(3), Qbar(3));F2: DFF port map (Pre, Clr, Clk, D(2), Q(2), Qbar(2));F2: DFF port map (Pre, Clr, Clk, D(2), Q(2), Qbar(2));F1: DFF port map (Pre, Clr, Clk, D(1), Q(1), Qbar(1));F1: DFF port map (Pre, Clr, Clk, D(1), Q(1), Qbar(1));F0: DFF port map (Pre, Clr, Clk, D(0), Q(0), Qbar(0));F0: DFF port map (Pre, Clr, Clk, D(0), Q(0), Qbar(0));

end;end;



Register ArchitectureRegister Architecture(short cut – “generate” statement)(short cut – “generate” statement)

beginbeginfor k in 0 to 3 generatefor k in 0 to 3 generate F: DFF port map (Pre, Clr, Clk, D(k), Q(k), Qbar(k));F: DFF port map (Pre, Clr, Clk, D(k), Q(k), Qbar(k));end generate;end generate;

end;end;

Generates multiple copies of the given statement(s)Generates multiple copies of the given statement(s)Value of k inserted where specifiedValue of k inserted where specifiedIteration number k is appended to each label FIteration number k is appended to each label FResult is identical to previous exampleResult is identical to previous example



Statements used for modelingStatements used for modeling

Concurrent statementsConcurrent statements– Concurrent assignmentsConcurrent assignments– with – select – whenwith – select – when– when – elsewhen – else

Sequential statements using “process”Sequential statements using “process”– if – then – elseif – then – else– case – whencase – when– for – loopfor – loop– while - loopwhile - loop



Concurrent assignmentsConcurrent assignments

A <= not (Preset and D and B) after 1 ns;A <= not (Preset and D and B) after 1 ns;

B <= not (A and Clear and Clock) after 1 ns;B <= not (A and Clear and Clock) after 1 ns;

C <= not (B and Clock and D) after 1 ns;C <= not (B and Clock and D) after 1 ns;

D <= not (C and Clear and Data) after 1 ns;D <= not (C and Clear and Data) after 1 ns;



With – select - whenWith – select - when

with S selectwith S select

y <= a after 1 ns when “00”,y <= a after 1 ns when “00”,

b after 1 ns when “01”,b after 1 ns when “01”,

c after 1 ns when “10”,c after 1 ns when “10”,

d after 1 ns when “11”;d after 1 ns when “11”;

(or: d after 1 ns when others;)(or: d after 1 ns when others;)

00

01

10

11

a

b

c

d

S

y

4-to-1 Mux



When - elseWhen - else

y <= a after 1 ns when (S=“00”) elsey <= a after 1 ns when (S=“00”) else

b after 1 ns when (S=“01”) elseb after 1 ns when (S=“01”) else

c after 1 ns when (S=“10”) elsec after 1 ns when (S=“10”) else

d after 1 ns;d after 1 ns;

Any boolean expression can beAny boolean expression can be

used for each condition.used for each condition.

Ex. Ex. y <= a after 1 ns when (F=‘1’) and (G=‘0’) …y <= a after 1 ns when (F=‘1’) and (G=‘0’) …

00

01

10

11

a

b

c

d

S

y

4-to-1 Mux



Tristate buffer exampleTristate buffer example

library ieee;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_1164.all;

entity tristate isentity tristate is port ( a: in bit;port ( a: in bit;

y: out std_logic;y: out std_logic; en: in bit);en: in bit);

end tristate;end tristate;

architecture a1 of tristate isarchitecture a1 of tristate isbeginbegin

y <= ay <= a after 1 ns when (en=‘1’) else after 1 ns when (en=‘1’) else ‘ ‘Z’ after 1 ns;Z’ after 1 ns;

end;end;-- Error: Type mismatch between y and a-- Error: Type mismatch between y and a

ya

en



Tristate buffer exampleTristate buffer example(correct)(correct)


entity tristate isentity tristate is port ( a: in bit;port ( a: in bit;

y: out std_logic;y: out std_logic; en: in bit);en: in bit);



y <= ‘0’ after 1 ns when (en=‘1’) and (a=‘0’) elsey <= ‘0’ after 1 ns when (en=‘1’) and (a=‘0’) else ‘ ‘1’ after 1 ns when (en=‘1’) and (a=‘1’) else1’ after 1 ns when (en=‘1’) and (a=‘1’) else

‘ ‘Z’ after 1 ns;Z’ after 1 ns;end;end;

ya

en



Tristate bus buffer exampleTristate bus buffer example


entity tristate isentity tristate is port ( a: in bit_vector(0 to 7);port ( a: in bit_vector(0 to 7);

y: out std_logicvector(0 to 7);y: out std_logicvector(0 to 7); en: in bit);en: in bit);



y <= y <= to_stdlogicvector(a)to_stdlogicvector(a) after 1 ns when (en=‘1’) else after 1 ns when (en=‘1’) else “ “ZZZZZZZZ” after 1 ns;ZZZZZZZZ” after 1 ns;

end;end;

ya

en



VHDL “Process” ConstructVHDL “Process” Construct

Allows conventional programming language Allows conventional programming language methods to describe circuit behaviormethods to describe circuit behavior

Supported language constructs (“sequential Supported language constructs (“sequential statements”) statements”) –– only allowed within a processonly allowed within a process::– variable assignmentvariable assignment– if-then-else (elsif)if-then-else (elsif)– case statementcase statement– while (condition) loopwhile (condition) loop– for (range) loopfor (range) loop



Process FormatProcess Format

[label:] process ([label:] process (sensitivity listsensitivity list))declarationsdeclarations

beginbeginsequential statementssequential statements

end process;end process;

Process statements executed once at start of Process statements executed once at start of simulationsimulationProcess halts at “end” until an event occurs on a Process halts at “end” until an event occurs on a signal in the “sensitivity list”signal in the “sensitivity list”



Using a “process” to model Using a “process” to model sequential behaviorsequential behavior

entity DFF is entity DFF is port (D,CLK: in std_logic;port (D,CLK: in std_logic;

Q: out std_logic);Q: out std_logic);end DFF;end DFF;

architecture behave of DFF isarchitecture behave of DFF isbeginbegin

process(clk) -- “process sensitivity list”process(clk) -- “process sensitivity list”beginbegin

if if (clk’event and clk=‘1’)(clk’event and clk=‘1’) then then Q <= D after 1 ns;Q <= D after 1 ns;end if;end if;

end process;end process;end;end;

Process statements executed sequentially (sequential statements)Process statements executed sequentially (sequential statements)clk’event is an attribute of signal clk which is TRUE if an event has occurred on clk at the current clk’event is an attribute of signal clk which is TRUE if an event has occurred on clk at the current simulation timesimulation time

D Q

CLK



Alternative to sensitivity listAlternative to sensitivity listentity DFF is entity DFF is port (D,CLK: in std_logic;port (D,CLK: in std_logic;

Q: out std_logic);Q: out std_logic);end DFF;end DFF;architecture behave of DFF isarchitecture behave of DFF isbeginbegin

process -- no “sensitivity list”process -- no “sensitivity list”beginbegin

wait on clk; -- suspend process until event on clkwait on clk; -- suspend process until event on clkif (clk=‘1’) thenif (clk=‘1’) then Q <= D after 1 ns;Q <= D after 1 ns;end if;end if;


Other “wait” formats: wait until (clk’event and clk=‘1’)Other “wait” formats: wait until (clk’event and clk=‘1’) wait for 20 ns; wait for 20 ns;Process executes endlessly if no sensitivity list or wait statement!Process executes endlessly if no sensitivity list or wait statement!

D Q

CLK



D latch vs. D flip-flopD latch vs. D flip-flopentity Dlatch is entity Dlatch is port (D,CLK: in std_logic;port (D,CLK: in std_logic;

Q: out std_logic);Q: out std_logic);end Dlatch;end Dlatch;architecture behave of Dlatch isarchitecture behave of Dlatch isbeginbegin

process(D, clk)process(D, clk)beginbegin

if if (clk=‘1’)(clk=‘1’) then then Q <= D after 1 ns;Q <= D after 1 ns;end if;end if;


For latch, Q changes whenever the latch is enabled by CLK=‘1’For latch, Q changes whenever the latch is enabled by CLK=‘1’(rather than being edge-triggered)(rather than being edge-triggered)

D Q

CLK



Synchronous vs. Asynchronous Synchronous vs. Asynchronous Flip-Flop InputsFlip-Flop Inputs

entity DFF is entity DFF is port (D,CLK: in std_logic;port (D,CLK: in std_logic; PRE,CLR: in std_logic;PRE,CLR: in std_logic;

Q: out std_logic);Q: out std_logic);end DFF;end DFF;architecture behave of DFF isarchitecture behave of DFF isbeginbegin

process(clk,PRE,CLR)process(clk,PRE,CLR)beginbegin

if (CLR=‘0’) then if (CLR=‘0’) then -- CLR has precedence-- CLR has precedence Q <= ‘0’ after 1 ns;Q <= ‘0’ after 1 ns;elsif (PRE=‘0’) then elsif (PRE=‘0’) then -- Then PRE has precedence-- Then PRE has precedence Q <= ‘1’ after 1 ns;Q <= ‘1’ after 1 ns;elsif (clk’event and clk=‘1’) thenelsif (clk’event and clk=‘1’) then Q <= D after 1 ns; Q <= D after 1 ns; -- Only if CLR=PRE=‘1’-- Only if CLR=PRE=‘1’end if;end if;


CLRD Q

CLK PRE



Configurable N-bit registerConfigurable N-bit registerentity REG is entity REG is generic (N:integer := 4)generic (N:integer := 4) port (D: in std_logic_vector(N-1 downto 0);port (D: in std_logic_vector(N-1 downto 0); CLK: in std_logic;CLK: in std_logic;

Q: out std_logic_vector(N-1 downto 0));Q: out std_logic_vector(N-1 downto 0));end REG;end REG;architecture behave of REG isarchitecture behave of REG isbeginbegin

process(clk)process(clk)beginbegin

if (clk’event and clk=‘1’) thenif (clk’event and clk=‘1’) then Q <= D after 1 ns; Q <= D after 1 ns; end if;end if;




Signals vs VariablesSignals vs Variables

SignalsSignals– Signals follow the notion of ‘event scheduling’Signals follow the notion of ‘event scheduling’– An event is characterized by a (time,value) pairAn event is characterized by a (time,value) pair– Signal assignment example:Signal assignment example:X <= Xtmp after <time>;X <= Xtmp after <time>; meansmeansSchedule the assignment of the value of signal Schedule the assignment of the value of signal XtmpXtmp to signal to signal XX at (Current time + <time>) at (Current time + <time>)

VariablesVariables– Variables do not have notion of ‘events’Variables do not have notion of ‘events’– Variables can be defined and used only inside the Variables can be defined and used only inside the processprocess block and some other special blocks. block and some other special blocks.



Using a “variable” to describe Using a “variable” to describe sequential behavior within a processsequential behavior within a process

cnt: process(clk)cnt: process(clk)variable count_v: std_logic_vector; variable count_v: std_logic_vector; -- internal counter variable-- internal counter variablesignal count_s: std_logic_vector; signal count_s: std_logic_vector; -- internal counter signal-- internal counter signal

beginbeginif clk=‘1’ and clk’event thenif clk=‘1’ and clk’event then

if load=‘1’ thenif load=‘1’ thencount_v := Din; count_v := Din; count_s <= Din after 1ns;count_s <= Din after 1ns;

elsif cnt=‘1’ thenelsif cnt=‘1’ thencount_v := count_v + 1; count_v := count_v + 1; -- use appropriate package for ‘+’-- use appropriate package for ‘+’

count_s <= count_s + 1 after 1ns;count_s <= count_s + 1 after 1ns;end if;end if;

end if; end if; DoutA <= count_v after 1ns;DoutA <= count_v after 1ns;

DoutB <= count_s after 1ns;DoutB <= count_s after 1ns; end process;end process;

TimeTime clkclk loadload DinDin count_vcount_v count_scount_s DoutADoutA DoutBDoutB

0-0- 00 11 11 00 00 00 00

00 11 11 11 11 00 00 00

11 11 11 11 11 11 11 00



Sequential statements in processSequential statements in processif-then-elsif-else if-then-elsif-else statementstatementif if conditioncondition then then

(... sequence of statements...)(... sequence of statements...) elsif elsif conditioncondition then then

(... sequence of statements...)(... sequence of statements...)else else

(... sequence of statements...)(... sequence of statements...) end if; end if;

case case statementstatementcase case expressionexpression is is

when when choiceschoices => => sequence of statementssequence of statements when when choiceschoices => => sequence of statementssequence of statements ... ... when when othersothers => => sequence of statementssequence of statements

end case;end case;



Sequential statements in processSequential statements in process

while while looploop [[label:label:]] while while conditioncondition loop loop

... sequence of statements ... ... sequence of statements ... end loopend loop [[labellabel]]; ;

for for looploop[[label:label:] for ] for loop_variableloop_variable in in rangerange loop loop

... sequence of statements... ... sequence of statements... end loop end loop [[labellabel]]; ;



Modeling Finite State Machines Modeling Finite State Machines (Synchronous Sequential Circuits)(Synchronous Sequential Circuits)

Comb.Logic

FFs

Inputsx

Outputsz

Next StateY

Present Statey

Next State Y = f(x,y)

Clock



Synchronous Sequential Circuit Synchronous Sequential Circuit (FSM) Example(FSM) Example

B /0 C /1 A /1

0 /0

1 /1 1 /0

1 /1

0 /0

0 /0

X /ZP resen t

s ta teIn p u t x

0 1

N ex t s ta te /o u tp u t

A /0 A /0 C /0

A B C

A

BC



FSM Example – entity definitionFSM Example – entity definition

entity seqckt isentity seqckt is

port (port (

x: in bit;x: in bit; -- FSM input-- FSM input

z: out bit;z: out bit; -- FSM output-- FSM output

clk: in bit );clk: in bit ); -- clock-- clock

end seqckt;end seqckt;



FSM Example - behavioral modelFSM Example - behavioral model

architecture behave of seqckt isarchitecture behave of seqckt istype states is (A,B,C); -- symbolic state namestype states is (A,B,C); -- symbolic state namessignal curr_state,next_state: states;signal curr_state,next_state: states;

beginbegin-- Model the memory elements of the FSM-- Model the memory elements of the FSMprocess (clk)process (clk)beginbegin

if (clk’event and clk=‘1’) thenif (clk’event and clk=‘1’) thenpres_state <= next_state;pres_state <= next_state;

end if;end if;end process;end process;

(continue on next slide)(continue on next slide)



FSM Example - continuedFSM Example - continued

-- Model the next-state and output functions of the FSM-- Model the next-state and output functions of the FSMprocess (x, pres_state) process (x, pres_state) -- function inputs-- function inputsbeginbegin

case pres_state is case pres_state is -- describe each state -- describe each state when A => if (x = ‘0’) thenwhen A => if (x = ‘0’) then

z <= ‘0’;z <= ‘0’;next_state <= A;next_state <= A;

else else -- (x = ‘1’)-- (x = ‘1’)z <= ‘0’;z <= ‘0’;next_state <= B;next_state <= B;

end if;end if;(continue next slide for pres_state = B and C)(continue next slide for pres_state = B and C)



FSM Example (continued)FSM Example (continued)

when B => if (x=‘0’) thenwhen B => if (x=‘0’) thenz <= ‘0’;z <= ‘0’;next_state <= A;next_state <= A;

elseelsez <= ‘1’;z <= ‘1’;next_state <= C;next_state <= C;

end if;end if;when C => if (x=‘0’) thenwhen C => if (x=‘0’) then

z <= ‘0’;z <= ‘0’;next_state <= C;next_state <= C;

elseelsez <= ‘1’;z <= ‘1’;next_state <= A;next_state <= A;

end if;end if; end case;end case;




64K x 8 Memory Example64K x 8 Memory Example

library ieee;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_1164.all;use work.qsim_logic.all;use work.qsim_logic.all; -- package with to_integer() -- package with to_integer()

funcfunc

entity memory8 isentity memory8 is port (dbus: inout std_logic_vector(0 to 7);port (dbus: inout std_logic_vector(0 to 7); abus: in std_logic_vector(0 to 15);abus: in std_logic_vector(0 to 15); ce: in bit;ce: in bit; -- active low chip enable-- active low chip enable oe: in bit;oe: in bit; -- active low output enable-- active low output enable we: in bit);we: in bit); -- active low write enable-- active low write enableend memory8;end memory8;



64K x 8 Memory Example64K x 8 Memory Examplearchitecture reglevel of memory8 isarchitecture reglevel of memory8 isbeginbegin process (ce,oe,we,abus,dbus)process (ce,oe,we,abus,dbus) type mem is array(natural range <>) of std_logic_vector(0 to 7);type mem is array(natural range <>) of std_logic_vector(0 to 7); variable M: mem(0 to 65535);variable M: mem(0 to 65535); beginbegin if (ce='0') and (oe='0') then if (ce='0') and (oe='0') then -- read enabled-- read enabled dbus <= M(to_integer(abus));dbus <= M(to_integer(abus)); -- drive the bus-- drive the bus elsif (ce='0') and (we='0') then elsif (ce='0') and (we='0') then -- write enabled-- write enabled dbus <= "ZZZZZZZZ";dbus <= "ZZZZZZZZ"; -- disable drivers-- disable drivers M(to_integer(abus)) := dbus;M(to_integer(abus)) := dbus; -- write to M-- write to M elseelse dbus <= "ZZZZZZZZ";dbus <= "ZZZZZZZZ"; --disable drivers--disable drivers end if;end if; end process;end process;end;end;



Miscellaneous VHDL ItemsMiscellaneous VHDL Items

Subtypes of previously-defined data typesSubtypes of previously-defined data types

subtype int3 is integer range 0 to 7;subtype int3 is integer range 0 to 7;

Use of “alias” for existing elementsUse of “alias” for existing elements

signal instruc: bit_vector(0 to 31);signal instruc: bit_vector(0 to 31);

alias opcode: bit_vector(0 to 5) is instruc(0 to 5);alias opcode: bit_vector(0 to 5) is instruc(0 to 5);alias rd: bit_vector(0 to 4) is instruc(6 to 10);alias rd: bit_vector(0 to 4) is instruc(6 to 10);alias rs: bit_vector(0 to 4) is instruc(11 to 15);alias rs: bit_vector(0 to 4) is instruc(11 to 15);

Fill a bit_vector with a constant (right-most bits):Fill a bit_vector with a constant (right-most bits):A <= (‘0’,’1’,’1’, others => ‘0’);A <= (‘0’,’1’,’1’, others => ‘0’);

B(15 downto 0) <= C(15 downto 0);B(15 downto 0) <= C(15 downto 0);B(31 downto 16) <= (others => C(15)); -- sign extension!B(31 downto 16) <= (others => C(15)); -- sign extension!

Concatenate bits and bit_vectorsConcatenate bits and bit_vectorsA <= B & C(0 to 3) & “00”; -- A is 16 bits, B is 10 bitsA <= B & C(0 to 3) & “00”; -- A is 16 bits, B is 10 bits



Unconstrained Bit VectorsUnconstrained Bit VectorsAllows a generic component with different sizes:Allows a generic component with different sizes:

entity mux isentity mux is

port (port (a,b: in bit_vector; -- a,b: in bit_vector; -- unconstrainedunconstrained

c: out bit_vector;c: out bit_vector;

s: in bit );s: in bit );

end mux;end mux;

architecture x of mux isarchitecture x of mux is

beginbegin

c <= a when (s=‘0’) else b;c <= a when (s=‘0’) else b;

end;end;



Unconstrained Bit VectorsUnconstrained Bit VectorsVector constrained when instantiated:Vector constrained when instantiated:

architecture struct of my_design is architecture struct of my_design is signal s1,s2: bit;signal s1,s2: bit;

signal a5,b5,c5: bit_vector (0 to 4);signal a5,b5,c5: bit_vector (0 to 4);signal a32,b32,c32: bit_vector (0 to 31);signal a32,b32,c32: bit_vector (0 to 31);component mux component mux

port (a,b: in bit_vector; -- unconstrainedport (a,b: in bit_vector; -- unconstrainedc: out bit_vector;c: out bit_vector;s: in bit );s: in bit );

end component;end component;beginbegin

M5: mux port map (a5,b5,c5,s1); -- 5-bit muxM5: mux port map (a5,b5,c5,s1); -- 5-bit muxM32: mux port map (a32,b32,c32,s2); -- 32-bit muxM32: mux port map (a32,b32,c32,s2); -- 32-bit mux

end;end;



Other VHDL resourcesOther VHDL resourcesVHDL mini-reference onVHDL mini-reference on Prof. Nelson’s Prof. Nelson’s websitewebsite– http://www.eng.auburn.edu/department/ee/mgc/vhdl.html

VHDL resources on VHDL resources on Prof. Stroud’sProf. Stroud’s website website– http://www.eng.auburn.edu/~strouce/elec4200.html

VHDL Tutorial: Learn by Example VHDL Tutorial: Learn by Example byby Weijun Zhang Weijun Zhang – http://esd.cs.ucr.edu/labs/tutorial/

fall 09, aug 19 elec 5200-001/6200-001 lecture 2 (from prof. nelson's and prof. stroud's...

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