fabrication of ic 7

Michel CalameDpt. of Physics, Klingelbergstrasse 82, 4056 Basel

room: 1.20, 1st floor

email: [email protected]

web: http://calame.unibas.ch/

Micro- and nano-fabrication

Nano III

Nanofabrication, Nano III / mc / 2

Outline

• Introduction:

overview, state of the art

semiconductor physics basics ( CMOS)

• Fabrication basics

– IC fabrication overview

– clean-rooms

– Silicon: from sand to wafer

– material deposition techniques

– etching

– lithography

– examples of devices: MEMS, NEMS

• Outlook: new and future techniques


References

• overview books

1. Fundamentals of Microfabrication: The Science of Miniaturization M. Madou, 2nd ed., CRC Press, 2002

2. Nanoelectronics and Information Technology R. Waser ed., Wiley-VCH, 2003 (newer edition…)

3. VLSI Technology (more physical) SM. Sze, 2nd ed., McGraw-Hill, 1988

4. Introduction to Semiconductor Manufacturing Technology

H. Xiao, Prentice-Hall, 2001.


Introduction

1947, 24th December

John Bardeen

Walter Brattain

William Schockley

first point contact transfer resistor

Bell labsBell labs nobel.se

ATT Bell Labs


Introduction

1958

Jack Kilby, Texas Instruments

first IC (Integrated Circuit)

C. Esser, Infineon


Introduction

1961, Robert Noyce,

Fairchild Camera

first integrated circuit available as a monolithic chip

Planar technology

(Si substrate and Al lines)

C. Esser, Infineon


Introduction

1971 Intel anounces the i4004 microprocessor

"a new era of integrated electronics"

2250 transistors, 10μm technology, 108kHz

http://www.intel.com


Introduction

1981

Intel i8088

29000 transistors, 3μmtechnology, 8MHz

invention of the PC (personal computer)

IBM, A.Child, B.Gates

http://www.intel.com


Introduction

http://www.pbs.org/transistor/

“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short this rate can be expected to continue, if not increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years.”

Electronics, Vol. 38(8), 1965

1965, Gordon E. Moore

(co-founder Intel Corporation)

Nanofabrication, Nano III / mc / 10 M. Bohr, Intel

Introduction

Scaling trends

Nanofabrication, Nano III / mc / 11 M. Bohr, Intel

Introduction

Scaling trends

performance , power , cost


Introduction

state of the art today 45nm(near) future: 32nm, …

www.intel.com/technology/


Introduction

“I think there is a world market for

maybe five computers.”

Thomas Watson,

Chairman of IBM, 1943

“There is no reason for any

individual to have a computer in

their home.”

Ken Olson,

President, Chairman and Founder of Digital Equipment Corp., 1977

“640K ought to be enough for

anybody.”

Bill Gates, Microsoft founder, 1981

(though today he denies he said it)


Introduction

1958 1 transistor = 10 US$;

first integrated circuit with 4 transistors: 150 US$

market 218·106 US$

2000 for 10 US$, you receive 50·106 transistors (with passive components, interconnects, ...)

market 200-300·109 US$

unprecedented in industry's history


Introduction

J. Gobrecht, PSI


Introduction

top-down approach:

extend current techniques to smaller sizes

(EUV-L, x-ray lithography., nano-imprint, flip-up principle, i.e.: horizontal/vertical exchange, etc…)

problem: precision, costs

bottom-up approach:

start from individual atoms/molecules

use principles of self-organization (self-assembly; inspiration from biology, biochemistry, chemistry)

problem: long-range order difficult to achieve


Introduction

micro-fabrication

UV lithography, micro-CP

sub-micrometer fabrication

EBL, FIB

chemical synthesis

-SH

1 mμ

100nm

10nm

1nm

10 mμ

top-down approach:

extend current techniques to smaller sizes

(EUV-L, x-ray lithography., nano-imprint, flip-up principle, i.e.: horizontal/vertical exchange, etc…)

problem: precision, costs

bottom-up approach:

start from individual atoms/molecules

use principles of self-organization (self-assembly; inspiration from biology, biochemistry, chemistry)

problem: long-range order difficult to achieve

nanofabrication (<100nm) combination of both routes


Outline

• Introduction:

overview, state of the art,

semiconductor physics reminder

( condensed matter course)



– clean-rooms



– etching

– lithography




Semiconductors physics reminder

Energy gaps

Si ~ 1.12 eVGe ~ 0.66 eVGaAs ~ 1.43 eV

NB: kT (RT) ~25meV



Si atoms, intrinsic

As doped Sin-typeother donors: P, Sb

Ga doped Sip-typeother acceptors:B, Al

e.g.: resistivity changes by > 6 orders of mag. with a 1ppm B doping



Basic (active) element of IC’s: transistor

• bipolar transistor

current driven, based on pn junction

npn or pnp

• FET (field-effect transistor)

voltage applied to capacitively coupled electrode (gate) creates an electric field altering the nb of charge carriers in a semiconductor, thus modulating its conductivity (transfer resistor)

technologies for gate electrode

• pn-junction (junction FET or J-FET)

• Schottky barrier (metal-silicon FET or MESFET)

• insulated gate FET, like metal-oxide-semiconductor MOSFET



pn-junction Current vs voltage: diode behavior

Ref. 3

Forward biasedapplied voltage opposed to internal potential difference

Reverse biasedapplied voltage enhances the internal potentialdifference

depletion region shrinks

breakdown



npn-transistor2 diodes back-to-back

Ref. 3

n-type

p-type

n-type



Structure and sign convention of a metal-semiconductor junction

Course Van Zeghbroeck

MESFET technology

metal-semiconductor junction: (Schottky) barrier for electrons and holes

if the Fermi energy of the metal is somewhere between the conduction and valence band edge



Energy band diagram of the metal and the semiconductor

Course Van Zeghbroeck

before contact after contact

thermal equilibrium (Fermi levels adjusted)

animation



Workfunction of selected metals and their measured barrier height (eV) on germanium, silicon and gallium arsenide.

Course B. Van Zeghbroeck



MOSFET technology: MOS capacitor

Ref. 3

Metal (gate) : Al (Mo, W, Cu), Poly-SiOxide : SiO2, d ≈ 1.7-10 nmSemiconductor : p- or n-type silicondoping 1013 - 1018 cm-3

orientation typ. <100>

energy band diagram Al/SiO2/p-Si



MOS capacitor: ideal case

B. Föste, Infineon

Assumptions for the ideal MOS structure:1. No workfunction difference between metal and semiconductor (aligned vacuum and Fermi niveaus)2. charges at any bias exist only in thesemiconductor and at the metal surface3. no carrier transport through the oxide under dc-biasing conditions

i.e. Flat band condition at V=0(potential V between gate and back contact)



B. Föste, Infineon

Real MOS structure:

flatband voltage <> 0 VFB=φMS

MOS capacitor: real case



MOS capacitor

B. Föste, Infineon

p-type semiconductor



MOS capacitor

B. Föste, Infineon



MOS capacitor

B. Föste, Infineon



MOS capacitor

B. Föste, Infineon

gate voltage

control knob for charge carrier nature

(electron/hole) and density at

oxide/semiconductor interface



MOSFET

B. Föste, Infineon



B. Föste, Infineon



B. Föste, Infineon

Vg=0 Vg<>0

two different types of MOSFETs(n-channel)

• depletion type

(on by default)

• enhancement type

(off by default)



n- or p-channel

n-channel (NMOS)

(charge carriers:

electrons)

p-channel (PMOS)

(charge carriers:

holes)

Ref. 1



Refs. 1 & 3

for an enhancement-type MOSFET:



B. Föste, Infineon

CMOS: complementary MOS, today’s most common technology

• n-channel MOS device in series with p-channel MOS device(when NMOS on, PMOS off and vice-versa, hence "complementary")

• simple design• draws very little current (except when switched on)• low-power technology

basic logic gate: inverter

• Vin high (1): NMOS on, PMOS off,

Vout=Vss (low, 0)

• Vin low (0): NMOS off, PMOS on,

Vout=Vdd (high, 1)



CMOS: state-of-the-art

SOI substrate, Cu/low-k interconnection, 5 metal layers, features <0.13mm, 300mm wafers (12 ")

Refs 1 & 3 M. Bohr, Intel



CMOS: state-of-the-art

gate structurevery thin oxide layers

SOI substrate, Cu/low-k interconnection, 5 metal layers, features <0.13mm, 300mm wafers (12 ")

Refs 1 & 3

Nanofabrication, Nano III / mc / 44 http://www.intel.com/technology/silicon/index.htm

TEM cross-sections (Chau et al., Intel)

gate dielectric

state-of-the-art transistors: sub-50nm technology


Nanofabrication, Nano III / mc / 45 H. Xiao, Ref.1

CMOS fabrication steps

example of (simple…?!) CMOS process sequence


…and then contacting.: wire bonding, packaging

H. Xiao, Ref.1

S. Oberholzer

D. Keller


yet…

«The simplest cell (…) is more complex than any machine built by people so far.»

(Maddox, 1998)

Refs 2

scaling down systems is not only about downsizing,it's also about the choice of materials,

the interfaces between materials ("contacts")the geometry / design / architecture of the system


Outline

• Introduction:





– clean-rooms



– etching

– lithography




IC fabrication

clean room

Silicon


IC fabrication

Ref. 3


Outline

• Introduction:





– clean-rooms



– lithography

– etching




importance of yield in industrial processes

clean rooms

• limit contaminants

(air, people, facility, equipment, gas, chemicals, static charges, ….)

• special furniture and tools (paper, pens, ...)

Clean room

CMI, EPFL

grain of salt on a piece of a microprocessor


Clean room

clean room classes

class 1

less than 1 particle of diameter larger than 0.5μm in a cubic foot

"normally clean" appartment:

typ. > 500’000 particles per cubic foot..!

(Federal Standard 209E)


clean room standard (ISO 14644-1)

Cn = 10N (0.1 / D)2.08 Cn maximum permitted number of particles per m3

≥ specified particle size (rounded)N ISO class number ( multiple of 0.1 and ≤ 9)D particle size (micrometers)

ISO 8700100,000100,000

ISO 77010,00010,000

ISO 671,0001,000

ISO 5100300750100

ISO 410307535010

ISO 3137351

≥5 µm≥0.5 µm≥0.3 µm≥0.2 µm≥0.1 µm

ISOequivalent

maximum particles/ft³Class

Clean room

Nanofabrication, Nano III / mc / 550.001 to 30Typical Atmospheric Dust

0.005 - 0.3Viruses

0.01 - 4Tobacco Smoke

0.2 - 3Burning Wood

0.3 - 60Bacteria

0.5 - 15Copier Toner

0.9 - 3Humidifier

0.1 - 1000Metallurgical Dust

1 - 150Auto and Car Emission

1 - 50Smoke from Synthetic Materials

1 - 100Coal Dust

3 - 40Spores

5 - 10Red Blood Cells

8 - 300Tea Dust

30 - 600Saw Dust

40 - 300Human Hair

10 - 1000Textile Fibers

10 - 1000Pollens

100 - 10000Beach Sand

Particle Size(microns)

ParticleClean room


Clean room

H. Xiao, Ref.1

simple clean room design


Clean room

H. Xiao, Ref.1

more advanced clean room design


1. Store personal items.

2. Discard any gum, candy, etc.

3. Remove any makeup with cleanroom soap and water.

4. Take a drink of water to wash away throat particles.

5. Cover any facial hair with a surgical mask or beard/mustache lint-free cover.

6. Put on a lint-free head cover.

7. Clean shoes with shoe cleaners.

8. Put shoe cover on over shoes.

9. Clean any small, pre-approved items to be taken inside.

10. Pick up booties.

11. Sit on "dirty" side of bench.

12. Put on one bootie (over plastic shoe cover).

13. Swing bootied foot to "clean" side of bench.

14. Put on other bootie on "dirty" side.

15. Swing bootied foot to "clean" side.

16. Enter main gowning room.

17. Set aside badge, pager, and any other items to be taken inside.

18. Put on nylon gowning gloves.

19. Obtain bunny suit and belt from hanger.

21. If you've never done it before, putting on a bunny suit can take 30 to 40 minutes. The Intel pros can do it in five.

22. Put on bunny suit without letting it touch the floor.

23. Put on belt.

24. Tuck bunny suit pant legs into booties.

25. Fasten snaps at top of booties.

26. Attach filter unit to belt.

27. Attach battery pack to belt.

28. Plug filter unit into battery pack.

29. Obtain helmet, safety glasses, and ID badge from rack.

30. Put on helmet.

31. Tuck helmet skirt into bunny suit.

32. Zip up bunny suit at shoulders.

33. Attach helmet hose to filter unit.

34. Tighten knob at back of helmet.

35. Put on ID badge.

36. Put on pager.

37. Put on safety glasses.

38. Obtain disposable scope shield.

39. Remove protective covering from both sides of scope shield.

40. Undo front helmet snaps.

41. Attach face shield to helmet.

42. Re-snap front helmet snaps.

43. Examine attire in mirror.

44. Put on latex gloves.

45. Enter the cleanroom.

Steps to enter a cleanroom (Intel)

http://www.intel.com/

Clean room


Outline

• Introduction:





– clean-rooms



– etching

– lithography




Silicon: from sand to wafer

2nd (after oxygen) most abundant in earth’s crusts: 26%

7th most abundant element in universe

14 +IV(+II)

SiSilicon

[Ne]3s23p2

28.085g/mol1410°C 2.33kg/m3



Si: nonmetallic element, indirect

semiconductor

SiO2 glass (amorphous),

quartz (cristalline)

SiC very hard (polishing)

Si crystalline (semiconductor industry)

typical resistivity: 100 mΩ cm

structure: cfc (diamond-like)

C. Heedt, Wacker Siltronic



advantadges of Si over other semiconductors (Ge)

• cheap, abundant

• oxide (SiO2) strong and stable dielectric ( MOS technology); grown easily by thermal oxidation

• larger band gap (1.1 eV): higher operation T

• larger breakdown voltage

Doping elements

• n-type: P (phophorus), As (arsenic), Sb (antimony)

• p-type: B (boron)




Si purification: natural Si oxide MGS EGS

metallurgical electronic grade




Si purification: MGS EGS




EGS single cristal ingot: CZ growth (Czochralski method)




Si ingot

up to 300mm diameter (FZ or floating zone purer butlimited to 200mm)



Surface grinding

flat: up to 150mm

notch: > 200mm

mark crist. orient.





wafer sawing

edge rounding



Ref. 1

wafer finishing

• lapping

(global planarization, double-sided)

• wet etching , isotropic

(4:1:3 mixture of HNO3, HF and CH3COOH)

• CMP (chemical mechanical polishing)

• wet cleaning (RCA1, RCA2)

surface roughness after the various treatment



Ref. 1

wafer flats

• Orientation for automatic equipment

• Indicate type and orientation of crystal.

Primary flat – The flat of longest length located in the circumference of the wafer. The primary flat has a specific crystal orientation relative to the wafer surface.

Secondary flat – Indicates the crystal orientation and doping of the wafer. The location of this flat varies.

flat at 180 deg for n-type and 90 deg for p-type

flat at 45 deg for n-type, no secondary for p-type

www.ee.byu.edu/cleanroom



Ref. 1

Miller indices description of lattice planes and lattice directions in crystal

example cubic lattice system

the direction [hkl] defines a vector direction normal to surface of a particular plane or facet.

www.ee.byu.edu/cleanroom

type: <100>Equivalent directions:[100],[010],[001]

type: <110>Equivalent directions:[110], [011], [101],[-1-10], [0-1-1], [-10-1],[-110], [0-11], [-101],[1-10], [01-1], [10-1]

type: <111>Equivalent directions:[111], [-111], [1-11], [11-1]


Outline

• Introduction:





– clean-rooms



– etching

– lithography



additivesubstractive


Fabrication: material deposition techniques

Physical processes

• Physical Vapor Deposition (PVD):

basics of film deposition

thermal evaporation

molecular beam epitaxy (MBE)

pulsed laser deposition (PLD)

sputtering

• Casting

Chemical processes

• Chemical Vapor Deposition (CVD)

• Atomic Layer Deposition (ALD)

• Electrodeposition

• Langmuir-Blodgett films (LB)


Fabrication: physical deposition techniques

fundamentals of film deposition

• gas kinetics

(mean free path: small holes filling, residual gas atoms: purity)

• UHV (p<10-9 mbar) necessary depending on final purity needed

• phase diagrams of materials to deposit (pressure, temperature)

• control type of growth: homoepitaxy; heteroepitaxy; growth of polycristalline or amorphous layers;

importance of strain misfit dislocations

substrate temperature



• gas kinetics

(mean free path: small holes filling, residual gas atoms: purity)

table for residual air at 25°C



• UHV (p<10-9 mbar) necessary depending on final purity needed

Rough Vacuum High Vacuum Ultra-High Vacuum

760 to 10-3 torr 10-3 to 10-8 torr 10-8 to 10-12 torr

load locks evaporation surface analysis

sputtering ion implantation molecular beam

epitaxy (MBE)

reactive ion etching

(RIE)

low pressure chemical

vapor deposition (LPCVD)

NB: 1 torr = 1.33 mbar = 1mm Hg



• phase diagrams of materials to deposit (pressure, temperature)e.g.: YBa2Cu3Ox

CuO2 plane

yttrium

baryum

oxygen

copper

ab

c

Cu(1)

Cu(2)

O(1)

O(2)

O(3)

O(4)(apical)

6.0 6.2 6.4 6.6 6.8 7.0

100

200

300

400

500

Oxygen content: x

TN [

K]

50

100

150

200

250

MetallicOrthorhombic

InsulatingTetragonal

Antiferro-magnetic Superconducting

Tc [K

]



• type of growth: homoepitaxy

IBM AlmadenSTM image, 28nm by 28nm area of the terraced copper and copper nitride surface with Manganese humps (1-10 atoms long).



• heteroepitaxy

small mismatch large mismatch

Frank-Van der Merwe Volmer-Weber Stranski-Krastanov

(layer growth; ideal) (island growth) (layers then islands due to strain build up)



• importance of strain misfit dislocations: T

strained layer

substrate


Fabrication: thermal evaporation

thermal evaporation: free, isotropic (Langmuir)

resistance heated evaporation sources: wires, boats

• Simple, robust, widespread • T ~ 1800°C• Use W, Ta, or Mo filaments to heat evaporation source.

• Typical filament currents are 200-300 Amperes.• Exposes substrates to visible and IR radiation.• Typical deposition rates are 1-20 Å/s.• Common evaporant materials:– Au, Ag, Al, Sn, Cr, Sb, Ge, In, Mg, Ga– CdS, PbS, CdSe, NaCl, KCl, AgCl, MgF2, CaF2, PbCl2



thermal evaporation: free, isotropic (Langmuir)

e-beam evaporation

• More complex, but extremely versatile.• T > ~ 3000°C• Use evaporation cones or crucibles (e.g. graphite) in a copper hearth.

• Typical emission voltage is 8-10 kV.• Exposes substrates to secondary electron radiation.

– X-rays can also be generated by high voltage electron beam.

• Typical deposition rates are 1-100 Å/s• Common evaporant materials:– Everything a resistance heated evaporator will accommodate, plus:

– Ni, Pt, Ir, Rh, Ti, V, Zr, W, Ta, Mo– Al2O3, SiO, SiO2, SnO2, TiO2, ZrO2



thermal evaporation: ~ directional

effusion (Knudsen) cell

evaporation rate ~ controlled by temperature only(play with equilibrium vapor pressure and aperture size)

NB: distribution of vapor beam intensity; depends on ratio L/d (filling level of cell !)

Biasiol and Sorbia, 2001



NB: shadow effects / step coverage

directionality and adhesion effects


Fabrication: Molecular Beam Epitaxy (MBE)

Ref. 3 & J.Faist

excellent control on layer compostion

- source: effusion cells- multiple cells/shutters- UHV ( in-situ surface characterisation techniques possible)

- epitaxy (heated substrate)


Fabrication: Molecular Beam Epitaxy (MBE)

Molecular Beam Epitaxy (MBE)

J.Faist, ETHZ

TEM pictures of a QCLGaAs/AlGaAs structure(J. Faist, ETHZ)


Fabrication: Pulsed Laser Deposition (PLD), laser ablation

- source: target, thermal energy (laser pulse ~ few J/cm2)

- multiple target possible (YBCO/PBCO)- typ. oxide films- epitaxy (heated substrate)- off-axis geometry (rotating substrate)


Fabrication: Sputtering

DC sputtering

• few 100V plasma (p~10-1 - 10-3mbar)

• sputtering of target by ions, typ. Ar+

(binding energy of target atoms: 4-8eV; min energy of Ar+ ions: 20-50eV; multiple collisions necessary)

• stoichiometry of target (~) preserved

• increase ionization rate of plasma with B-field (magnetron sputtering)

• insulating targets: RF-sputtering (~13MHz)

(erosion)


Fabrication: Casting

Casting (spinning)

(typ. polymers, e.g. photoresists, polyimide)


Fabrication: material deposition techniques

Physical processes

• Physical Vapor Deposition (PVD):

thermal evaporation

molecular beam epitaxy (MBE)

pulsed laser deposition (PLD)

sputtering

• Casting

Chemical processes

• Chemical Vapor Deposition (CVD)

• Atomic Layer Deposition (ALD)

• Electrodeposition

• Langmuir-Blodgett films (LB)


Fabrication: Chemical Vapor Deposition

Chemical Vapor Deposition (CVD)

def: reaction of chemicals (precursors, gas phase) at high T

to form the deposited thin film

SiO2 3 SiH4 + O2 SiO2 + 2 H2 450°C

SiO2 SiCl2H2 + 2N2O SiO2 + 2 N2 + 2HCl 900°C

Si3N4 3 SiH4 + 4NH3 Si3N4 + 12 H2 700°C-900°C

poly Si SiH4 Si + 2 H2 580-650°C, 1mbar

LPCVD: low-pressure CVD; requires higher temperaturesPECVD: plasma enhanced CVD, allows temperature reductionMOCVD: metal-organic CVD, use organometallic precursors

CMI, EPFL

note: stress can be critical (nitride layers)


Fabrication: chemical deposition techniques

note: thermal oxidation (note really a deposition process, Si consumed during process)

better oxide quality, very low density of defects, homogeneous thickness (gate – insulating - material)

dry Si (solid) + O2 (gas) SiO2 (solid)

wet Si (solid) + H2O (steam) SiO2 (solid) + 2H2 (gas)

final thickness: few x 10Å to 2μm (NB: native oxide layer: ~ 2nm)

T ~ 900°C – 1200°C

limited to materials able to form oxides



thermal oxidation xox(t) ∝ [1+c(t+τ)]1/2

(Deal-Grove)



note: in similar ovens: doping(diffusion process)

T ~ 800°C


self-limiting growth

Beneq

Fabrication: Atomic Layer Deposition (ALD)


A: Hydroxylated surface

B: Trimethylaluminium (TMA) reacts with OH

C: TMA does not react with itself (passivation)

D: Purge reactor

Cambridge Nanotech



E: H2O removes CH3and passivates

F: Purge reactor

G: Ready for new cycle

Repeat A-G for controlled monolayer deposition


Cambridge Nanotech


typical conditions

• Pressure 0.1-5 mbar

• Temperature 60-500ºC

• Gas flow 0.3-1.0 SLM (std liter / min.)


variety of materials

• Oxides (e.g. Al2O3, HfO2, TiO2, ZrO2 , Y2O3)

• Nitrides (e.g. AlN, TiN, WxN)

• Sulfides (e.g. ZnS, CaS)

• Fluorides (e.g. ZnF2, SrF2)

• Metals (e.g. Pt, Ir, Pd)

• Doped materials (e.g. ZnS:Mn, ZnO:Al)

• Polymers (polyimides)

• Biocompatible thin films (hydroxyapatite)

Coating uniformity

Beneq



CVD example: carbon nanotubes growth

(CH4, C2H4, C2H2...)


hydrcarbon gases: C2H2 (acetylene), C2H4 (ethylene), CH4 (methane) (+ …)

carrier gases: H2, Artemperature: 600-1000C catalyst: Fe (Ni, Co)

CVD example: CNTs


1μm

~2nm

SWNTs

Fe, ethylene, 900C-1000C

see e.g.: Dai et al. and Hafner et al.


lithographically patterned Fe film, acetylene, 600C-700C


• length of tubes vs time, flow and thickness

• SEM image perp. to SiO2/Si surface

0 5 10 15 20

20

40

60

80

100

120

Leng

th (

µm)

Fe thickness [nm]

0 5 10 15 20

60

80

100

120

Leng

th (

µm)

C2H

2 Flow [sccm]

0 5 10 150

20

40

60

80

100

120

Leng

th (

µm)

Growth Time [min]

Z. Liu et al., 2002


M. Perrin et al.,


M. Perrin et al.,

applications: - composite materials- carbon-based super-capacitors(large surface to volume ratio)

- …


Fabrication: Electrodeposition (electroplating)

- typ. for thick (>μm) metallic layers - solution with reducible form of metal (electrolyte)- sample at cathode (neg. potential)

e.g. Cu2+ + 2e- Cu (solid)incorporation of the reduced metal in the substrate

- NB: in pores deposition of wires

note:- substrate is conducting- deposition of same material as substrate (seed layer)



Electrodeposition of metallic nanowires

L. Grüter et al., (PhD thesis, 2005)



L. Grüter et al., (PhD thesis, 2005)

SEM picture of Au wires on a Si substrate(electrochemical template synthesis)

Au wires after etching off the Ni. NB: deposition time for Ni: 33 s at V= -0.9 V in both cases. Gaps: (a) 25 nm and in (b) 60 nm


Fabrication: Langmuir-Blodgett (LB) technique


additive techniques: short summary

PVD: physical vapor deposition

film growth mass transport from source to substrate; epitaxial growth possible (temperature, phase diagrams, vacuum)

source - thermal evaporation (boat, e-beam, effusion cell, laser pulse)

- sputtering

CVD: chemical vapor deposition

film growth deposition of material in gas phase after a temperature controlled chemical reaction of the component chemicals

source precursor gases


Outline

• Introduction:





– clean-rooms



– etching

– lithography



additivesubtractive


Fabrication: etching

Chemical:

• wet etching (can be anisotropic due to crystal-face selectivity)

• fast, up to 10μm/min or more

Physical etching (sputtering)

• ion milling, FIB (focused ion beam)

• dry etching (plasma assisted techniques, pressures up to 10mbar)

(more a combination of physical and chemical material removal)

• slower, typ. 100Å -1000Å/min

key points:

selectivity (etch rates ratio of masking layer and layer to etch)

directionality (defines etch profile)

note:

CMP, chemical mechanical polishing to achieve global planarization

combine mechanical abrasion with chemical etching; key parameters: force, slurry type, pad velocity

Nanofabrication, Nano III / mc / 113 http://www.memsguide.com

Fabrication: wet etching

• use chemical solutions to dissolve material

• chemical species react with surface etch products rinse, dry

isotropic, typ. 10μm/min

anisotropic, typ. 1μm/min



SiO2 6:1, buffered in NH4F (BHF) or 10:1 to 100:1 (by vol.) HF in H2O

(NB: 1:1 HF (49% HF in H2O) too fast)

SiO2 + 6 HF → H2SiF6 + 2 H2O (H2SiF6 soluble in H2O)

BHF etch rate: 1000Å/min (room temperature)

masks: photoresist, silicon nitride

Si polycrystalline or single-crystal

isotropic: mix of HNO3 and HF

(cyclic process: HNO3 oxidizes Si, HF removes oxide)

Si + HNO3 + 6 HF → H2SiF6 + HNO2 + H2O + H2



Si anisotropic (cystalline Si): (100) rate / (111) rate ~ 100 at 80°C

e.g.: KOH

23.4% wt, C3H8O 13.3% wt (isopropyl alcohol), H2O 63.3% wt

Si + 4 OH- → Si(OH)4 + 4 e-

exposes slow planes (111)

(~not attacked by etchant)

V-shaped (or trapezoidal)

groove for (100) wafers

vertical trench for

(110) wafers

(110)



MicroChemicals



Si3N4 H3PO4 91.5% concentration at 180°C (etch rate ~ 100Å/min)

Si3N4 + 4 H3PO4 → Si3(PO4)4 + 4 NH3

silicon phosphate (Si3(PO4)4) and amonia (NH3) are water soluble

selectivity to

thermally grown SiO2 > 10:1

Si > 33:1

metals Al mix of acids (phosphoric, acetic, nitric) and water

Ti mix of sulfuric acid and hydrogen peroxide

NB: selectivity multilayers including stop layer for etching: well-defined wells


Fabrication: dry etching

dry etching: usually plasma based

as compared to wet etch:

- smaller undercut (patterning of smaller lines)

- higher anisotropicity (high aspect-ratio structures possible)

- less selective

- mask etching not negligible

ion milling

purely physical

sputering by accelerated Ar+ ions

p ~ 10-4 – 10-3 torr;

etch rate: few nm/min

note: no selectivity



RIE: reactive ion etchingphysical and chemical

Si etch with SF6

- accelerated ions (e.g.: Ar+, directional) either modify surface state (e.g.: bond

breaking, makes surface more reactive) or help etch products to desorb

- reactive species (e.g. plasma generated from from SF6) diffuse to substrate surface and react, forming SiF4 (volatile)

SF5+

F-



recipes, cf:

T. J. Cotler, M. E. Elta: Plasma-etch technology, IEEE Circuits & Devices Mag. 6 (1990) 38–43



DRIE (key process for MEMS)

deep reactive ion etching

ICP RIE

SF6 alternated with C4F8 (to passivate walls), Bosch process

selectivity

Si:SiO2, 150:1

profile angle +/- 1°



Focused Ion Beam (FIB)

• controlled, directed heavy ion beam (typ. Ga)

• local ion milling (sputtering)

• fine structures, nm range

SEM/FIB (FEI Nova 600 nanoLab)

Electrons• are very small, inner shell reactions• High penetration depth• Low mass -> higher speed for given energy• Electrons are negative• Magnetic lens (Lorentz force)

Ions• Big -> outer shell reactions (no x-rays)• High interaction probability, less penetration depth• Ions can remain trapped -> doping• High mass -> slow speed but high momentum milling !!!• Ions are positive• Electrostatic lenses

IBM



Pavius et al., CMI EPFL

FIB operating modes



Pavius et al., CMI EPFL

milling

local cross-sectioning of IC's (Uni Erlangen)


Fabrication: etching, short summary

Chemical:

• wet etching (can be anisotropic due to crystal-face selectivity)

Physical etching (sputtering)

• ion milling, FIB (focused ion beam)

• dry etching (plasma assisted techniques, pressures up to 10mbar)

(more a combination of physical and chemical material removal)

key points:

selectivity (etch rates ratio of masking layer and layer to etch)

directionality (defines etch profile)


Outline

• Introduction:





– clean-rooms

– Silicon: from powder to wafer


– etching

– lithography




lithography: Greek lithos "stone" + graphein "write."

definition: method to define a pattern on a substrate

typ.: pattern engraving on print block, inking and transfer to paper(1st process, Senefelder, 1798)

• first synthetic photo-polymer: 1935, Eastman Kodak


lithography

overview of lithography process

• Surface Preparation• Coating (Spin Casting)• Pre-Bake (Soft Bake)• Alignment• Exposure• Development• Post-Bake (Hard Bake)• Processing Using the Photoresist as a Masking Film• Stripping• Post Processing Cleaning (Ashing)


lithography

R.B. Darling

Wafer cleaning

Typical contaminants that must be removed prior to photoresist coating:

• dust from scribing or cleaving (minimized by laser scribing)• atmospheric dust (minimized by good clean room practice)• abrasive particles (from lapping or CMP)• lint from wipers (minimized by using lint-free wipers)• photoresist residue from previous photolithography (minimized by

performing oxygen plasma ashing)• bacteria (minimized by good DI water system)

• films from other sources:– solvent residue– H2O residue– photoresist or developer residue– oil– silicone


lithography

R.B. Darling

Wafer cleaning

• Standard degrease:– 2-5 min. soak in acetone with ultrasonic agitation– 2-5 min. soak in isopropanol with ultrasonic agitation– 2-5 min. soak in DI H2O with ultrasonic agitation– 30 sec. rinse under free flowing DI H2O– spin rinse dry for wafers; N2 blow off dry for tools and chucks

• For particularly troublesome grease, oil, or wax stains:– Start with 2-5 min. soak in 1,1,1-trichloroethane (TCA) or

trichloroethylene (TCE) with ultrasonic agitation prior to acetone

• Hazards:– TCE is carcinogenic; 1,1,1-TCA is less so– acetone is flammable– methanol is toxic by skin adsorption


lithography

R.B. Darling

Wafer priming

• Adhesion promoters are used to assist resist coating.

adhesion factors:• moisture content on surface• wetting characteristics of resist• type of primer• delay in exposure and prebake• resist chemistry• surface smoothness• stress from coating process• surface contamination

• for silicon:– primers form bonds with surface and produce a polar (electrostatic) surface– most are based upon siloxane linkages (Si-O-Si)

1,1,1,3,3,3-hexamethyldisilazane (HMDS), (CH3)3SiNHSi(CH3)3


lithography

R.B. Darling

Spin coating of photoresist


lithography

R.B. Darling

Prebake (soft-bake)

Used to evaporate the coating solvent and to densify the resist after spin coating.

• Typical thermal cycles:– 90-100°C for 20 sec. in a convection oven– 75-85°C for 45 sec. on a hot plate

• Commercially, microwave heating or IR lamps are also used in production lines.

• Hot plating the resist is usually faster, more controllable, and does not trap solvent like convection oven baking.


lithography


Different types of lithography

Ref. 3

radiation source

illumination control system

resist coated sample

DLW


Optical lithography

Ref. 3

DUV: 157nm-250nm

EUV: 11nm-14nm

x-ray: < 10nm

source wavelengths:

optical: > 450nm

UV: 365nm-435nm


Optical lithography

masking methods

Ref. 3

contact

mask deteriorates

Minimum Feature Size

MFS ~ (dλ)1/2

proximity

poorer resolution

MFS ~ [(d+g)λ]1/2

projection

better resolution(diffrac. limited)

MFS ~ 0.61 λ/NA

reduction possible (decreases errors),

stepper (multiple exp.)

mask deteriorates


Optical lithography

phase-shifting technique

destructive interference


Optical lithography

photoresists

positive: develops at exposed areas

made soluble upon exposure

(chain scission)

e.g. PMMA (DUV, e-beam), DQN

negative: stays at exposed areas

initiates cross-linking of side chains

or polymerization of mono-/oligomericspecies

e.g. maN400

Ref. 3


Optical lithography


Optical lithography


Optical lithography


Optical lithography


Optical lithography

Postbake (Hard Bake)

Used to stabilize and harden the developed photoresist prior to processing steps that the resist will mask.

• Main parameter is the plastic flow or glass transition temperature.

• Postbake removes any remaining traces of the coating solvent or developer (eliminates the solvent burst effects in vacuum processing).

• Postbake introduces some stress into the photoresist; some shrinkage of the photoresist may occur.

• Longer or hotter postbake makes resist removal much more difficult.

NB: Postbake is not needed for processes in which a soft resist is desired, e.g. metal liftoff patterning.


Optical lithography

photoresists profiles(after development)

Ref. 2

R: developing rate of exposed region

R0: developing rate of unexposed region

R/R0 > 10: fast developper

γ: resist contrast

(linked to exposure dose, cf Madou)


Optical lithography

Example: lift-off process, undercut controlma-N 400 negative resist (micro resist technology), 2 µm thickness

micro resist technology

Effect of exposure time

tE 90 s,0 µm undercut

tE 100 s,0,5 µm undercut

tE 140 s,1,5 µm undercut


EUV lithography (R&D)

reflection optics(for λ=10-15nm: no transparent enough materials for lenses)

Ref. 3


x-ray lithography (R&D)

X-ray Interference Lithography (XIL)NB: same problem as EUV, no lenses

J. Gobrecht, H. Solak et al.



X-ray Interference Lithography (XIL)NB: same problem as EUV, no lenses

• frequency multiplication: factor depending on the diffraction orders chosen (2x for 1st order).• fransmission grating patterned with e-beam• coherent beam

J. Gobrecht, H. Solak et al.

EUV: λ=13.5 nm feature size: 3.5 nm



J. Gobrecht et al.



H. Solak et al.

typ. exposure param. for PMMAfield up to 3mm wide (coherence limited)10 sec exposure, λ=13.4nm

“world record “for photon-basedlithography

positive tone negative tone



multiple beam interference

H. Solak et al.


electron beam lithography (EBL)

precise (energy, dose)relatively slow (industrial application: parallel beams)resolution limit ~ 10nm (50nm)no masklarge DOF

large scattering of electrons

Refs. 1 & 3


proximity effects

J. Gobrecht, PSI




dose test on PMMA: overcut to undercut (A. Kleine) note: undercut critical for lift-off



EBL compared to optical/UV lithography

+ precise control of dose delivery

+ fast beam deflection and modulation

+ smaller spot on resist (<10nm) as compared to light (500nm), increased resolution

+ no mask needed (direct writing, "software" mask)

+ large depth of focus

- strong electron scattering in solids (practical resolution > 10nm)

- operation in vacuum (electron beam)

- slow exposure speed (scanning)

- high cost


lithography: short summary

• optical (mask contact or projection)

• electron beam (direct writing)


soft lithography and more "exotic" techniques

B. Michel et al., Advanced Semiconductor Lithography, 2001

polydimethylsiloxane (PDMS)(e.g Sylgard 184, DOW Corning)

microcontact printing (MCP)

Nanofabrication, Nano III / mc / 159B. Michel et al., Advanced Semiconductor Lithography, 2001



Nanofabrication, Nano III / mc / 160B. Michel et al., Advanced Semiconductor Lithography, 2001

• first used to print alkanethiols on gold surfaces

• quick and cheap method to perform simple assays (e.g.: immunoassay: crossed stamped lines)

master

stamp

printed and etched pattern





source: J. Gobrecht

First SPM lithographyJ. Gobrecht and J. Pethica1986

Scanning Probe Microscope - based lithography

AFM LithographyTh. Jung, H. Hug et al. 1989



STM lithography

Th. Jung et al.



J. Gobrecht

Hot embossing: the principle



J. Gobrecht

Hot embossing: nanoreplication in polymers

(NB: plasma etchbefore eavporation)

S. Chou, 1998



Materials Today, June 2007

Multiphoton polymerization

Fig. 1 Fluorescence in a rhodamine B solution excited by single-photon excitation from a UV lamp (left) and by TPA of a mode-locked Ti:sapphire laser tuned to 800 nm (right). In the former case, the integrated intensity is equal in all transverse planes, while in the latter case the integrated intensity squared is peaked in the focal region. (Reprinted with permission from3. © 2007 Wiley-VCH.)



Materials Today, June 2007

Multiphoton polymerization


Outline

• Introduction:





– clean-rooms

– Silicon: from powder to wafer


– etching

– lithography

– examples of devices


Si nanowires: SOI wafers

~100 nm1 - 10 μm

500 μm150 nm

60 nm80 nm

• Silicon on Insulator, thermal oxidation

• Cr mask

• Plasma etch: CHF3,

• Cr removed: KMnO4, NaOH

• Si etched: TMAH

• Contacts etched: HF

• Al contacts: deposit & anneal

Si

SiO2


Si nanowires: SOI wafers

D. Keller, O. Knopfmacher


Si nanowires

D. Keller, O. Knopfmacher

• processes: thermal oxidation, spinning (resist), lithography (optical + e-beam), metallization (Cr mask, with e-beam), dry etching (RIE SiO2 with CHF3), Cr mask stripping (in solution) and wet etching of Si (NB: 1st wet etch of SiO2 surface oxide and then Si), annealing (contact improvement).


-10 -8 -6 -4 -2 0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

Vg (V)

Vpt

(V

)

pH 7

-10 -8 -6 -4 -2 0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

Vg (V)

Vp

t (V

)

pH 4

G (S)

5.000E-10

1.581E-9

5.000E-9

1.581E-8

5.000E-8

1.581E-7

5.000E-7

Si nanowires


molecular electronics: contacting molecules

mc, J. Seminario

VA

?~ 2 nm


200nm

1mm

Nanogaps fabrication

• UV + e-beam lithography• angle evaporation

PMMA-MA

PMMA

SiO2

0° a

wireaxis

10 – 20 nm gapsgold 15/50 nm thick

„direct“ nanogaps

L. Bernard et al.


AC field : 1Mhz, 106-107 V/m

dielectrophoresisinteraction “induced dipole moment / applied electric field”

positive dielectrophoresis(particles with higher permittivity than medium: force towards the highest intensity of the field)

2

2DEPF V Eα

= ∇r r r%

3 ( )

2m p m

p m

ε ε εα

ε ε−

=+

% 0i i jσε ε εω

= −%

34

3V dπ=

trapping: dielectrophoresis

L. Bernard et al.


Ti/Au electrodes

SiN

SiO

F. Dewarrat et al., Single Molecules, 2002

structure for DNA manipulation


break junctions

• microfabricated junctions: e-beam lithography

phosphor bronze / polyimide / Au oxygen plasma underetched

• elongation: e= 6thz/L2

reduction factor: r=e/z ≈ 1/100'000

mechanically controllable break junction

z

suspended metallic bridge

24mm

T. Gonzalez et al.


transfer of the film to a PDMS stamp

stamping on solid substrate: patterned array

PDMS PDMSPDMS

PDMS

PDMSA. master

fabrication

B. stamping

example: colloids arrays for molecular electronics


example: colloids arrays for molecular electronics

"stamper": Jon Agustsson


b

c d

Patterned nanoparticle array

SiO2/Si

patterned colloids arrays

60°

J. Liao et al.


C8 C12 C16

arrays structure

dC8 = 2.4 ± 0.1nm

lC8 ~ 1.3nm(overlap ~ 2Å)

dC16 = 3.3 ± 0.1nm

lC16 ~2.3nm(overlap ~ 13Å)

dC12 = 3.1 ± 0.1nm

lC12 ~1.8nm(overlap ~ 5Å)

C8 C12 C16


contacting

SiO2

Si

patterned arrays

evaporated contacts

• TEM grid as shadow mask

• e-beam metal deposition

(5nm Ti / 40-60nm Au)

20μm20 mμ

a l

w


molecular exchange

formation of an inter-linked network of particles by incorporation of the thiolatedOPE

stable array (no aggregation)

~ "breadboard"

Ar

1mM OPEin THF, 24h

OPE: A. Pfalz, Basel


a “switch” molecule: light

reversible switching on Au surface: Katsonis et al., Adv. Mat., 2006

λ1 > 420 nm (vis)

λ2 = 313 nm (UV)

"ON"

"OFF"

Nanofabrication, Nano III / mc / 184 S. vd Molen, J. Liao et al.,

"ON"

(closed)

"OFF"

(open)

0 100 200 300 400 5002.0

2.2

2.4

2.6

2.8

3.0

3.2 visUVvis UVvis UVvis UVvis UVvis

G (

nS)

meas. cycle # (1cycle = 30s)

switch is on

a “switch” molecule: light


oxidation: FeCl3 (iron chloride)

reduction: Fe(C2H5)2 (ferrocene)

S. Decurtins et al.

a “switch” molecule: redox


preliminary results

C8 TTF (0)TTF ox (2+)TTF red (0)

experiment: exchange oxidation reduction

J. Liao, J. Agustsson, S. Wu et al.,

a “switch” molecule: redox


colloid arrays: platform for molecular electronics

m mm μm nm


MEMS/NEMS and devices

from MEMS (micro-electromechanical systems) …

e.g. Si gears for watch industry: lower friction and inertia

CSEM & Ulysse-Nardin



• electrostatic micromotorfabricated from silicon

Physics World, Feb. 2001

• individual mechanical micromirrors part of a Texas Instruments Digital Light Processor (MOEMS)



fabrication process for such structures


structural layer sacrificial layer substrate





… down to NEMS

• masses in 10-15g to 10-18 g range (∝ L3)

• resonators above 10GHz (∝ 1/L)

(f ~ (spring cst/eff. mass)1/2, spring constant ∝ L)

• very low power: 10-18W threshold (thermal fluc. at 300K)

• low dissipation, high Q factor: sensitive to damping sensors

(sensitivity potentially reaching quantum limit)

• NB: 10x10x100 nm Si beam contains ~ 5 x 105 atoms,

among which ~3 x 104 reside at the surface

(i.e.: > 10% of the constituents are surface or near-surface atoms)




nano-tweezers:

electrostatic actuation

actuation amplitude

down to 6 pm (rms)/ sqrt(Hz)

Ch. Meyer, H. Lorenz, and K. Karrai, "Optical detection of quasi-static actuation of nanoelectromechanical systems" Appl. Phys. Lett. 83, 2420 (2003).

Nanofabrication, Nano III / mc / 194 Fuhrer, Zettl et al., Nature 2004

300 nm

stator (control electrodes)

rotor (metal)

axis (CNT)

anchor




Nanomechanical Electron Transport:

quantum-bell: max current at fdrive~ resonance freq.

A Erbe, Ch Weiss, W Zwerger, and R H Blick, Phys. Rev. Lett. 87, 096106 (2001) M Jonson and R Shekhter, Phys. World 16, 21 (2003).

avg nb of e- shuttled per cycle

videos


Integration: hybrid devices

Tech. Roadmap for Nanoelectronics, IST program, European Commission

fabrication of ic 7

Documents

gates nanofabrication

intel introduction state

infineon introduction

outline introduction

al lines nanofabrication

information technology

vlsi technology

intel anounces