ic fabrication process - how to fabricate an ic on a silicon chip and its diagrams?

7/23/2019 IC Fabrication Process - how to fabricate an ic on a silicon chip and its diagrams?

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IC Fabrication Process:An integrated circuit consist of a single crystal chip of

silicon. Containing both active and passive elements, and their interconnection.The basic structure of an IC consist of four layers of materials, such that:

1. Substrate

2. Epitaxial growth3. Diffusion4. Metallization

Substrate:The p-type silicon bottom layer (6 mils thick) and serves where the

integrated circuit is to be built known as Substrate.

Epitaxial growth:The second n-type layer (25µm=1mil)where all active and

passive component are built, which is grown as a single crystal extension is called

Epitaxial growth.

Diffusion:The third layer of IC fabrication is Diffusion process. Active and

passive component are made by diffusing p-type and n-type impurities. Theselective diffusion of impurities is accomplished by using SiO2 as a barrier.

Metallization:Finally a fourth material (aluminum) Layer is added to supply the

necessary interconnection between components. It provided contact among thecomponents Al is used for metallization.

Diode Fabrication:

Transistor Fabrication:



FET Fabrication:

Capacitance Fabrication:

Resistor fabrication:



CMOS Fabrication:

MOSFET Fabrication:

Monolithic IC:



IC characteristics / Elimination:

1. Typical value of Resistance 10 Ω < R < 30 k Ω & Capacitance <30pf.2. Poor tolerance typical value is 10% only.3. High thermal co-efficient & voltage resistive.4. No transfer & inductor can be fabricated.5. Higher cost for small scale production.

Design rules for monolithic layout: These following ten design rules are stated by Phillips:

1. Redrawn per connection with the minimum crossover.2. Determine the no of isolation islands and reduce the areas as much as

possible.3. Place all resistors having fixed potential and return that isolation to the

most positive potential.4. Connect the substrate to the most negative potential of the circuit.5. In layout allow an isolation border equal to twice the epitaxial thickness.6. Use 1-mili widths for emitter regions and ½ -mil width for base contacts

and for collector contacts and spacings.7. For resistors use widest possible designs consistent with limitation die size.8. Always optimize the layout arrangement to maintain the smallest die size

and if necessary, compromise pin connections.9. Determine component geometries from the performance requirements of

the circuit.10.

Keep all metalizing runs as short and as wide as possible, particularly atthe emitter and collector out put connections.

Work out Example:

Solution:



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ic fabrication process - how to fabricate an ic on a silicon chip and its diagrams?

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