ese 570 fabrication of cmos integrated circuitsese570/spring2015/ese570... · 2015. 1. 22. ·...

ESE 570 FABRICATION OF CMOS INTEGRATED CIRCUITS

Kenneth R. Laker, University of Pennsylvania, updated 22Jan15 2


Crystal Puller with rotation mechanism

Crystal Seed

Quartz Crucible Heat

Shield

Molten Polysilicon

Ingot Wafer

Water Jacket

Heating Element

Image from Quirk & Serda

Single-Crystal Silicon

● 2010: 300 mm (12 in.) diameter wafers● 2016: 450 mm (18 in.) - goal


The ROI of 450mm wafers however is compelling. A 450mm fab with equal wafer capacity to a 300mm fab can produce 2x the amount of die. A rough calculation of die cost: a 14nm die from a 450mm wafer will cost 23% less than the same die from a 300mm wafer.

Silicon Wafer Manufacturing

Si Ingots

Si Wafers300 mm(12 in.)

450 mm (18 in.)


mask (e.g. metal)

UV light illumination

field area is actually opaque

lens

unexposed die

exposed dieSi wafer coated with photoresist

wafer scan direction


PHOTOLITHOGRAPHY


CMOS Processing Technology

time = 60 stime = 0 s

Boron atoms deposited on

surface


CMOS Processing TechnologyION IMPLANTATION

N keV

DepthDepth (µm)

0 0.5 1.0 1.5

B in Si Dose: 1015 cm-2

Con

cent

ratio

n (c

m-3) 1*1020

0.5*1020

0

50 keV

200 keV100 keV

400 keV

Boron (B)

Advantages of Ion Implantation Precise control of dose and depth profile. Low temperature process (can use photoresist as mask)


Acceptors

Metalloids

Chemical Periodic Table

American Chemical Society (ACS)

Donors

Boronatom

Freehole

Phosphorus atom

Freeelectron

Electrons shared by neighbor atoms

5

Doping of Semiconductors

85At


(d)

Si3N

4


Wdrawnn+ n+

p substrate (bulk)

n+ n+G

S D

polygate

S D

gateoxide

Leffective

metal 1

Ldrawn

field oxide

Physical Structure Layout Representation

Schematic Representation

Ldrawn


nMOS Transistor from a 3D Perspective

GateOxide

FieldOxide

FieldOxide

P-TypeSource/Drain

Regions


nMOS Transistor

nMOS Transistor

metalroute


To eliminate the opportunity to create parasitic transistors: 1. “p+ Channel Stop Implant” is introduced in areas where there are to be absent nMOS transistors.2. Increase the the field oxide in areas to be absent nMOS transistors.


Grow field oxide. Create contact window, deposit & pattern metal film.


p+ channel stop implant

channel stop


Substrate contact

VDD


C. Bipolar Transistors


High-K Dielectric Metal gate MOSFET

MOSFET TECHNOLOGY INNOVATIONSiO

2 Dielectric Poly gate MOSFET

High-K 3D Tri-Gate MOSFET (Intel)

22 nm

High-K Dielectric

=HfO2

Dielectric constant = 25

Dielectric constant = 3.9

Source

Drain


Contacts and Vias in CMOS Fabrication

Enhanced Feature

1

2

1

2


Poly-silicide or Silicide = metallurgical combination polysilicon and a refractory metal


L

W


p = substrate p = substrate

p+ p+

Field oxide Capacitor oxide

metal

High-k capacitor oxide

Planar Capacitor(metal-p+)

“Trench” Capacitor(metal-p+)

MORE CMOS CAPACITORS

p+


Metal 1 & Metal 2


PHYSICAL LAYER: Design Rules are a set of process-specific geometric rules for preparing layout artwork to enable the layout to be manufacturable, i.e. preserve all of the circuit structures and feature geometries intended by the chip designers.

PURPOSE: Realize fabricated chips that are die area efficient and manufacturable by balancing the conflicting objectives to minimize die area and maximize yield.

DESIGN RULE WAIVER: Explicit permission granted by the fabrication organization to the design organization to violate certain design rules or to allow certain design rule errors on a given design (IP or chip).

. Permits first-order scaling and tend to be more conservative than 'micron' rules.


To be able to tolerate some level of natural fabrication variations, such as

1. Mask misalignment

2. Dust

3. Process parameters (e.g., lateral diffusion)

4. Rough 3D surfaces

WHY HAVE DESIGN RULES?


Basic CMOS Process Design Rule Set

8"A3 =

A – N-WELL RULES

B – ACTIVE RULES

C – POLY RULES


2"

2"

7"

H – METAL 2 RULES

J – METAL 3RULES

I – VIA2 RULES

G – VIA RULES

E – CONTACT RULES

F – METAL 1 RULES

1"


Potential Consequences of Design Rule Violations

Intended Transistor

Intended Unrelated Poly & DiffusionIntended Unrelated Poly & Diffusion

Catastrophic Error – Unintended misalignment cause Source-Drain short circuit

Catastrophic Error – Unintended overlap cause fabrication of a parasitic Transistor


Potential Consequences of Design Rule Violations

Intended Contact Alignment

Error – Unintended misalignment cause poor contact

Mask misalignmentBoth Metal 1 & Diffusion

Both Metal 1 & Diffusion

M1 contact to n-diffusionM1 contact to p-diffusion -> Contact MaskM1 contact to poly

Mn contact to Mn-1 for n = 2, 3,.. -> Via Mask

Contact and Via Masks


http://www.seas.upenn.edu/%7Eese570/manual_16.htm


D. Extract parasitic resistances and statistical extraction in later versions of Cadence.




poly_not_fet_to all-diff minimum spacing = 0.14 um

EXAMPLE Design Rule Checker Message

ese 570 fabrication of cmos integrated circuitsese570/spring2015/ese570... · 2015. 1. 22. ·...

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