450mm SOI wafers

Development of 450mm SOI substrates, related technologies and equipments

Agenda

• SOI, a key enabling substrate for next technology nodes

• Project perspectives and collaboration

• Update on EVG SOI bonding tool development

• Update on adixen AMC metrology equipment

• Conclusion

2 2013, Oct 9th

Moore’s law challenged: the scaling issue

Moore’s Law implies: – More functionalities per chip

– Less power per transistor

– Faster transistors

– For comparable chip cost

Processor,

Node N

n Million transistors

Scaling:

”Moore’s law”

Processor,

Node N+1

~2n Million transistors in

similar chip size

3 2013, Oct 9th

Upcoming: FinFET, FD-SOI

Next: how to continue Moore’s law beyond 10 nm ?

450mm, SOI and high-u materials as answers

High mobility active layer

4 2013, Oct 9th

Source: Intel via www.semi.org

>2x die per wafer

improves die cost

So

urc

e: P

rof.

Ta

ka

gi, IE

DM

20

11

450mm

F. A

llibe

rt, S

OI

Con

f.2

012

Strained SOI Ge and III-V

Smart CutTM to extend the CMOS roadmap

5 2013, Oct 9th

• Smart CutTM enables efficient device scaling across channel materials • Usable on any channel material, and multiple isolation options • Full flexibility of material and isolation type, thickness and uniformity

over multiple layers for future applications

Soitec FD-3D Wafer Soitec FD-3D,

thin BOX

Soitec FD-3D,

sSOI

Buried Oxide

Top Si layer

Base silicon

Buried Oxide

Top Si layer

Base silicon

Buried Oxide

Base silicon

Top strained-Si layer

Buried Oxide

Base silicon

Top Ge / III-V layer

Gate

SiliconFin

Buried Oxide

Substrate

Gate

SiliconFin

Buried Oxide

Substrate

Gate

Strained-SiFin

Buried Oxide

Substrate

Gate

Strained-SiFin

Buried Oxide

Substrate

Gate

Ge/III-VFin

Buried Oxide

Substrate

Gate

Ge/III-VFin

Buried Oxide

Substrate

Buried Oxide

Base silicon Ultra-thin BOX

Top Si layer

Base silicon

Gate

Silicon Fin

Ultra-thin BOX

Substrate

Substrate Options

Soitec FD-3D,

xxOI (non silicon)

Example devices

Smart CutTM process fitted for FinFet modules

6 2013, Oct 9th

Cost

Built-In

uniformity Multiple

Donors

450 mm

CATRENE SOI 450mm Consortium Update

• 8 Consortium Partner from 4 European countries

• Strong Support from Europe and Local Governments

7 2013, Oct 9th

SOI450: perspectives and collaboration from the European ecosystem to global cooperation

– The collaboration with G450C is fastly gaining momentum to:

– Reach initial technical objectives seeking potential access to some process equipments

– Increase the impact and dissemination of the equipment developed in SOI450 project

8 2013, Oct 9th

SOI450: technical update

ASM : 2nd SOI run oxidation

EVG: Bonding tool Installed in Soitec / under qualification

Altatech: manual 450mm inspection platform for metrology

Soitec: - New bulk (Sumco) validation - Cleaning improved on SWC - Implantation hardware upgraded

G450C: - Equipment access - Thermal treatment

Adixen: 1st APA450 to be delivered in June 2014 to G450C

Intel: link to Semi standard

9 2013, Oct 9th

SOI 450 mm Process Update

• Roughness

• TTV

• Polish Quality

• Oxide Quality

• Particles

• Bond SOI 450 mm Process focus in

2012/2013

Quality for FD-SOI

is defined

10 2013, Oct 9th

SOI 450mm Process Update

• Megasonic Cleaning System

• Vacuum Bonding System

• Installed and qualified in Soitec

• 2013 First fully automated 450 mm SOI Wafer bond

11 2013, Oct 9th

SOI 450 mm Process Update - Cleaner

• Hydrophilic Surface conditioning

• Megasonic Cleaning

• Particle Cleaning (SC1 / SC2)

• Bridge tool capability for 300 and 450mm wafer processing

• PWP Target for FD – SOI

• PWP 0 Adder @ > 50nm

courtesy of ProSys

• Continuous Cleaning process improvement could be established with EVG and Soitec

12 2013, Oct 9th

Reduced spinner chuck

speed improved significant Continuous cleaning trend

SOI 450 mm Process Update - Bonder

• HVM proofed mechanical wafer alignment

• Good Notch to Notch Alignment

• First fully automated Wafer Bond in 2013

Bonded Wafer Pair

Notch

13 2013, Oct 9th

IR Inspection Result

• No major voids could be observed

• High bond quality

• Good Wafer Alignment

Automated Bond IR Measurement Result 2013

2013, Oct 9th 14

adixen Pod Analyzer – APA principle

• Measuring Airborne Molecular Contamination (AMC)

• Amines, acids, VOC, NH3, H2O, HF

• Technology IMS, FID, CRDS

• FOUP and clean-room ambient

• ppb level within 5 minutes

2013, Oct 9th 15

SOI450 : APA300 test campaign

• AMC characterization in Soitec’s 300mm SOI production line

• using adixen APA300

• New derivation sampling on APA300 for off-line analyzers

• Sampling line measurements by CEA LETI

• Correlate APA results with other technologies

2013, Oct 9th 16

VOC mapping on different process steps FOUP cleaning efficiency on HF conta, May 2013, Soitec

APA450 development with

• Airborne Molecular Contamination critical at 450mm:

• Smaller nodes sensitive to AMC generated defects

• Longer Q-time inside carriers before inspection/litho steps

• Shipping issue : long time confinement inside MAC

• adixen developing new APA450 to test & analyze AMC at G450C

APA sampling simulation in 450mm FOUP, adixen

2013, Oct 9th 17

Outlook / Conclusion

• Continuous Cleaning Process Improvement

• Bond Quality Repeatability

• Automated IR Measurement capability

• SOI450 collaboration with G450C to leverage the value of both consortiums

2013, Oct 9th 18

CATRENE SOI 450 mm Consortium Update

• European Program for 450 mm

19 2013, Oct 9th