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ARM architecture

ARM architectures

The ARM logo

Designer ARM Holdings

Bits 32-bit, 64-bit

Introduced 1985

Design RISC

Type Register-Register

Branching Condition code

Open Proprietary

64/32-bit architecture

Introduced 2011

Version ARMv8-A

Encoding AArch64/A64 and AArch32/A32

use 32-bit instructions, T32(Thumb-2) uses mixed 16- and

32-bit instructions. ARMv7 user-

spacecompatibility[1]

Endianness Bi(little as default)

Extensions All mandatory: Thumb-2, NEON,

Jazelle, VFPv4-D16, VFPv4

Registers

General

purpose

31x 64-bit integer registers[1]plus

PC and SP, ELR, SPSR for

exception levels

Floating

point

32 128-bitregisters[1]for scalar

32- and 64-bit FPor SIMDFP or

integer; or cryptography

32-bit architectures (Cortex)Version ARMv8-R, ARMv7-A, ARMv7-R,

ARMv7E-M, ARMv7-M, ARMv6-M

Encoding 32-bit except Thumb-2 extensions

use mixed 16- and 32-bit

instructions.

Endianness Bi(little as default)

Extensions Thumb-2(mandatory since

ARMv7), NEON, Jazelle, FPv4-SP

Registers

General

purpose

16x 32-bit integer registers

including PC and SP

Floating

point

Up to 32 64-bit registers,[2]

SIMD/floating-point (optional)

32-bit architectures (legacy)Version ARMv6, ARMv5, ARMv4T,

ARMv3, ARMv2

Encoding 32-bit except Thumb extension

uses mixed 16- and 32-bit

instructions.

Endianness Bi(little as default) in ARMv3 and

above

Extensions Thumb, Jazelle

Registers

General

purpose

16x 32-bit integer registers

including PC (26-bit addressing in

older) and SP

From Wikipedia, the free encyclopedia

ARMis a family of instruction set architecturesfor computer processorsbased on a reduced

instruction set computing(RISC) architecturedeveloped by British company ARM Holdings.

A RISC-based computer design approach means ARM processors require significantly fewer

transistors than typical CISCx86processors in most personal computers. This approach reduces

costs, heat and power use. These are desirable traits for light, portable, battery-powered devices

including smartphones, laptops, tabletand notepad computers, and other embedded systems. A

simpler design facilitates more efficient multi-coreCPUs and higher core counts at lower cost,

providing improved energyefficiency for servers.[3][4][5]

ARM Holdings develops the instruction set and architecture for ARM-based products, but does not

manufacture products. The company periodically releases updates to its cores. Current cores from

ARM Holdings support a 32-bitaddress spaceand32-bit arithmetic; the ARMv8-A architecture,

announced in October 2011,[6]adds support for a 64-bitaddress space and 64-bit arithmetic.

Instructions for ARM Holdings' cores have 32 bits wide fixed-length instructions, but later versions of

the architecture also support a variable-length instruction set that provides both 32 and 16 bits wide

instructions for improved code density. Some cores can also provide hardware execution of Java

bytecodes.

ARM Holdings licensesthe chip designs and the ARM instruction set architectures to third parties,who design their own products that implement one of those architecturesincluding systems-on-

chips(SoC)that incorporate memory, interfaces, radios, etc. Currently, the widely used Cortex cores,

older "classic" cores, and specialized SecurCorecores variants are available for each of these to

include or exclude optional capabilities. Companiesthat make chips that implement an ARM

architecture include Apple, AppliedMicro, Atmel, Broadcom, Freescale Semiconductor, Nvidia, NXP,

Qualcomm, Samsung Electronics, ST Microelectronicsand Texas Instruments. Qualcomm introduces

new three-layer 3D chip stacking in their 2014-15 ARM SoCs such as in their first 20 nm64-bit octa-

core.[7]

Globally ARM is the most widely used instruction set architecture in terms of quantity

produced.[8][9][10][11][12] The low power consumption of ARM processors has made them very popular:

over 50 billion ARM processors have been produced as of 2014, thereof 10 billion in 2013[13]and

"ARM-based chips are found in nearly 60 percent of the worlds mobile devices". In 2008, 10 billion

chips had been produced.[14]The ARM architecture (32-bit) is the most widely used architecture in

mobile devices, and most popular 32-bit one in embedded systems.[15]In 2005, about 98% of all

mobile phones sold used at least one ARM processor.[16]According to ARM Holdings, in 2010 alone,

producers of chips based on ARM architectures reported shipments of 6.1 billion ARM-based

processors, representing 95% of smartphones, 35% of digital televisionsand set-top boxesand 10%

of mobile computers.

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Microprocessor-based system on a chip

The ARM1 second processor for theBBC Micro

Contents [hide]

1 History

1.1 Acorn RISC Machine: ARM2

1.2 Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale

2 Licensing

2.1 Core licence

2.2 Architectural licence

3 Cores

3.1 Example applications of ARM cores

4 32-bit architecture

4.1 CPU modes

4.2 Instruction set4.2.1 Arithmetic instructions

4.2.2 Registers

4.2.3 Conditional execution

4.2.4 Other features

4.2.5 Pipelines and other implementation issues

4.2.6 Coprocessors

4.3 Debugging

4.4 DSP enhancement instructions

4.5 SIMD extensions for multimedia

4.6 Jazelle

4.7 Thumb

4.8 Thumb-2

4.9 Thumb Execution Environment (ThumbEE)

4.10 Floating-point (VFP)

4.11 Advanced SIMD (NEON)4.12 Security extensions (TrustZone)

4.13 No-execute page protection

4.14 ARMv8-R

5 64/32-bit architecture

5.1 ARMv8-A

5.1.1 AArch64 features

6 Operating system support

6.1 32-bit operating systems

6.2 64-bit operating systems

7 See also

8 References

9 Further reading

10 External links

History [edit]The British computer manufacturer Acorn Computersfirst developed ARM in the 1980s to use

in its personal computers. Its first ARM-based products were coprocessor modules for the

BBC Microseries of computers. After the successful BBC Micro computer, Acorn Computers

considered how to move on from the relatively simple MOS Technology 6502processor to

address business markets like the one that was soon dominated by the IBM PC, launched in

1981. The Acorn Business Computer(ABC) plan required that a number of second processors

be made to work with the BBC Micro platform, but processors such as the Motorola 68000and

National Semiconductor 32016were considered unsuitable, and the 6502 was not powerful

enough for a graphics based user interface.[17]

After testing all available processors and finding them lacking, Acorn decided it needed a new

architecture. Inspired by white papers on the Berkeley RISCproject, Acorn considered

designing its own processor.[18]A visit to the Western Design Centerin Phoenix, where the6502 was being updated by what was effectively a single-person company, showed Acorn

engineers Steve Furberand Sophie Wilsonthey did not need massive resources and state-of-

the-art research and developmentfacilities.[19]

Wilson developed the instruction set, writing a simulation of the processor in BBC BASICthat

ran on a BBC Micro with a second 6502 processor. This convinced Acorn engineers they were

on the right track. Wilson approached Acorn's CEO, Hermann Hauser, and requested more

resources. Once he had approval, he assembled a small team to implement Wilson's model in

hardware.

Acorn RISC Machine: ARM2 [edit]

The official Acorn RISC Machineproject started in October 1983. They chose VLSI Technologyas the

silicon partner, as they were a source of ROMs and custom chips for Acorn. Wilson and Furber led the

design. They implemented it with a similar efficiency ethos as the 6502.[20]A key design goal was achieving

low-latency input/output (interrupt) handling like the 6502. The 6502's memory access architecture had let

developers produce fast machines without costly direct memory accesshardware.

VLSI produced the first ARM silicon on 26 April 1985. It worked the first time, and was known as ARM1 by

April 1985.[3]The first production systems named ARM2 were available the following year.

The first ARM application was as a second processor for the BBC Micro, where it helped in developing simulation software to finish development of

the support chips (VIDC, IOC, MEMC), and sped up the CAD softwareused in ARM2 development. Wilson subsequently rewrote BBC BASIC in
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Dieof an ARM610 microprocessor.

Dieof a STM32F103VGT6 ARMCortex-M3microcontroller with1 megabyteflash memorybySTMicroelectronics .

ARM assembly language. The in-depth knowledge gained from designing the instruction set enabled the code to be very dense, making ARM BBC

BASIC an extremely good test for any ARM emulator. The original aim of a pr incipally ARM-based computer was achieved in 1987 with the release

of the Acorn Archimedes.[21]In 1992, Acorn once more won the Queen's Award for Technologyfor the ARM.

The ARM2 featured a 32-bit data bus, 26-bitaddress space and 27 32-bit registers. Eight bits from the program counterregister were available for

other purposes; the top six bits (available because of the 26-bit address space), served as status flags, and the bottom two bits (available because

the program counter was always word-aligned), were used for setting modes. The address bus was extended to 32 bits in the ARM6, but program

code still had to lie within the first 64 MBof memory in 26-bit compatibility mode, due to the reserved bits for the status flags.[22]The ARM2 had a

transistor countof just 30,000, compared to Motorola's six-year-older 68000 model with around 40,000. [23]Much of this simplicity came from the

lack of microcode(which represents about one-quarter to one-third of the 68000) and from (like most CPUs of the day) not including any cache.

This simplicity enabled low power consumption, yet better performance than the Intel 80286. A successor, ARM3, was produced with a 4 KB

cache, which further improved performance.[24]

Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale [edit]

In the late 1980s Apple Computerand VLSI Technologystarted working with Acorn on newer versions of

the ARM core. In 1990, Acorn spun off the design team into a new company named Acorn RISC Machines

Ltd., which became ARM Ltd when its parent company, ARM Holdingsplc, floated on the London Stock

Exchangeand NASDAQin 1998.[25]

The new Apple-ARM work would eventually evolve into the ARM6, first released in early 1992. Apple used

the ARM6-based ARM610 as the basis for their Apple Newton PDA. In 1994, Acorn used the ARM610 as

the main central processing unit(CPU) in their RiscPCcomputers. DEClicensed the ARM6 architecture

and produced the StrongARM. At 233 MHz, this CPU drew only one watt ( newer versions draw far less).

This work was later passed to Intel as a par t of a lawsuit settlement, and Intel took the opportunity to

supplement their i960line with the StrongARM. Intel later developed its own high performance

implementation named XScale, which it has since sold to Marvell. Transistor count of the ARM core

remained essentially the same size throughout these changes; ARM2 had 30,000 transistors, while ARM6grew only to 35,000.[citation needed]

Licensing [edit]See also: ARM Holdings Licensees

Core licence [edit]

ARM Holdings' primary business is selling IP cores, which licensees use to create microcontrollers(MCUs)

and CPUsbased on those cores. The original design manufacturercombines the ARM core with other

parts to produce a complete CPU, typically one that can be built in existing semiconductor fabsat low cost

and still deliver substantial performance. The most successful implementation has been the ARM7TDMI

with hundreds of millions sold. Atmel has been a precursor design center in the ARM7TDMI-based

embedded system.

The ARM architectures used in smartphones, PDAs and other mobile devicesrange from ARMv5, used in

low-end devices, through ARMv6, to ARMv7 in current high-end devices. ARMv7 includes a hardware

floating-point unit(FPU), with improved speed compared to software-based floating-point.

In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition

with netbooks based on Intel Atom.[26]According to analyst firm IHS iSuppli, by 2015, ARM ICs may be in

23% of all laptops.[27]

ARM Holdings offers a variety of licensing terms, varying in cost and deliverables. ARM Holdings provides to all licensees an integratable hardware

description of the ARM core as well as complete software development toolset (compiler, debugger, software development kit) and the right to sell

manufactured siliconcontaining the ARM CPU.

SoC packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR plc's Quatro family, ST-Ericsson's Nova and

NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's OMAP products, Samsung's Hummingbird and Exynosproducts, Apple's A4, A5,

and A5X, and Freescale's i.MX.

Fablesslicensees, who wish to integrate an ARM core into their own chip design, are usually only interested in acquiring a ready-to-manufacture

verified IP core. For these customers, ARM Holdings delivers a gate netlistdescription of the chosen ARM core, along with an abstractedsimulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device

manufacturers (IDM) and foundry oper ators, choose to acquire the processor IP in synthesizableRTL(Verilog) form. With the synthesizable RTL,

the customer has the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exotic design goals not

otherwise possible with an unmodified netlist (high clock speed, very low power consumption, instruction set extensions, etc.). While ARM Holdings

does not grant the licensee the right to resell the ARM architecture itself, licensees may freely sell manufactured product such as chip devices,

evaluation boards and complete systems. Merchant foundriescan be a special case; not only are they allowed to sell finished silicon containing

ARM cores, they generally hold the right to re-manufacture ARM cores for other customers.

ARM Holdings prices its IP based on perceived value. Lower performing ARM cores typically have lower licence costs than higher performing

cores. In implementation terms, a synthesizable core costs more than a hard macro ( blackbox) core. Complicating price matters, a merchant

foundry that holds an ARM licence, such as Samsung or Fujitsu, can offer fab customers reduced licensing costs. In exchange for acquiring the

ARM core through the foundry's in-house design services, the customer can reduce or eliminate payment of ARM's upfront licence fee.

Compared to dedicated semiconductor foundries (such as TSMCand UMC) without in-house design services, Fu jitsu/Samsung charge two- to

three-times more per manufactured wafer.[citation needed]For low to mid volume applications, a design service foundry offers lower overall pricing

(through subsidisation of the licence fee). For high volume mass-produced parts, the long term cost reduction achievable through lower wafer

pricing reduces the impact of ARM's NRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice.

Architectural licence [edit]

Companies can also obtain an ARM architectural licencefor designing their own CPU cores using the ARM instruction sets. These cores must

comply fully with the ARM architecture.
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Tronsmart MK908, a Rockchip-based quad-core Android "mini PC",with a microSD card next to it for a sizecomparison.

Cores [edit]Main article: List of ARM cores

ArchitectureBit

widthCores designed by ARM Holdings Cores designed by third parties Cortex profile References

ARMv1 32/26 ARM1

ARMv2 32/26 ARM2, ARM3 Amber, STORM Open Soft Core[28]

ARMv3 32 ARM6, ARM7

ARMv4 32 ARM8 StrongARM, FA526

ARMv4T 32 ARM7TDMI, ARM9TDMI

ARMv5 32 ARM7EJ, ARM9E, ARM10E XScale, FA626TE, Feroceon, PJ1/Mohawk

ARMv6 32 ARM11

ARMv6-M 32ARM Cortex-M0, ARM Cortex-M0+, ARM

Cortex-M1Microcontroller

ARMv7-M 32 ARM Cortex-M3 Microcontroller

ARMv7E-M 32 ARM Cortex-M4 Microcontroller

ARMv7-R 32ARM Cortex-R4, ARM Cortex-R5, ARM

Cortex-R7Real-time

ARMv7-A 32

ARM Cortex-A5, ARM Cortex-A7, ARM

Cortex-A8, ARM Cortex-A9, ARM Cortex-

A12, ARM Cortex-A15, ARM Cortex-A17

Krait, Scorpion, PJ4/Sheeva, Apple A6/A6X(Swift ) Application

ARMv8-A 64/32 ARM Cortex-A53, ARM Cortex-A57[29] X-Gene, Denver, Apple A7(Cyclone), AMD K12,

Apple A8 Application[30][31]

ARMv8-R 32 No announcements yet Real-time [32][33]

A list of vendors who implement ARM cores in their design (application specific standard products (ASSP), microprocessor and microcontrollers) is

provided by ARM Holdings.[34]

Example applications of ARM cores [edit]

Main article: List of applications of ARM cores

ARM cores are used in a number of products, particularly PDAsand smartphones. Some computing

examples are the Microsoft Surface, Apple's iPad and ASUS Eee Pad Transformer. Others include Apple's

iPhone smartphone and iPod portable media player, Canon PowerShot A470digital camera, Nintendo DS

handheld game console and TomTomturn-by-turn navigation system.

In 2005, ARM Holdings took part in the development of Manchester University's computer, SpiNNaker,

which used ARM cores to simulate the human brain.

[35]

ARM chips are also used in Raspberry Pi, BeagleBoard, BeagleBone, PandaBoardand other single-board

computers, because they are very small, inexpensive and consume very little power.

32-bit architecture [edit]The 32-bit ARM architecture, such as ARMv7-A, is the most widely used architecture in mobile devices.[15]

From 1995, the ARM Architecture Reference Manual has been the primary source of documentation on the ARM processor architecture and

instruction set, distinguishing interfaces that all ARM processors are required to support (such as instruction semantics) from implementation

details that may vary. The architecture has evolved over time, and version seven of the architecture, ARMv7, that defines the architecture for the

first of the Cortex series of cores, defines three architecture "profiles":

A-profile, the "Application" p rofile: Cortex-Aseries

R-profile, the "Real-time" profile: Cortex-Rseries

M-profile, the "Microcontroller" profile: Cortex-Mseries

Although the architecture profiles were first defined for ARMv7, ARM subsequently defined the ARMv6-M architecture (used by the Cortex

M0/M0+/M1) as a subset of the ARMv7-M profile with fewer instructions.

CPU modes [edit]

Except in the M-profile, the 32-bit ARM architecture specifies several CPU modes, depending on the implemented architecture features. At any

moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically.[36]

User mode:The only non-privileged mode.

FIQ mode:A privileged mode that is entered whenever the processor accepts an FIQ interrupt.

IRQ mode:A privileged mode that is entered whenever the processor accepts an IRQ interrupt.

Supervisor (svc) mode:A privileged mode entered whenever the CPU is reset or when an SVC instruction is executed.

Abort mode:A privileged mode that is entered whenever a prefetch abort or data abort exception occurs.

Undefined mode:A privileged mode that is entered whenever an undefined instruction exception occurs.

System mode (ARMv4 and above):The only privileged mode that is not entered by an exception. It can only be entered by executing an

instruction that explicitly writes to the mode bits of the CPSR.Monitor mode (ARMv6 and ARMv7 Security Extensions, ARMv8 EL3):A monitor mode is introduced to support TrustZone extension in ARM

cores.

Hyp mode (ARMv7 Virtualization Extensions, ARMv8 EL2):A hypervisor mode that supports Popek and Goldberg virtualization requirements

for the non-secure operation of the CPU.[37][38]

Instruction set [edit]
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Registers across CPU modes

usr sys svc abt und irq fiq

R0

R1

R2

R3

R4

R5

R6

R7

R8 R8_fiq

R9 R9_fiq

R10 R10_fiq

R11 R11_fiq

R12 R12_fiq

R13 R13_svc R13_abt R13_und R13_irq R13_fiq

R14 R14_svc R14_abt R14_und R14_irq R14_fiq

R15

CPSR

SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq

The original (and subsequent) ARM implementation was hardwired without microcode, like the much simpler 8-bit6502processor used in prior

Acorn microcomputers.

The 32-bit ARM architecture (and the 64-bit architecture for the most part) includes the following RISC features:

Load/store architecture.

No support for unaligned memory accessesin the original version of the architecture. ARMv6 and later, except some microcontroller versions,

support unaligned accesses for half-word and single-word load/store instructions with some limitations, such as no guaranteed atomicity.[39][40]

Uniform 16 32-bit register file(including the Program Counter, Stack Pointer and the Link Register).

Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Later, the Thumb instruction set

added 16-bit instructions and increased code density.

Mostly single clock-cycle execution.

To compensate for the simpler design, compared with processors like the Intel 80286 and Motorola 68020, some additional design features wereused:

Conditional execution of most instructions reduces branch overhead and compensates for the lack of a branch predictor.

Arithmetic instructions alter condition codesonly when desired.

32-bit barrel shiftercan be used without performance penalty with most arithmetic instructions and address calculations.

Has powerful indexed addressing modes.

A link registersupports fast leaf function calls.

A simple, but fast, 2-priority-level interruptsubsystem has switched register banks.

Arithmetic instructions [edit]

The ARM supports add, subtract, and multiply instructions. The integer divide instructions are only implemented by ARM cores based on the

following ARM architectures:

ARMv7-M and ARMv7E-M architectures always include divide instructions.[41]

ARMv7-R architecture always includes divide instructions in the Thumb instruction set, but optionally in its 32-bit instruction set.[42]ARMv7-A architecture optionally includes the divide instructions. The instructions might not be implemented, or implemented only in the Thumb

instruction set, or implemented in both the Thumb and ARM instructions sets, or implemented if the Virtualization Extensions are included.[42]

Registers [edit]

Registers R0 through R7 are the same across a ll CPU modes; they are never

banked.

R13 and R14 are banked across all privileged CPU modes except system

mode. That is, each mode that can be entered because of an exception has its

own R13 and R14. These registers generally contain the stack pointer and the

return address from function calls, respectively.

Aliases:

R13 is also referred to as SP, the Stack Pointer.

R14 is also referred to as LR, the Link Register.R15 is also referred to as PC, the Program Counter.

CPSR has the following 32 bits. [43]

M (bits 04) is the processor mode bits.

T (bit 5) is the Thumb state bit.

F (bit 6) is the FIQ disable bit.

I (bit 7) is the IRQ disable bit.

A (bit 8) is the imprecise data abort d isable bit.

E (bit 9) is the data endianness bit.

IT (bits 1015 and 2526) is the if-then state bits.

GE (bits 1619) is the greater-than-or-equal-to bits.

DNM (bits 2023) is the do not modify bits.

J (bit 24) is the Java state bit.

Q (bit 27) is the sticky overflow bit.V (bit 28) is the overflow bit.

C (bit 29) is the carry/borrow/extend bit.

Z (bit 30) is the zero bit.

N (bit 31) is the negative/less than bit.

Conditional execution [edit]

Almost every ARM instruction has a conditional execution feature called predication, which is implemented with a 4-bit condition code selector (the

predicate). To allow for unconditional execution, one of the four-bit codes causes the instruction to be always executed. Most other CPU

architectures only have condition codes on branch instructions.

Though the predicate takes up four of the 32 bits in an instruction code, and thus cuts down significantly on the encoding bits available for

displacements in memory access instructions, it avoids branch instructions when generating code for small if statements. Apart from eliminating

the branch instructions themselves, this preserves the fetch/decode/execute pipeline at the cost of only one cycle per skipped instruction.

The standard example of conditional execution is the subtraction-based Euclidean algorithm:

In the C programming language, the loop is:

while(i !=j) { if(i >j) { i -=j; }
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else/* i < j (since i != j in while condition) */ { j -=i; } }

In ARM assembly, the loop is:

loop: CMP Ri,Rj ; set condition "NE" if (i != j), ; "GT" if (i > j), ; or "LT" if (i < j) SUBGT Ri,Ri,Rj ; if "GT" (Greater Than), i = i-j; SUBLT Rj,Rj,Ri ; if "LT" (Less Than), j = j-i; BNE loop ; if "NE" (Not Equal), then loop

which avoids the branches around the then and else clauses. If Ri and Rj are equal then neither of the SUB instructions will be executed,

eliminating the need for a conditional branch to implement the while check at the top of the loop, for example had SUBLE (less than or equal)

been used.

One of the ways that Thumb code provides a more dense encoding is to remove the four bit selector from non-branch instructions.

Other features [edit]

Another feature of the instruction setis the ability to fold shifts and rotates into the "data processing" (arithmetic, logical, and register-register

move) instructions, so that, for example, the C statement

a +=(j


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Some devices such as the ARM Cortex-A8 have a cut-down VFPLitemodule instead of a full VFP module, and require roughly ten times more

clock cycles per float operation.[56]Pre-ARMv8 architecture implemented floating-point/SIMD with the coprocessor interface. Other floating-point

and/or SIMD units found in ARM-based processors using the coprocessor interface include FPA, FPE, iwMMXt, some of which where implemented

in software by trapping but could have been implemented in hardware. They provide some of the same functionality as VFP but are not opcode-

compatible with it.

VFPv1

Obsolete

VFPv2

An optional extension to the ARM instruction set in the ARMv5TE, ARMv5TEJ and ARMv6 architectures. VFPv2 has 16 64-bit FPU registers.

VFPv3 or VFPv3-D32

Implemented on the Cortex-A8 and A9 ARMv7 processors. It is backwards compatible with VFPv2, except that it cannot trap floating-pointexceptions. VFPv3 has 32 64-bit FPU registers as standard, adds VCVT instructions to convert between scalar, float and double, adds

immediate mode to VMOV such that constants can be loaded into FPU registers.

VFPv3-D16

As above, but with only 16 64-bit FPU registers. Implemented on Cortex-R4 and R5 processors.

VFPv3-F16

Uncommon; it supports IEEE754-2008 half-precision (16-bit) floating point.

VFPv4 or VFPv4-D32

Implemented on the Cortex-A12 and A15 ARMv7 processors, Cortex-A7 optionally has VFPv4-D32 in the case of an FPU with NEON.[57]

VFPv4 has 32 64-bit FPU registers as standard, adds both half-precision extensions and fused multiply-accumulateinstructions to the features

of VFPv3.

VFPv4-D16

As above, but it has only 16 64-bit FPU registers. Implemented on Cortex-A5 and A7 processors (in case of an FPU without NEON[57]).

In DebianLinux and derivatives armhf(ARM hard float) refers to the ARMv7 architecture including the additional VFP3-D16 floating-point

hardware extension (and Thumb-2) above.

Software packages and cross-compiler tools use the armhf vs. arm/armel suffixes to differentiate.[58]

Advanced SIMD (NEON) [edit]

The Advanced SIMDextension (aka NEONor "MPE" Media Processing Engine) is a combined 64- and 128-bitSIMD instruction set that provides

standardized acceleration for media and signal processing applications. NEON is included in all Cortex-A8 devices but is optional in Cortex-A9

devices.[59]NEON can execute MP3 audio decoding on CPUs running at 10 MHz and can run the GSMadaptive multi-rate(AMR) speech codecat

no more than 13 MHz. It features a comprehensive instruction set, separate register files and independent execution hardware.[60]NEON supports

8-, 16-, 32- and 64-bit integer and single-precision (32-bit) floating-point data and SIMD operations for handling audio and video processing as

well as graphics and gaming processing. In NEON, the SIMD supports up to 16 operations at the same time. The NEON hardware shares the

same floating-point registers as used in VFP. Devices such as the ARM Cortex-A8 and Cortex-A9 support 128-bit vectors but will execute with

64 bits at a time,[56]whereas newer Cortex-A15 devices can execute 128 bits at a time.

ProjectNe10 is ARM's first open source project (from its inception). The Ne10 library is a set of common, useful functions written in both NEON

and C (for compatibility). The library was created to allow developers to use NEON optimizations without learning NEON but it also serves as a setof highly optimized NEON intrinsic and assembly code examples for common DSP, arithmetic and image pr ocessing routines. The code is

available on GitHub .

Security extensions (TrustZone) [edit]

The Security Extensions, marketed as TrustZone Technology, is in ARMv6KZ and later application profile architectures. It provides a low-cost

alternative to adding another dedicated security core to an SoC, by providing two virtual processors backed by hardware based access control.

This lets the application core switch between two states, referred to as worlds (to reduce confusion with other names for capability domains), in

order to prevent information from leaking from the more trusted world to the less trusted world. This world switch is generally orthogonal to all

other capabilities of the processor, thus each world can operate independently of the other while using the same core. Memory and peripherals

are then made aware of the operating world of the core and may use this to provide access control to secrets and code on the device.[61]

Typical applications of TrustZone Technology are to run a rich operating system in the less trusted world, and smaller security-specialized code in

the more trusted world (named TrustZone Software, a TrustZone optimised version of the Trusted Foundations Software developed by Trusted

Logic Mobility ), allowing much tighter digital rights managementfor controlling the use of media on ARM-based devices,[62]and preventing any

unapproved use of the device. Trusted Foundations Software was acquired by Gemalto. Giesecke & Devrient developed a rival implementationnamed Mobicore. In April 2012 ARM Gemalto and Giesecke & Devrient combined their TrustZone portfolios into a joint venture T rustonic.[63][64]

Open Virtualization[65]and T6[66]are open source implementations of the trusted world architecture for TrustZone.

In practice, since the specific implementation details of TrustZone are proprietary and have not been publicly disclosed for review, it is unclear

what level of assurance is provided for a given threat model.[citation needed]

No-execute page protection [edit]

As of ARMv6, the ARM architecture supports no-execute page protection, which is referred to as XN, for eXecute Never.[67]

ARMv8-R [edit]

The ARMv8-Rsub-architecture, announced after the ARMv8-A, shares some features except that it is not 64-bit.

64/32-bit architecture [edit]

ARMv8-A [edit]

Announced in October 2011,[6]ARMv8-A(often called ARMv8 although not all variants are 64-bit such as ARMv8-R) represents a fundamental

change to the ARM architecture. It adds a 64-bit architecture, named "AArch64", and a new "A64" instruction set. AArch64 provides user-space

compatibility with ARMv7-A ISA, the 32-bit architecture, therein referred to as "AArch32" and the old 32-bit instruction set, now named "A32". The

Thumb instruction sets are referred to as "T32" and have no 64-bit counterpart. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS,

and a 32-bit OS to be under the control of a 64-bit hypervisor.[1]ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012. [29]
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The Definitive Guide to the ARM Cortex-M3; 2nd Edition; Joseph Yiu; Newnes; 480 pages; 2009; ISBN 978-1-85617-963-8. (Online Sample)

The Definitive Guide to the ARM Cortex-M0; 1st Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN 978-0-12-385477-3. (Online Sample)

An Introduction To Reverse Engineering for Beginners" including ARM assembly; Dennis Yurichev; online book .

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Instructions: Thumb , ARM and Thumb-2 , Vector Floating PointOpcodes: Thumb , Thumb , ARM , ARM , GNU Assembler Directives .

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