electronic testing

7/26/2019 electronic testing

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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1

ssentials of

lectronic Testing

Vishwani D. Agrawal

Agere Systems, Murray Hill, NJ 4!4

"a#agere.com

Michael $. %ushnell

E&E De't., (utgers )ni"ersity

*iscataway, NJ +-4

ushnell#cai'.rutgers.e/u

*resente/ at the 0nternational Test

&onference 1++2
mailto:[email protected]:[email protected]


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*art 0

0NT(3D)&T03N T3

T ST0N


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V$S0 (eali5ation

*rocess

Determine re6uirements

7rite s'ecifications

Design synthesis an/ Verification

8aricatio

n

Manufacturing test

&hi's to custome

&ustomer9s nee/

Test /e"elo'ment


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Definitions

Design synthesis: i"en an 0;3 function, /e"elo'a 'roce/ure to manufacture a /e"ice using


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October 28, 2001 Essentials of Test: Agrawal & Bushnell

(eal Tests

%ase/ on analy5ale fault mo/els, whichmay not ma' on real /efects.

0ncom'lete co"erage of mo/ele/ faults /ue

to high com'le=ity. Some goo/ chi's are re>ecte/. The

fraction ?or 'ercentage@ of such chi's iscalle/ theyiel/ loss.

Some a/ chi's 'ass tests. The fraction?or 'ercentage@ of a/ chi's among all'assing chi's is calle/ the /efect le"el.


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October 28, 2001 Essentials of Test: Agrawal & Bushnell !

&osts of Testing

Design for testaility?D8T@

&hi' area o"erhea/ an/ yiel/ re/uction

*erformance o"erhea/

Software 'rocesses of test Test generation an/ fault simulation

Test 'rogramming an/ /eugging

Manufacturing test

Automatic test e6ui'ment?ATE@ ca'ital cost Test center o'erational cost


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October 28, 2001 Essentials of Test: Agrawal & Bushnell "

*resent an/ 8uture

Transistors;s6. cm 4 B 2+M 2 B C!M

*in count 2++ B !++ 2+ B 24-

&loc< rate ?MH5@ 1++ B C+ -C+ B 22++

*ower ?7atts@ 2.1 B 2 1 B !

8eature si5e ?micron@ +.1- B +.2- +.2C B +.2+

2!! B1++2 1++C B 1++

S0A (oa/ma', 0EEE S'ectrum, July 2!!!


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&ost of Manufacturing

Testing in 1+++AD

+.-B2.+H5, analog instruments,2,+14/igital 'ins: ATE 'urchase 'rice

F2.1M G 2,+14 = FC,+++ F4.11M

(unning cost ?fi"eByear linear /e'reciation@

De'reciation G Maintenance G 3'eration

F+.-4M G F+.+-M G F+.-M

F2.4C!M;year

Test cost ?14 hour ATE o'eration@

F2.4C!M;?C- = 14 = C,++@

4.- cents;secon/


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October 28, 2001 Essentials of Test: Agrawal & Bushnell #

&ourse 3utline

*art 0:

%asic conce'ts an/ /efinitions

Test 'rocess an/ ATE

Test economics an/ 'ro/uct 6uality

8ault mo/eling *art 00:

$ogic an/ fault simulation

&ominational circuit AT* Se6uential circuit AT*

Memory test

Analog test

Delay test an/ 0DD test

*art 000: Scan /esign

%0ST

%oun/ary scan an/ analog test us

System test an/ coreBase/ /esign


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V$S0 Testing *rocess

an/ 6ui'ment


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Testing *rinci'le


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Automatic Test

6ui'ment

&om'onents

&onsists of:

*owerful com'uter

*owerful C1Bit Digital Signal

*rocessor

?DS*@ for analog testing

Test *rogram ?written in highBle"el

language@ running on the com'uter

*roe Hea/ ?actually touches the

are or 'ac


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&haracteri5ation Test

7orstBcase test

&hoose test that 'asses;fails chi's

Select statistically significant sam'le

of chi's

(e'eat test for e"ery comination of 1G

en"ironmental "ariales

*lot results in Schmoo 'lot

Diagnose an/ correct /esign errors

&ontinue throughout 'ro/uction life of

chi's to im'ro"e /esign an/ 'rocess to

increase yiel/


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Schmoo *lot


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Manufacturing Test

Determines whether manufacture/ chi'

meets s'ecs

Must co"er high I of mo/ele/ faults

Must minimi5e test time ?to control cost@

No fault /iagnosis

Tests e"ery /e"ice on chi'

Test at s'ee/ of a''lication or s'ee/

guarantee/ y su''lier


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1!

%urnBin or Stress Test

*rocess:

Su>ect chi's to high tem'erature

o"erB"oltage su''ly, while running

'ro/uction tests

&atches:

0nfant mor talitycases K these are

/amage/ chi's that will fail in the first

1 /ays of o'eration K causes a/

/e"ices to actually fail efore chi's are

shi''e/ to customers

8rea< failuresK /e"ices ha"ing same

failure mechanisms as reliale /e"ices


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1"

Ty'es of

Manufacturing Tests

7afer sortor'roetest K /one efore

wafer is scrie/ an/ cut into chi's

0nclu/es test site characteri5ation K

s'ecific test /e"ices are chec


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SuBty'es of Tests

*arametricK measures electrical

'ro'erties of 'in electronics K /elay,

"oltages, currents, etc. K fast an/ chea'

8unctionalK use/ to co"er "ery high I

of mo/ele/ faults K test e"ery transistor

an/ wire in /igital circuits K long an/

e='ensi"e K main to'ic of tutorial


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1#

Two Different

Meanings of

8unctional Test

AT an/ Manufacturing 7orl/K any

"ectors a''lie/ to co"er high I of faults

/uring manufacturing test

Autom atic TestB*attern 4 eneration

7orl/K testing with"erification

"ectors , which /etermine whether

har/ware matches its s'ecification K

ty'ically ha"e low fault co"erage ?L +

I@


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Test S'ecifications

*lan

Test S'ecifications:

8unctional &haracteristics

Ty'e of De"ice )n/er Test?D)T@

*hysical &onstraints K *ac


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ADVANT ST Mo/el

T1 AT


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$T 8)S03N H8 AT


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Summary

*arametric tests K /etermine whether 'in

electronics system meets /igital logic "oltage,

current, an/ /elay time s'ecs

8unctional tests K /etermine whether internal

logic;analog suBsystems eha"e correctly

AT &ost *rolems

*in in/uctance ?e='ensi"e 'roing@

MultiBH5 fre6uencies

High 'in count ?2+14@

AT &ost (e/uction

MultiBSite Testing

D8T metho/s li


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Test conomics an/

*ro/uct uality


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conomics of Design

for Testaility ?D8T@

&onsi/er lifeBcycle cost D8T on chi'

may im'act the costs at oar/ an/

system le"els.

7eigh costs against enefits

&ost e=am'les: re/uce/ yiel/ /ue to area

o"erhea/, yiel/ loss /ue to nonBfunctional

tests

%enefit e=am'les: (e/uce/ AT cost /ue

to selfBtest, ine='ensi"e alternati"es to

urnBin test


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%enefits an/ &osts of

D8T

Design

an/ test

G ; B

G ; B

G ; B

8ariB

cation

G

G

G

Manuf.

Test

B

B

B

$e"el

&hi's

%oar/s

System

Maintenance

test

B

Diagnosis

an/ re'air

B

B

Ser"ice

interru'tion

B

G &ost increase

B &ost sa"ing

G;B &ost increase may alance cost re/uction


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V$S0 &hi' Oiel/

A manufacturing /efect is a finite chi' areawith electrically malfunctioning circuitrycause/ y errors in the farication 'rocess.

A chi' with no manufacturing /efect is calle/

a goo/ chi'. 8raction ?or 'ercentage@ of goo/ chi's

'ro/uce/ in a manufacturing 'rocess is calle/the yiel/. Oiel/ is /enote/ y symol O.

&ost of a chi':

&ost of faricating an/ testing a wafer

BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB

BBBBBBB

Oiel/ = Numer of chi' sites on the

wafer


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Defect $e"el or (e>ect

(atio

Defect le"el ?D$@ is the ratio of faultychi's among the chi's that 'ass tests.

D$ is measure/ as 'arts 'er million ?''m@.

D$ is a measure of the effecti"eness oftests.

D$ is a 6uantitati"e measure of themanufacture/ 'ro/uct 6uality. 8or

commercial V$S0 chi's a D$ greater than-++ ''m is consi/ere/ unacce'tale.


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Mo/ifie/ Oiel/

6uation

Three 'arameters:8ault /ensity, f a"erage numer of

stuc


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Defect $e"el

O

?

T

@ B

O

?2@

D$?T@ E BBBBBBBBBBBBBBBBBBBB

O ?T@

?

G

TAf

@

E 2 B

BBBBBBBBBBBBBBBBBBBB

?

G

Af

@

here T is the fault co"erage of tests,

Af

is the a"erage numer of faults on the

chi' of area A ,

is the fault clustering

'arameter. Af an/ are /etermine/ y

test /ata analysis.


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=am'le: S MAT &H

&hi'

%us interface controller AS0& faricate/an/ teste/ at 0%M, %urlington, Vermont

22,+++ e6ui"alent ?1Bin'ut NAND@ gates

C+4B'in 'ac


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Test &o"erage from

8ault Simulator

S

u

a

f

a

t

c

e

a

Vector numer


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Measure/ &hi' 8allout

Vector

numer

M

e

u

e

c

'

f

a

o


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Mo/el 8itting

O

?

T

@ for

Af

E 1.2 an/

E +.+C

Measure/ chi' fallout

O

?2@ E +.1C

&

'

f

a

o

a

c

m

'

e

2

O

?

T

@

Stuc


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&om'ute/ D$

Stuc


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Summary

V$S0 yiel/ /e'en/s on two 'rocess 'arameters,/efect /ensity ?/ @an/ clustering 'arameter ?@

Oiel/ /ro's as chi' area increases low yiel/means high cost

8ault co"erage measures the test 6uality Defect le"el ?D$@ or re>ect ratio is a measure of

chi' 6uality

D$ can e /etermine/ y an analysis of test

/ata 8or high 6uality: D$ L -++ ''m, fault co"erage

P !!I


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8ault Mo/eling


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7hy Mo/el 8aultsQ

0;3 function tests ina/e6uate for

manufacturing ?functionality "ersus

com'onent an/ interconnect testing@

(eal /efects ?often mechanical@ too

numerous an/ often not analy5ale

A fault mo/el i/entifies targets for testing

A fault mo/el ma


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Some (eal Defects in

&hi's

*rocessing /efects

Missing contact win/ows*arasitic transistors

3=i/e rea


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3ser"e/ *&% Defects

Defect classes

Shorts3'ens

Missing com'onents7rong com'onents(e"erse/ com'onents%ent lea/sAnalog s'ecificationsDigital logic*erformance ?timing@

3ccurrence fre6uency ?I@

-2 2

2C - - -

(ef.: J. %ateson, 0nB&ircuit Testing, Van Nostran/ (einhol/, 2!-.


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&ommon 8ault Mo/els

Single stuc


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Single Stuc


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8ault 6ui"alence

Numer of fault sites in a %oolean gate circuit R*0 G Rgates G R?fanout ranches@.

8ault e6ui"alence: Two faults f2 an/ f1 aree6ui"alent if all tests that /etect f2 also

/etect f1. 0f faults f2 an/ f1 are e6ui"alent then the

corres'on/ing faulty functions are i/entical. 8ault colla'sing: All single faults of a logic

circuits can e /i"i/e/ into /is>oint

e6ui"alence susets, where all faults in asuset are mutually e6ui"alent. A colla'se/fault set contains one fault from eache6ui"alence suset.


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6ui"alence (ules

sa+ sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+sa2

sa+sa2

sa+

sa+sa2

sa2

sa+

sa+

sa+sa2

sa2

sa2

AND

NAND

3(

N3(

70(

N3T

8AN3)T


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6ui"alence =am'le

sa+ sa2

sa+sa2

sa+ sa2

sa+sa2

sa+sa2

sa+sa2

sa+ sa2

sa+sa2

sa+sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+ sa2

sa+sa2

sa+sa2

sa+ sa2

8aults in re/remo"e/ ye6ui"alencecolla'sing

1+&olla'se ratio BBBBB +.1- C1


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8ault Dominance

0f all tests of some fault 82 /etect another fault81, then 81 is sai/ to /ominate 82.

Dominance fault colla'sing: 0f fault 81/ominates 82, then 81 is remo"e/ from thefault list.

7hen /ominance fault colla'sing is use/, it issufficient to consi/er only the in'ut faults of%oolean gates. See the ne=t e=am'le.

0n a tree circuit ?without fanouts@ *0 faults form

a /ominance colla'e/ fault set. 0f two faults /ominate each other then they are

e6ui"alent.


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Dominance =am'le

sBaB282

sBaB281 ++2

22+ +2+ +++

2+2 2++

+22

All tests of 81

3nly test of 82sBaB2

sBaB2sBaB2

sBaB+

A /ominance colla'se/ fault set


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&hec


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&lasses of Stuc


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Summary

8ault mo/els are analy5ale a''ro=imations of/efects an/ are essential for a testmetho/ology.

8or /igital logic single stuc


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*art 00

T ST M TH3DS

$ogic Simulation


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Simulation Define/

Definition: Simulation refers to mo/eling of a/esign, its function an/ 'erformance.

A software simulator is a com'uter 'rograman emulator is a har/ware simulator.

Simulation is use/ for /esign "erification: Vali/ate assum'tions Verify logic Verify 'erformance ?timing@

Ty'es of simulation: $ogic or switch le"el Timing &ircuit 8ault


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Simulation for

Verification

TrueB"alue

simulation

S'ecification

Design

?netlist@

0n'ut stimuli

om'ute/

res'onses

(es'onse

analysis

Synthesis

Design

changes


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Mo/eling for

Simulation

Mo/ules, loc


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October 28, 2001 Essentials of Test: Agrawal & Bushnell

=am'le: A 8ullBA//er

HA

in'uts: a,

out'uts: c, f

AN D: A2, ?a, @, ?c@

AN D: A1, ?/, e@, ?f@

3( : 32, ?a, @, ?/@

N3 T: N2, ?c@, ?e@

a

c

/

e

f

HA

8A

in'uts: A, %, &

out'uts: &arry, Sum

HA : HA 2, ?A, %@, ?D, @

HA : HA 1, ? , &@, ?8, Sum @

3( : 31, ?D, 8@, ?&arr y@

HA2

HA1

A

%

&

D

8

Sum

&arry


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&

a

$ogic Mo/el of M3S

&ircuit

&

c

&

V

DD

a

c

'M3S 8 Ts

nM3S 8 Ts

&

a

, &

an/ &

c

are

'arasitic

ca'acitances

D

c

D

a

c

a

D

a

an/ D

are

interconnect or

'ro'agation

/elays

D

c

is inertial /elay

of gate

D


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October 28, 2001 Essentials of Test: Agrawal & Bushnell "

3'tions for 0nertial

Delay

?simulation of a NAND gate@

a

c

?&M3S@

Time un its

-

c

?5ero /elay@

c

?unit /elay@

c

?multi'le /elay@

c

?minma= /elay@

0

n

$

c

m

u

a

o

min E1, ma= E-

riseE-, fallE-

Transient

region

)n


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Signal States

TwoBstates ?+, 2@ can e use/ for 'urely

cominational logic with 5eroB/elay. ThreeBstates ?+, 2, @ are essential for

timing ha5ar/s an/ for se6uential logicinitiali5ation.

8ourBstates ?+, 2, , @ are essential for M3S/e"ices. See e=am'le elow.

Analog signals are use/ for e=act timing of/igital logic an/ for analog circuits.

+

+

?hol/ 're"ious "alue@


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October 28, 2001 Essentials of Test: Agrawal & Bushnell #

Mo/eling $e"els

&ircuit

/escri'tion

*rogramming

languageBli


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October 28, 2001 Essentials of Test: Agrawal & Bushnell !0

TrueBValue Simulation

Algorithms

&om'ile/Bco/e simulation A''licale to 5eroB/elay cominational logic Also use/ for cycleBaccurate synchronous se6uential

circuits for logic "erification Efficient for highly acti"e circuits, ut inefficient for

lowBacti"ity circuits HighBle"el ?e.g., & language@ mo/els can e use/

E"entB/ri"en simulation 3nly gates or mo/ules with in'ut e"ents are

e"aluate/ ?e"ent means a signal change@

Delays can e accurately simulate/ for timing"erification

Efficient for lowBacti"ity circuits &an e e=ten/e/ for fault simulation


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&om'ile/B&o/e

Algorithm

Ste' 2: $e"eli5e cominational logic an/enco/e in a com'ilale 'rogramming language

Ste' 1: 0nitiali5e internal state "ariales ?fli'B

flo's@ Ste' C: 8or each in'ut "ector

Set 'rimary in'ut "ariales

(e'eat ?until stea/yBstate or ma=. iterations@

E=ecute com'ile/ co/e (e'ort or sa"e com'ute/ "ariales


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"entBDri"en Algorithm

? =am'le@

1

1

4

1

a E2

E2

c E2

+

/

E +

e

E2

f E+

g E2

Time, t

4

g

t E +

2

1

C

4

-

Sche/ule/

e"ents

c

E +

/

E 2,

e

E +

g

E +

f

E 2

g

E 2

Acti"ity

list

/, e

f, g

g

T

m

e

a


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fficiency of "entB

/ri"en Simulator

Simulates e"ents ?"alue changes@ only

S'ee/ u' o"er com'ile/Bco/e can e tentimes or more in large logic circuits aout+.2 to 2+I gates ecome acti"e for an in'utchange

$arge logic

loc< without

acti"ity

Stea/y +

+ to 2 e"ent

Stea/y +

?no e"ent@


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Summary

$ogic or trueB"alue simulators are essentialtools for /esign "erification.

Verification "ectors an/ e='ecte/ res'onsesare generate/ ?often manually@ from

s'ecifications. A logic simulator can e im'lemente/ using

either com'ile/Bco/e or e"entB/ri"en metho/.

*er "ector com'le=ity of a logic simulator is

a''ro=imately linear in circuit si5e. Mo/eling le"el /etermines the e"aluation

'roce/ures use/ in the simulator.


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8ault Simulation


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October 28, 2001 Essentials of Test: Agrawal & Bushnell !!

*rolem an/

Moti"ation

8ault simulation *rolem: i"en A circuit

A se6uence of test "ectors

A fault mo/el

Determine 8ault co"erage B fraction ?or 'ercentage@ of

mo/ele/ faults /etecte/ y test "ectors

Set of un/etecte/ faults

Moti"ation Determine test 6uality an/ in turn 'ro/uct 6uality

8in/ un/etecte/ fault targets to im'ro"e tests


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October 28, 2001 Essentials of Test: Agrawal & Bushnell !"

8ault simulator in a

V$S0 Design *rocess

Verifie/ /esignnetlist

Verificationin'ut stimuli

8ault simulator Test "ectors

Mo/ele/fault list

Testgenerator

Testcom'actor

8aultco"erage

Q

(emo"e

teste/ faultsDelete

"ectors

A// "ectors

$ow

A/e6uate

Sto'

8ault Simulation


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Scenario

&ircuit mo/el: mi=e/Ble"el Mostly logic with some switchBle"el for highBim'e/ance ?@ an/ i/irectional signals

HighBle"el mo/els ?memory, etc.@ with 'in faults

Signal states: logic Two ?+, 2@ or three ?+, 2, @ states for 'urely

%oolean logic circuits

8our states ?+, 2, , @ for se6uential M3S circuits

Timing:

eroB/elay for cominational an/ synchronouscircuits

Mostly unitB/elay for circuits with fee/acustification.

0f the 'roce/ure fails for all reachale *3s, then the

fault is untestale. 0f 2;+ or +;2 cannot e >ustifie/ at any *3, ut 2; or

+; can e >ustifie/, the the fault is 'otentially/etectale.


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&om'le=ity of AT*

Synchronous circuit BB All fli'Bflo's controlle/ y cloc


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&ycleB8ree &ircuits

&haracteri5e/ y asence of cycles amongfli'Bflo's an/ a se6uential /e'th, /se6.

/se6is the ma=imum numer of fli'Bflo's

on any 'ath etween *0 an/ *3. %oth goo/ an/ faulty circuits are

initiali5ale.

Test se6uence length for a fault is oun/e/

y /se6G 2.


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&ycleB8ree =am'le

82

81

8C

$e"el 2

1

82

81

8C

$e"el 2

1

C

C

/se6 C

s B gra'h

&ircuit

All faults are testale. See E=am'le ..


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&yclic &ircuit =am'le

8281&NT

Mo/uloBC counter

s B gra'h

82 81

A//ing 0nitiali5ing


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Har/ware

8281&NT

0nitiali5ale mo/uloBC counter

s B gra'h

82 81

&$(

sBaB+

sBaB2

sBaB2sBaB2 )ntestale fault*otentially /etectale fault


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%enchmar< &ircuits

&ircuit*0*388atesStructure

Se6. /e'thTotal faultsDetecte/ faults*otentially /etecte/ faults)ntestale faultsAan/one/ faults8ault co"erage ?I@8ault efficiency ?I@Ma=. se6uence lengthTotal test "ectorsentest &*) s ?S'arc 1@

s22! 24 24 2 -1!

&ycleBfree

4214121C! + C +

!!. 2++.+

C C2C 2+

s21C 24 24 2-+

&ycleBfree

42C--21C + 1 +

!4. 2++.+

C C+ 2-

s24 2! -C

&yclic

BB242C4 1 1

!C.2 !4.

14 -1-2!!42

s24!4 2! 4

&yclic

BB2-+2C! 1 C+ !

!2. !C.4

1 --!2!2C

SimulationBase/


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AT*

Difficulties with timeBframe metho/: $ong initiali5ation se6uence 0m'ossile initiali5ation with threeB"alue/ logic

?Section -.C.4@ &ircuit mo/eling limitations

Timing 'rolems K tests can cause races;ha5ar/s High com'le=ity 0na/e6uacy for asynchronous circuits

A/"antages of simulationBase/ metho/s

A/"ance/ fault simulation technology Accurate simulation mo/el e=ists for "erification Variety of tests K functional, heuristic, ran/om )se/ since early 2!+s

)sing 8ault Simulator


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8aultsimulator

Vector source:

8unctional ?testBench@,Heuristic ?wal


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%ac


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?As@

Theory of e"olution y natural selection ?Darwin, 2+!B1.@ &. (. Darwin, 3n the 3rigin of S'ecies y Means of Natural

Selection, $on/on: John Murray, 2-!.

J. H. Hollan/, A/a'tation in Natural an/ Artificial Systems,Ann Aror: )ni"ersity of Michigan *ress, 2!-.

D. E. ol/erg, enetic Algorithms in Search,

3'timi5ation, an/ Machine $earning, (ea/ing,Massachusetts: A//isonB7esley, 2!!.

*. Ma5um/er an/ E. M. (u/nic


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Strategate (esults

s241C s-C sC-!C1

Total faults 2,-2- 4,+C C!,+!4

Detecte/ faults 2,424 C,C! C-,2++

8ault co"erage !C.CI !.2I !.I

Test "ectors C,!4C 22,-2 1-

&*) time 2.C hrs. C. hrs. 2+.1 hrs.H* J1++ 1-M%

(ef.: M. S. Hsiao, E. M. (u/nic< an/ J. H. *atel, YDynamic State Tra"ersal for Se6uential &ircuit Test eneration,Z A&M Trans. on Design Automation of Electronic Systems ?T3DAES@,"ol. -, no. C, July 1+++.


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Summary

&ominational AT* algorithms are e=ten/e/: TimeBframe e='ansion unrolls time as cominational array NineB"alue/ logic system Justification "ia ac


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Memory Test


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Memory &ells *er &hi'

Test Time in Secon/s


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?Memory Si5e n % its@

n

2 M4 M2 M4 M1- M

2 1

n

+.++.1-2.+24.+C

2.224.4C21.!

n log1n

2.1-.-414.2

2+4.4-2.+

2!C1.C!!4.4

nC;1

4.--2-.42.1 hr

!.1 hrC.C hr

-.4 hr2-. hr

n1

2.C hr1!C.1 hr4!2.C hr

-++.+ hr21++!-!.! hr2!12-C-.4 hr24CC. hr

Si5e Numer of Test Algorithm 3'erations


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March Test Notation

r BB (ea/ a memory location

w BB 7rite a memory location

r+ BB (ea/ a + from a memory location

r2 BB (ea/ a 2 from a memory location

w+ BB 7rite a + to a memory location

w2 BB 7rite a 2 to a memory location

BB 7rite a 2 to a cell containing +

BB 7rite a + to a cell containing 2

March Test Notation


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?&ontinue/@

BB &om'lement the cell contents

BB 0ncreasing memory a//ressing

BB Decreasing memory a//ressing

BB ither increasing or /ecreasing


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MATSG March Test

M+:[ March element ?w+@ \

for cell :E + to n B 2 ?or any other or/er@ /o

write + to A Ucell

M2:[ March element ?r+, w2@ \

for cell :E + to n B 2 /o

rea/ A Ucell [ ='ecte/ "alue E +\

write 2 to A Ucell

M1:[March element ?r2, w+@ \

for cell :E n K 2 /own to + /o

rea/ A Ucell [ ='ecte/ "alue E 2 \

write + to A Ucell


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(e/uce/ 8unctional

8aults

SA8

T8

&8

N*S8

8aultStuc


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&ell fails to ma


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&ou'ling 8aults

&ou'ling 8ault

?&8@: Transition in it

>

causes

unwante/ change in it i

1B&ou' ling 8ault : 0n"ol"es 1 cells, s'ecial case

of


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8aults ?&8i/@

or transition in >sets cellito + or 2

&on/ition

: 8or all cou'le/ faults, each shoul/

e rea/ after a series of 'ossile &8i/s may

ha"e ha''ene/, such that the sensiti5e/ &8i/s

/o not mas< each other.

Asymmetr ic

: cou'le/ cell only /oes or

Symmetric

: cou'le/ cell /oes oth /ue to fault

L +], L 2], L +], L 2]


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A//ress Deco/er 8aults

A//ress /eco/ing error assum'tions:

Deco/er /oes not ecome se6uential

Same eha"ior /uring oth rea/ write

Multi'le AD8s must e teste/ for

Deco/ers ha"e &M3S stuc


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A%8

A%8

SA+

A%8

SA2 SA2GS&8

S&8

gg

8ault Hierarchy


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8ault 8re6uency


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3taine/ with Scanning lectron Microsco'e

&8in an/ T8 faults rarely occurre/

&luster+

21C4

-BB24

R De"ices24

2!2!

-1BB1

8ault classStuc


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with March Tests

March Tests can /etect A8s BB N*S8

Tests &annot

&on/itions for A8 /etection:

Nee/ ? r =, w =@

Nee/ ? r =, w =@

0n the following March tests,

a//ressing or/ers can e interchange/

0rre/un/ant March


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Test Summary

Algorithm

MATS

MATSG

MATSGG

MA(&H

MA(&H &^

MA(&H A

MA(&H O

MA(&H %

SA8

All

All

All

All

All

All

All

All

A8

Some

All

All

All

All

All

All

All

T8

All

All

All

All

All

All

&8

in

All

All

All

All

All

&8

i/

All

&8

/yn

All

S&8

All

$in


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&ell ?1, 2@ SA2 8ault

MATSG:

[ M+: ?w+@ M2: ?r+, w2@ M1: ?r2, w+@ \

Memory Testing


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Summary

Multi'le fault mo/els are essential

&omination of tests is essential:

March K S(AM an/ D(AM

N*S8 BB D(AM

D& *arametric BB %oth

A& *arametric BB %oth

0n/ucti"e 8ault A nalysis

is now re6uire/


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Analog Test

Mi=e/BSignal Testing


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*rolem

Differences from


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Digital Testing

Si5e not a 'rolem K at most 2++ com'onents

Much har/er analog /e"ice mo/eling

No wi/elyBacce'te/ analog fault mo/el

0nfinite signal range

Tolerances /e'en/ on 'rocess an/

measurement error

Tester ?AT @ intro/uces measurement error

Digital ; analog sustrate cou'ling noise

Asolute com'onent tolerances G;B 1+I,

relati"e G;B +.2I

Multi'le analog fault mo/el man/atory

No uni6ue signal flow /irection

*resentBDay Analog


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Testing Metho/s

S'ecificationBase/ ?functional@ tests

Main metho/ for analog K tractale an/

/oes not nee/ an analog fault mo/el

0ntractale for /igital BB R tests is huge

Structural AT* K use/ for /igital, >ust

eginning to e use/ for analog ?e=ists@

Se'arate test for functionality an/ timing

not 'ossile in analog circuit

*ossile in /igital circuit

Definitions


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AD& K

A;D con"erter

AT K Automatic Test 6ui'ment

DA& K D;A con"erter

D8T K Discrete 8ourier Transform

D)T K

De"iceB)n/erBTest

88T K 8ast 8ourier Transform

4litch Area BB area in DA& out'ut of glitching

'ulses

Jitter

K $owBle"el electrical noise K corru'ts

$S%9s, es'ecially 're"alent on con"erter

cloc


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$S% BB

$east Signif icant % it

?of con"erter@

Measurement

K (esult of measuring 3;*

analog 'arameter an/ 6uantifying it

Measurement rrorK 0ntro/uce/ y

measurement 'rocess

NonBDeterministic De"ice K All analog

circuit measurements are not re'eatale

/ue to D)T or tester measurement noise

*haseB$oc


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` 2! 0

7a"eform Synthesis


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` 2! 0

Nee/s sin = ; =?sinc@ correction K 8initesam'le wi/th

7a"eform Sam'ling


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` 2! 0

Sam'ling rate ] 2++


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A;D an/ D;A Test


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*arameters

A;D BB )ncertain ma' from in'ut /omain "oltages

into /igital "alue ?not so in D;A@

Two con"erters are N3T in"erses

Transmission 'arametersaffect multiBtone tests

4ain , signa lBtoB/istortion ratio , intermo/ulation

/istort ion

,

noise 'ow er ratio

,

/ifferential 'hase

shift , en"elo' /elay / istort ion

0ntrinsic 'a ram etersK &on"erter s'ecifications

8ull scale range?8S(@,gain , R its , static

linearity?/ifferential an/ integral@,ma=imum

cloc< rate

,

co/e form at

,

settl ing time

?D;A@,

glitch area?D;A@

0/eal Transfer

8unctions


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A;D &on"erter D;A &on"erter

3ffset rror


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ain rror


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D;A Transfer 8unction


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NonB$inearity rror

8lash A;D &on"erter


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Differential $inearity


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rror

Differential l inearity functionK How each

co/e ste' /iffers from i/eal or a"erage ste'

?y co/e numer@, as fraction of $S%

Sutract a"erage count for each co/e tally,

e='ress that in units of $S%s

(e'eat test wa"eform 2++ to 2-+ times, use

slow triangle wa"e to increase resolution

$inear Histogram an/

D$ of Bit AD&


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` 2! 0

D;A Differential Test


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8i=ture

` 2! 0Measure VyK V=/ifference, not asolute V=orVy

Summary

DS*Base/ tester has:


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7a"eform enerator

7a"eform Digiti5er High fre6uency cloc< with /i"i/ers for

synchroni5ation A;D an/ D;A Test *arameters

Transmission 0ntrinsic

A;D an/ D;A 8aults: offset, gain, nonBlinearityerrors

Measure/ y D$E, 0$E, DN$, an/ 0N$

A;D Test Histograms K static linear an/ sinusoi/al D;A Test KB Differential Test 8i=ture

DS*B%ase/ Testing


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uanti5ation rrorK 0ntro/uce/ into

measure/ signal y /iscrete sam'ling

uantum VoltageK &orres'on/s to fli' of

$S% of con"erter

Sing leBTone TestBB Test of D)T using only

one sinusoi/al tone

ToneK *ure sinusoi/ off, A , an/ 'hase

Transmission

?

*erformance

@

*arameter

BB

in/icates how channel with eme//e/

analog circuit affects multiBtone test

signal

)T* K

)nit test 'erio/

: >oint sam'ling

'erio/ for analog stimulus an/ res'onse

&oherent


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1!0

Measurement Metho/

)nit Test *erio/ is integration inter"al *

Has integral R of stimulus 'erio/s M

Has integral R of D)T out'ut 'erio/s N

Stimulus sam'ling are 'hase loc


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=am'le

Serial AD& in /igital tele'hone e=change

Sam'ling rate +++ s;s

Au/io fre6uency range C++ K C4++ H5

8t 2+++ H5 8

s +++ s;s

* -+ msec

M -+ cycles N 4++ sam'les

*rolem: Man/Nnot relati"ely 'rime

All sam'les fall on wa"eform at certain

'hases K sam'le only ;1-- &3D & ste's

&3D & Testing


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Solution

Set 8s 4++


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8t 2+1+ H5 8s +++ s;s

* )T* -+ msec 1+ H5

M -2 cycles N 4++ sam'les Man/Nnow relati"ely 'rime

All sam'les fall on wa"eform at /ifferent

'hases K sam'les all &3D & ste's

)nit Test *erio/

` 2! 0


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S'ectral Test of A;D

&on"erter


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` 2! 0

a on"er er

Test


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1!!

` 2! 0

oo/ A;D &on"erter

Test


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1!"

` 2! 0

S'ectral DS*B%ase/

Testing &om'onents


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` 2! 0

&orrelation Mo/el

` 2! 0


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1!#

&rossBcorrelationK com'are 1 /ifferent signals

Autocorrelation

K com'are 2 signal with itself

8ourier Voltmeter

2

st

*rinci'le


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1"0

` 2! 0

8or signals Aan/% , if *is infinite,( E + . 0f

*is finite an/ contains integer R cycles

of oth Aan/% , then crossBcorrelation (

E + , regar/less of 'hase or am'litu/e

8ourier Voltmeter

1

n/

*rinci'le


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` 2! 0

0f signals

A

an/

%

of same

f

are !+

oout of

'hase, an/ *contains an integerJR of

signal cycles, then crossBcorrelation ( E + ,

regar/less of am'litu/e or starting 'oint

&once'tual Discrete

8ourier Voltmeter


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` 2! 0

A;D &on"erter

S'ectrum


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` 2! 0Au/io source at 2+ H5 sam'le/ at 44.2


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` 2! 0

SingleBTone Test

=am'le


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` 2! 0

MultiBTone Test =am'le

` 2! 0


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1"!

Total Harmonic

Distortion ?THD@


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1""

Measures energy a''earing in

harmonics

?H1, HC, @of fun/amentaltone H2as I of energy in the

fun/amental fre6uency in res'onse

s'ectrum

THD

2+ G 2+ G G 2+

2+

H12+

HC2+

H2+2+

H2

1+

DS* Testing Summary


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Analog testing greatly increasing in

im'ortance

SystemBonBaBchi'

7ireless

*ersonal com'uter multiBme/ia

Automoti"e electronics

Me/icine

0nternet tele'hony

&D 'layers an/ au/io electronics

Analog testing N3T /eterministic li


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October 28, 2001 Essentials of Test: Agrawal & Bushnell 1"#

Delay Test

Delay Test Definition


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A circuit that 'asses /elay test must'ro/uce correct out'uts when in'uts area''lie/ an/ out'uts oser"e/ withs'ecifie/ timing.

8or a cominational or synchronousse6uential circuit, /elay test "erifies thelimits of /elay in cominational logic.

Delay test 'rolem for asynchronous

circuits is com'le= an/ not wellun/erstoo/.

Digital &ircuit Timing


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0

n

3

'

time

Transient

region

&loc< 'erio/

&om.

logic

3ut'ut

3ser"ation

instant

0n'ut

Signal

changes

Synchroni5e/

7ith cloc

are in/e'en/ent, in a

'roailities are in/e'en/ent, an/ that all

out'uts /

i>

are in/e'en/ent, in a< Bit M0S(,

*

al

E 2;?1

electronic testing

Documents