efficiency model of boost dc–dc pwm converters

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONSInt. J. Circ. Theor. Appl. 2005; 33:419–432Published online in Wiley InterScience (www.interscience.wiley.com). DOI: 10.1002/cta.329

E�ciency model of boost dc–dc PWM converters

W. Aloisi‡ and G. Palumbo∗;†;§

Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi; Universit�a degli Studi di Catania;Viale Andrea Doria 6; I-95125 Catania, Italy

SUMMARY

A thorough e�ciency analysis of a boost PWM converter taking into account the conduction losses,the diode power loss, the switching losses, the gate-drive loss and the capacitive switching loss, forboth continuous conduction mode and discontinuous conduction mode is presented. The analysis is ex-tended in the synchronous recti�cation case where a self driven transistor instead of the diode recti�eris adopted. The expressions of the converter e�ciency can be used to predict the circuit behaviour forboth a constant input and constant output voltage operation. The model has been validated using SPEC-TRE simulator and a 0.35 �m CMOS process, and error always lower than 2% were found. Copyright? 2005 John Wiley & Sons, Ltd.

KEY WORDS: pulse-width-modulated (PWM) converters; boost converter; continuous conduction mode(CCM); discontinuous conduction mode (DCM); e�ciency

1. INTRODUCTION

In portable systems, a number of low-voltage, low-power dc voltage supplies are needed. Toprovide these voltages from a single battery source, a voltage conversion is required. To allowportability and preserve battery capacity, the voltage conversion should be accomplished inminimal space and mass, and with the e�ciency as high as possible [1, 2].In this scenario, the boost dc–dc pulse width modulated (PWM) converters are widely used

to obtain a voltage higher than the battery source one. During the design step, the e�ciencyof such a converter can be accurately predicted only if the main dissipation sources areconsidered.Over the last two decades various approaches to modelling dc–dc PWM converters for

continuous conduction mode (CCM) and discontinuous conduction mode (DCM) have been

∗Correspondence to: G. Palumbo, Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Universit�a degliStudi di Catania; Viale Andrea Doria 6, I-95125 Catania, Italy.

†E-mail: [email protected]‡E-mail: [email protected]§IEEE Senior Member.

Received 7 October 2004Copyright ? 2005 John Wiley & Sons, Ltd. Revised 12 May 2005

420 W. ALOISI AND G. PALUMBO

developed, but some of them have focused special attention on small-signal model, only.For example, the models in References [3–10] are very useful to predict the high frequencybehaviour, but in Reference [3] parasitic components are neglected, in References [4–6] onlythe conduction losses were analysed and the ripple of the inductor current was neglected,while in References [7–10] switching losses were ignored. Moreover, a method for includingparasitic components in the buck-boost converter analysis have been considered in Reference[11] (results can be easily used for pure boost converters), but, unfortunately, capacitiveswitching losses, as well as, gate-drive loss, were ignored. Finally, it is worth noting that, inthe literature the e�ciency of a PWM converter is traditionally expressed as a function of theparasitic parameters and the duty cycle, D [1–11]. But, despite having duty cycle is important,since the designer is a�ected by the duty cycle range available, an expression of e�ciencyindependent on the duty cycle could be more useful, in order to e�ectively design a PWMswitching regulator. Indeed, to obtain a constant output voltage for a given input voltage anda speci�ed output current, the PWM converter duty cycle is regulated by the control circuit.To reach a complete e�ciency model and avoid the traditional modelling drawbacks, in

this paper a thorough e�ciency analysis of boost dc–dc PWM converter is carried out. Inparticular, relationships that take into account the conduction losses, the diode power loss,the switching losses, the gate-drive loss, and the capacitive switching loss both for CCM andDCM, are given. In addition, a complete e�ciency model in the synchronous recti�cationcase was provided. The expressions developed can be e�ectively used to predict the convertercircuit behaviour both for a constant input voltage and output voltage operation, and can helpthe designer to improve the converter performance.

2. ANALYSIS OF BOOST CONVERTER

The conventional schematic of a boost dc–dc PWM converter is shown in Figure 1. It consistsof an inductor, L, a power NMOS transistor, MN, which implements a controllable switch, adiode, D1, a �lter capacitor, C, and a load resistance, R.

2.1. Main assumptions

The analysis of the dc–dc boost PWM converter in Figure 1 is based on the followingassumptions:

(1) Transistor MN is modelled as a linear resistance, RDSN, and as an open circuit whenswitched on and switched o�, respectively.

(2) The diode is modelled as a series combination of a constant voltage source, VF, anda linear resistance, RF, in direct bias condition and as an open circuit in inverse biascondition. Moreover, switching losses in the diode are neglected.

(3) Passive components like inductors and capacitors are assumed to be linear, time in-variant and frequency independent. In addition, the equivalent series resistances (ESR),RL and RC , of the inductor and capacitor, respectively, are supposed to be independentfrom their operating temperature.

(4) The waveform of the drain to source voltage, vDS1, and the drain current, iD1, duringthe switching times are supposed to vary linearly.

(5) Power losses in the control circuit are neglected.

Copyright ? 2005 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2005; 33:419–432

EFFICIENCY MODEL OF BOOST DC–DC PWM CONVERTERS 421

VI VOMN

L D1

C R vPWM

iL

iS

iD

iCvL

Figure 1. PWM dc–dc boost converter.

VI VO

L

C

R

RCRDSN

VF RF

CX

RL

vL

iL

iF

iSiC

Figure 2. Boost converter equivalent circuit including the parasitic components.

The equivalent circuit of the boost converter taking into account the parasitic componentsis shown in Figure 2, where capacitor, CX , is the equivalent parasitic capacitance at the drainof transistor MN, and the other components were de�ned above.Assuming the transistor-switch is turned on and o� at the constant switching frequency,

fS =1=TS, the inductor voltage and the current waveforms of the converter operated at CCMand DCM are depicted in Figures 3(a) and (b), respectively.

2.2. Continuous conduction mode

Assume the boost converter to work in CCM. As far as the conduction loss in the inductoris concerned, we have

PRL=RLI 2L;RMS (1)

where IL;RMS is the root mean squared current through the inductor which can be evaluatedfollowing the approach suggested in Appendix A.1, that is:

IL;RMS =[(MIO)2 +

�I 2L12

]1=2(2)

being M the ratio between the dc output voltage VO and the input voltage VI, current IO thedc output current through the load resistance R (i.e. VO=R) and �IL the ripple of the inductorcurrent, given by

�IL=VOLfS

M − 1M 2 (3)



IaIL

tidtoff

0

vL

t

VI

VI-VO

ID=IO

iD

iS

IbiL

Ts

toffton

iC

IO

(a) (b)

t

vL

VI

0 t

VI-VO

0

iLIbIL0 t

IbIa0 t

iSIb

0 t

Ib

t0

iDIb

ID=IO

t0

0 t

iC

0 tton

Ts

IO

Figure 3. Boost PWM converter waveforms: (a) CCM; and (b) DCM.

The diode power loss is

PD=VFID + RFI 2D;RMS =VFIO +RFMI 2L;RMS (4)

The power loss in the ESR, RC , results

PRC =RCI 2C;RMS =RCMI 2L;RMS − RCI 2O (5)

The power loss in the transistor-switch, MN, depends on four dissipation sources. Specif-ically, the �rst cause is the conduction loss, PS, in the resistance RDSN, which, taking intoaccount the relationship (A7) in Appendix A.1, can be evaluated as follows:

PS =RDSI 2S;RMS =RDSNM − 1M

I 2L;RMS (6)



The second dissipation source is the switching loss, PSW, due to turn-on and turn-o� ofpower transistor and it is given by

PSW =12(VO + VF)

(MIO +

�IL2

)(trv + t�)fS (7)

where trv and t� are the rise and the fall times of drain-source voltage and drain current,respectively. Note that, in determining Equation (7) we have assumed some reasonable ap-proximations. Speci�cally, since the current at turn-on of transistor switch is smaller than theturn-o� one, only power loss on the turn-o� can be considered.The third contribution is the gate-drive loss, PG, due to raising and lowering the power

transistor gate, which results

PG =CGNV 2OfS (8)

being CGN the equivalent capacitance at the gate of power transistor MN. It is worth notingthat to obtain relationship (8) the power supply of the control circuit has been assumed equalto the output voltage. Finally, the last contribution is the capacitive switching loss, PX , dueto the equivalent parasitic capacitance CX , which is given by

PX =CXV 2OfS (9)

Collecting the terms in Equations (1)–(9), the e�ciency of the PWM boost converterresults

�CCM =PO

PO + PRL + PD + PRC + PS + PSW + PG + PX

={1 +

VFVO+RY IOVO

+RZVOIO

�I 2L12

+[12

(1 +

VFVO

) (M +

�IL2IO

)(trv + t�)

+VOIO(CGN + CX )

]fS

}−1(10)

where RY and RZ are de�ned as

RY = RLM 2 + RFM + (RC + RDSNM)(M − 1) (11)

RZ = RL + RDSNM − 1M

+RF + RCM

(12)

From relationship (10) it is possible to predict the converter e�ciency taking into ac-count all the dissipation sources. Moreover, if the switching frequency, fS, is low enough sothat the switching losses can be neglected, expression (10) can be rewritten neglecting theterm in square bracket and, hence, substituting (11)–(12) an approximate e�ciency, �CCM;A,



can be evaluated as

�CCM;A =

{1 +

VFVO

− RC IOVO +IOVO

[RL + RDSN +

VIVO(RF + RC − RDSN)

]

×[(VOVI

)2+(VO − VI)2V 2I12(LfSIOVO)2

]}−1(13)

2.3. Discontinuous conduction mode

The same procedure used in the previous section can be applied to model the converter inthe DCM. In particular, relationships (1), (4)–(6), and (8), (9) still hold, but now the rootmean squared current, IL;RMS, (see Appendix A.2) is given by

IL;RMS = IO

[89M (M − 1)VO

LfSIO

]1=4(14)

As regard the switching loss, PSW, again in this case the dominant contribution depends onthe turn-o� of the transistor switch. Consequently, we have

PSW ≈ 12(VO + VF)IO

√2VOLfSIO

M − 1M

(trv + t�) (15)

Therefore, the e�ciency results

�DCM =

{1 +

VFVO

− RC IOVO +RZIOVO

√89M (M − 1)VO

LfSIO

+

[(1 +

VFVO

) √VO

2LfSIOM − 1M

(trv + t�) +VOIO(CGN + CX )

]fS

}−1

(16)

where resistance RZ was de�ned in Equation (12).Neglecting the switching losses we can rewrite the e�ciency during the DCM

�DCM;A =

{1 +

VFVO

− RC IOVO +IOVO

[RL + RDSN +

VIVO(RF + RC − RDSN)

]VOVI

√89(VO − VI)LfSIO

}−1

(17)



3. SYNCHRONOUS RECTIFICATION

By inspection of the analysis in previous sections it is worth noting that in a conventional boostconverter an intrinsic limitation on the maximum reachable e�ciency exists. Speci�cally, evenif all other losses in the circuit are made negligible, the e�ciency is limited by the forward-bias diode voltage, VF. To avoid this drawback, the diode in Figure 1 can be replaced by aPMOS transistor proper controlled as shown in Figure 4. This topology is named synchronousrecti�er and can more e�ciently perform the same function as the topology with the diode.Unfortunately, by using the PMOS transistor determines an increases of capacitive switchingloss as well as the gate-drive loss.In order to predict the e�ciency in the circuit in Figure 4 we assume to model the PMOS

transistor, MP, like done for transistor MN. As a consequence, the expressions of e�ciencycan be simply obtained from few changes on those previously developed. Speci�cally, theexact e�ciency in CCM of the synchronous recti�er, �SY CCM, results

�SY CCM ={1 +

R′Y IOVO

+R′Z

VOIO�I 2L12

+[12

(M +

�IL2IO

)(trv + t�)

+VOIO(CGN + CGP + C ′

X )]fS

}−1(18)

where R′Y and R

′Z can be obtained from Equations (11) and (12), respectively, substituting

the diode resistance RF with the on-resistance of the PMOS transistor, RDSP. Moreover, CGPis the equivalent capacitance at the gate of MP and C ′

X is the equivalent parasitic capacitanceat node X.Also in this case, neglecting the switching losses, relationship (18) can be approximated

�SY CCM;A =

{1− RC IOVO +

IOVO

[RL + RDSN +

VIVO(RC + RDSP − RDSN)

]

×[(VOVI

)2+(VO − VI)2V 2I12(LfSIOVO)2

]}−1(19)

VI VOMN

L

C R vPWM

MP

vCTR

X

Figure 4. Synchronous recti�cation.



As far as the DCM is concerned, the exact e�ciency is given by

�SY DCM =

{1− RC IOVO +

R′Z IOVO

√89M (M − 1)VO

LfSIO+

[√VO

2LfSIOM − 1M

(trv + t�)

+VOIO(CGN + CGP + C ′

X )]fS

}−1

(20)

and the approximated relationship results

�SY DCM;A =

{1− RC IOVO +

IOVI

[RL + RDSN +

VIVO(RC + RDSP − RDSN)

]√89(VO − VI)LfSIO

}−1

(21)

4. VALIDATION RESULTS

In order to validate the models previously developed, two PWM dc–dc boost regulatorswere designed in a 0.35 �m standard CMOS technology whose technology main parame-ters are reported in Table I. The schematics of the �rst and the second regulator designed,are shown in Figures 5 and 6, respectively. In the former regulator there are three passiveexternal components (all the parts within the dotted region are integrated on the chip). Specif-ically, an inductor, L, equal to 10 �H (ESR=RL=100m�), a capacitor, C, equal to 47 �F(ESR=RC =20m�) and a Schottky diode (VF =230mV; RF =230m�) were considered.The second regulator designed put in practice the synchronous recti�cation and, hence, theexternal components are L and C, only. Component values for both the two regulators arereported in Table II. Moreover, the aspect ratio of power transistors, MN, and MP were setto (11 500 �m/0.5 �m) and (34 500 �m/0.5 �m), respectively, so that, the on resistance, RDSNand RDSP, are about 230 and 260m�, respectively. For both the regulators, the output voltageis held to a constant value of 5V by means of the control circuit and the switching frequencywas set to 230 kHz by an internal oscillator. In addition, the circuit control has a currentlimiter which set an upper bound equal to 1A for the maximum inductor current, and, �nally,a control to the maximum duty cycle of 80%, useful at start-up operation, was adopted. Notethat the power supply of the circuit control is provided by output voltage.

Table I. Main technology parameters.

Parameter Value

�n0Cox 175 �A=V2�p0Cox 60 �A=V2VTn0 0.55VVTp0 −0.65V



PWM BOOST REGULATOR

MN

PWM LATCH

R1

RL

BUFFER

Q

R S

OFF LIM

CLK ton

L

VI

OSCILLATOR

OFF DMAX

OFF OPAMP

NORMAL START

SOFT START

Disable LIM

VREF

R6

R7

R3

R4

R5

R2

CC

C

RC

VOUT

R

Figure 5. Schematic of PWM dc–dc boost regulator.

PWM BOOST REGULATOR

MN

PWM LATCH

R1BUFFER

Q

R S

OFF LIM

CLK ton OSCILLATOR

OFF DMAX

OFF OPAMP

NORMAL START

SOFT START

Disable LIM

VREF

R6

R7

R3

R4

R5

R2

CC

C

RC

VOUT

R

MP

BUFFER DELAY

RL

L

VI

Figure 6. Schematic of regulator with synchronous recti�cation.

The circuits were simulated using SPECTRE. Figure 7 shows the comparison betweenthe theoretical approximated e�ciency, �A, evaluated by Equations (13) and (17) (solidline), and the simulated e�ciency of the �rst regulator, versus output current, IO, with in-put voltage, VI, as parameter. Similarly, in Figure 8 is depicted the comparison between,�SY A, evaluated by (19) and (21), and the simulated e�ciency in the synchronous rec-ti�cation case. Note that, for each regulator, the values of simulated e�ciency were



Table II. Component values for the regulators.

Parameter Value

R1 3M�R2 22 k�R3 700 k�R4 208 k�R5 42 k�R6 824 k�R7 176 k�VREF 1.25V

VI = 1.2 V VI = 1.5 V

VI = 2 V

Discontinuous Mode

Continuous Mode

0.84

0.86

0.88

0.9

0.92

0.94

0.96

0.98

1

0 0.05 0.1 0.15 0.2

Effi

cien

cy

Output Current (A)

eta sim Vi=3V eta sim Vi=2.5V

eta sim Vi=2V eta sim Vi=1.5V eta sim Vi=1.2V

VI = 3 V

VI = 2.5 V

Figure 7. Comparison between the theoretical e�ciency, �A, (solid line) andthe simulated e�ciency of boost regulator.

evaluated at steady-state operation taking into account the power losses of the circuitcontrol, too.According to the analysis in the previous sections, the e�ciency of the converter operated

at DCM is always better than CCM one. Moreover, it is worth noting that, the expectedvalues of e�ciency from Equations (13) and (17), as well as, from Equations (19) and (21)in synchronous recti�cation case, agree very well with the simulated ones. Speci�cally, forthe �rst and the second regulator designed, the error in worst case is about 0.7 and 2%,respectively.



0.86

0.88

0.9

0.92

0.94

0.96

0.98

1

0 0.05 0.1 0.15 0.2

Effi

cien

cy

Output Current (A)

eta sim Vi=3 Veta sim Vi=2.5 V

eta sim Vi=2 Veta sim Vi=1.5 V

ContinuousMode

Discontinuous Mode

VI = 2.5 V

eta sim Vi=1.2 V

VI = 2 V

VI = 1.5 V

VI = 1.2 V

VI = 3 V

Figure 8. Comparison between the theoretical e�ciency, �SY;A, (solid line) and the simulated e�ciencyof boost regulator in the synchronous recti�cation case.

5. ANALYSIS AND DESIGN REMARKS

The model developed suggest some interesting consideration. In particular, from the analysispoint of view, it is simply to verify that both expressions (10) and (16), as well as (13)and (17) become the same at the boundary between the continuous and discontinuous modes,where the root mean squared current, IL;RMS, is equal to 2MIO=

√3. This is also veri�ed in the

synchronous recti�cation case for relationships (18) and (20), as well as (19) and (21).From the design point of view, it is worth noting that the e�ciency at DCM is always

better than CCM one. As a consequence, when the high e�ciency is the main goal, the PWMdc–dc converters must always operate in DCM. This means that for a given application, wherethe values of �lter element, L and C, the diode (if necessary), the switching frequency andboth the constant input and output voltage, were set, an upper bound for the output current,IO, must be speci�ed.

6. CONCLUSIONS

In this paper, a detailed e�ciency analysis of a boost dc–dc PWM converter, taking intoaccount all the chief sources of dissipation, for both CCM and DCM was carried out. In ad-dition, the analysis was extended in the synchronous recti�cation case. The proposed expres-sions agree very well with simulated ones, and, therefore, can help the designer for designinga PWM converter operated with the highest e�ciency for a given application.



Finally, it is worth noting that the proposed analysis represents an important, but not ex-haustive, step in this topic. Indeed, a further investigation will be needed in order to includea more accurate modelling of the inductor which account for the magnetic material used.

APPENDIX A

In this section the main equations of boost PWM converter both for CCM and DCM arederived. Speci�cally we have focused special attention on the averaged current and the rootmean squared current of inductor, switch, diode and capacitor. For simplicity, the characteri-zation procedure will presume the ideal boost converter in Figure 1 with the main waveforms,under steady-state conditions, depicted in Figure 3.

A.1. Boost converter equations for continuous conduction mode

Let us consider the boost converter in CCM. It is well know that the principle of inductorvolt-second balance states that the average value, or dc-component, of voltage applied acrossan ideal inductor must be zero. As a consequence, naming, M, the ratio between the dc outputvoltage, VO, and the dc input voltage, VI, for an ideal boost converter results

M =1

1−D (A1)

being, D, equal to ton=TS, the duty cycle. Referring to Figure 3(a), the ripple of the inductorcurrent, �IL, is equal to

�IL= Ib − Ia= VIL ton =VOLfS

(M − 1M 2

)(A2)

As far as the average inductor current, IL, is concerned, assuming ideal conditions (i.e.neglecting any power dissipations) we have

IL=MIO (A3)

where current, IO, is the averaged output current through the load resistance, R (i.e. VO=R).From Figure 3(a), the root mean squared current through the inductor, IL;RMS, can be

evaluated as follows:

IL;RMS =[1TS

∫ TS

0i2L(t) dt

]1=2

=

{1TS

∫ ton

0

(Ia +

�ILtont)2dt +

1TS

∫ TS

ton

[Ia +�IL

(TS − tTS − ton

)]2dt

}1=2

(A4)

Since the minimum inductor current, Ia, is equal to IL −�IL=2, solving (A4) we have

IL;RMS =[(MIO)2 +

�I 2L12

]1=2(A5)



Observing the power transistor current behaviour, it is apparent that its averaged value, IS,as well as its root mean squared, IS;RMS, are given by

IS =tonTS(Ia + Ib)2

=DIL=(M − 1)IO (A6)

IS;RMS =[1TS

∫ TS

0i2S(t) dt

]1=2=

[DI 2a + I

2b + IaIb3

]1=2=

(M − 1M

)1=2IL;RMS (A7)

Let us consider the current through the diode depicted in Figure 3(a). The principle ofcharge balance states that the average current that �ows through an ideal capacitor must bezero. Consequently, the average value of diode current is equal to the dc output current, thatis, ID= IO. Moreover, for the root mean squared current, ID;RMS we get

ID;RMS =[1TS

∫ TS

0i2D(t) dt

]1=2=

[(1−D) I

2a + I

2b + IaIb3

]1=2=

(1M

)1=2IL;RMS (A8)

Finally, the root mean squared current through the capacitor, IC;RMS, can be evaluated takinginto account that iC = iD − IO. As a consequence

IC;RMS =[1TS

∫ TS

0i2C(t) dt

]1=2= [I 2D;RMS − IO]1=2 =

(1MI 2L;RMS − I 2O

)1=2(A9)

A.2. Boost converter equations for discontinuous conduction mode

Let us assume the boost converter in DCM. In this situation, the main waveforms aredepicted in Figure 3(b). By using the above-mentioned principle of inductor volt-secondbalance we have

M =D+D1D1

(A10)

where D1 is equal to to� =TS.As regard the dc current of inductor, IL, the following can be found:

IL=MIO =D+D12

Ib (A11)

Also in this case, for the root mean squared current through the inductor, IL;RMS, we have

IL;RMS =[1TS

∫ TS

0i2L(t) dt

]1=2

=

{1TS

∫ ton

0

(Ibtont)2dt +

1TS

∫ ton+to�

ton

[Ib

(ton + to� − t

to�

)]2dt

}1=2

(A12)

Solving (A12) results

IL;RMS = IO

[89M (M − 1)VO

LfSIO

]1=4(A13)



As regard the currents of power switch, of diode and capacitor, it is simply to verifythat relationships (A6)–(A9) still hold, but now the root mean squared current IL;RMS is givenby (A13).

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efficiency model of boost dc–dc pwm converters

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