[ees04] university of bolton school of engineering …

[EES04]

UNIVERSITY OF BOLTON

SCHOOL OF ENGINEERING

BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING

SEMESTER TWO EXAMINATION 2017/2018

INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS

MODULE NO: EEE5002

Date: Wednesday 23rd May 2018 Time: 14:00 – 16:00

INSTRUCTIONS TO CANDIDATES: There are SIX questions.

Answer ANY FOUR questions.

All questions carry equal marks.

Marks for parts of questions are shown in brackets.

Time: 2 hours

CANDIDATES REQUIRE: Answer book Graph papers

of 12 School of Engineering University of Bolton BEng (Hons.) Electrical and Electronics Engineering Semester Two Examination 2017/8 EEE5002, Intermediate Digital Electronics and Communications

Q1.

a) If A (=1100) and B (=1001) are two unsigned variables. Find the value of the

following expressions when used inside a Verilog module:

(i) (A AND B)

(ii) (A && B)

(iii) (A | B)

(iv) (A || B)

(v) A<<2 (5 marks)

b) Consider the following design (Fig. 1.1) for a set-reset (S-R) latch, incorporating a

NOR and XNOR gate:

Fig. 1.1

(i) Fill in the function table below for Z and ~Z in this sequential circuit and

reproduce this table in your answer sheet.

X Y Z ~Z

0 0

0 1

1 0

1 1

(5 marks)

Question 1b continues over the page….

PLEASE TURN THE PAGE….


Question 1b continued….

(ii) From the completed function table, explain what is wrong with this latch.

How can the design be corrected?

(2.5 marks)

c) The circuits shown below (Fig. 1.2) are (a) D-latch & (b) D-flipflop with their

outputs connected to their inputs via an inverter. Draw the output waveforms of X

and Y assuming that they are both low initially and that CLK is a uniform square

wave and explain what seems to be the problem for circuit (a).

Fig. 1.2 (5 marks)

d) Consider the following two Verilog modules, m1 and m2 for a shift register:

module m1 (in, CLK, out); input in, CLK; output out; reg q1, q2, out; always @(posedge CLK) begin q1 = in; q2 = q1; out = q2; end endmodule

Question 1d continues over the page….



Question 1d continued….

module m2 (in, CLK, out);

input in, CLK;

output out;

reg q1, q2, out;

always @(posedge CLK)

begin

q1 <= in;

q2 <= q1;

out <= q2;

end

endmodule

(i) Describe what will be the output for each of the two modules m1 and m2.

(2.5 marks)

(ii) Now, considering positive edge triggered D flip flops, provide the

procedural statement based Verilog code for a 4-stage shift register.

(5 marks)

Total 25 marks



Q2.

a) For the state machine shown below (Fig. 2.1),

(i) Draw the equivalent Moore machine.

Fig. 2.1

(7.5 marks)

(ii) What would be the sequence of the state transition and the resulting output

sequence if the input is fixed to a constant bit stream of “1” for all cycles?

(2.5 marks)

b) A synchronous state machine has its state represented by the 2-bit number S1:0

and has a single input signal DIR. The current state is stored in a D-type register

whose input NS1:0 is defined by: NS1 = S0 ⊕ DIR and NS0 = 𝑆1 ⊕ 𝐷𝐼𝑅̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅.

Draw the state table for the synchronous machine.

(7.5 marks)

Question 2 continues over the page….



Question 2 continued….

c) In the circuit shown below (Fig. 2.2), the propagation delays associated with the

flip flop on the left (FF1) and the following logical block are tp and td, respectively.

The flip flop on right hand side (FF2) has setup and hold times of ts and th,

respectively. The circuit is being driven synchronously by a CLK signal “C” with a

time period T. For the circuit (Fig. 2.2):

Fig. 2.2

(i) Write down the setup and hold inequalities which apply to the FF2 in the

circuit.

(5 marks)

(ii) Find the maximum CLK frequency for the circuit if the timing parameters

are tp =2, ts =11, th = 5 and 7 ≤ td ≤ 23 (all times in ns).

(2.5 marks)

Total 25 marks



Q3.

A state machine that controls a vending machine has three input signals A, B and C

which go high for one clock cycle following the insertion of 10p, 20p and 50p coins

respectively. At most one of A, B and C is ever high at a time and their transitions

occur shortly after the CLOCK rising edge (positive edge of CLOCK). The state

machine has three outputs, X, Y and Z which respectively dispense a chocolate bar

and give 10p and 20p coins as change. Figure 5.1 below shows the state diagram

for the vending machine; the outputs are all low except where indicated on transition

arrows.

Fig. 5.1

(i) Deduce the cost of a chocolate bar.

(5 marks)

(ii) Complete the timing diagram shown in Figure 5.2 showing the sequence

of states, S2:0, as a decimal number and the waveforms of X, Y and Z.

Question 5 continues over the page….




Fig. 5.2

(10 marks)

(iii) Draw a revised state diagram for a state machine having the same input

and output signals as before but with a chocolate bar price of 40p. The outputs

Y and Z must never be high simultaneously.

(10 marks)

Total 25 marks



Q4.

Given that the characteristic equation for a J-K flip flop is given by:

𝑄+ = 𝐽�̅� + 𝐾𝑄

(i) Now, determine the flip flop input equations for both the JK flip flops (A and

B) of the following sequential circuit (Fig. 3.1). You may consider that the

output of the system is defined by the output of the flip flop themselves.

Fig. 3.1

(10 marks)

(ii) Determine the state table and state diagram for the above system.

(15 marks)

Total 25 marks



Q5.

a) Draw and describe the construction of a single static RAM memory cell

incorporating the SR -latch and associated gates.

(5 marks)

b) Determine the output of the (i) binary weighted D/A convertor shown below, if the

sequence shown (ii) is applied to the inputs (Fig. 4.1).

(i) (ii)

Fig. 4.1

(10 marks)

c) Explain following modulating techniques with diagrams.

(i) Amplitude Shift Keying (ASK)

(ii) Frequency Shift Keying (FSK)

(10 marks)

Total 25 marks



Q6. a) Explain why most memory integrated circuits have “tri-state” data output pins.

(5 marks)

b) A toggle flipflop (T-flipflop) changes state whenever its T input is high on the

positive edge of the CLK as shown in the timing diagram (Fig. 6.1). Describe how a

T-flipflop can be made using a D latch.

Fig. 6.1

(10 marks)

c) A sample-hold circuit is used to store the input voltage of a 12-bit A/D converter

during each conversion. The sample-hold circuit has an aperture uncertainty of 5 ns

and a leakage current of ±1 nA. The A/D converter has an input voltage range of ±10

V. If the input voltage is a sine wave of amplitude 10 V, calculate:

(i) the input frequency at which the aperture uncertainty will result in an error

of ±0.5 LSB.

(5 marks)

Question 6c continues over the page….




(ii) If the sample-hold circuit uses a storage capacitor of 200 pF, calculate how

long the input voltage can be held before it changes by 0.5 LSB due to the

leakage current.

(5 marks)

Total 25 marks

END OF QUESTIONS

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