EECS 20 Lecture 7 (January 31, 2001) Tom Henzinger Reactive Systems

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<ul><li> Slide 1 </li> <li> EECS 20 Lecture 7 (January 31, 2001) Tom Henzinger Reactive Systems </li> <li> Slide 2 </li> <li> Transducive or Combinational System Input ValueOutput Value transduciveSystem : Values Values </li> <li> Slide 3 </li> <li> Reactive or Sequential System Input SignalOutput Signal reactiveSystem : [ Time Values ] [ Time Values ] </li> <li> Slide 4 </li> <li> Reactive Systems 1Memory-free systems 2Delays 3Causality 4Finite-memory systems 5Infinite-memory systems </li> <li> Slide 5 </li> <li> A reactive system F : [ Time Values ] [ Time Values ] is memory-free iff there exists a transducive system f : Values Values such that x [ Time Values ], y Time, ( F (x) ) (y) = f ( x (y) ). </li> <li> Slide 6 </li> <li> Memory-free Reactive Systems Normalize Trunc Quantize Negate The identity system Id Every constant system Const Every composition of memory-free systems Every block-diagram composition of memory-free systems Every combinational circuit </li> <li> Slide 7 </li> <li> Id : [ Time Values ] [ Time Values ] such that x [ Time Values ], Id (x) = x. For every constant const Values, Const : [ Time Values ] [ Time Values ] such that x [ Time Values ], y Time, ( Const (x) ) (y) = const. The Identity System The Constant Systems </li> <li> Slide 8 </li> <li> FG Composition of Memory-free Systems fg If F and G are memory-free, </li> <li> Slide 9 </li> <li> FG Composition of Memory-free Systems fg If F and G are memory-free, then G F is memory-free. G F g f </li> <li> Slide 10 </li> <li> Negate And Block-Diagram Composition of Memory-free Systems Bools </li> <li> Slide 11 </li> <li> Negate And Block-Diagram Composition of Memory-free Systems again memory-free 1 2 </li> <li> Slide 12 </li> <li> The Delay System Delay: [ Time Values ] [ Time Values ] such that x [ Time Values ], y Time, ( Delay (x) ) (y) = ? if y &lt; 1 x (y-1) if y 1 { </li> <li> Slide 13 </li> <li> The Delay System Delay c : [ Time Values ] [ Time Values ] such that x [ Time Values ], y Time, ( Delay (x) ) (y) = c if y &lt; 1 x (y-1) if y 1 { </li> <li> Slide 14 </li> <li> Delay 0 (sin) : Reals + Reals such that y [0,1), Delay (sin) (y) = 0 and y [1, ), Delay (sin) (y) = sin (y-1). Delay 11 (id) : Reals + Reals such that y [0,1), Delay (id) (y) = 11 and y [1, ), Delay (id) (y) = y - 1. Continuous-Time Delay </li> <li> Slide 15 </li> <li> Delay 13 (id) : Nats 0 Nats 0 such that Delay (id) (0) = 13 and y Nats, Delay (id) (y) = y - 1. Delay true (alt) : Nats 0 Bools such that Delay (alt) = { (0, true), (1, false), (2, true), (3, false), }. Discrete-Time Delay </li> <li> Slide 16 </li> <li> Discrete-time delay over finite set of values : finite memory Continuous-time delay, or infinite set of values: infinite memory </li> <li> Slide 17 </li> <li> Block Diagram with Delay DtDt DfDf 2 1 1 2 Bools </li> <li> Slide 18 </li> <li> Block Diagram with Delay 2 1 1 2 t, f, t, f, t, t, t, t, DtDt DfDf </li> <li> Slide 19 </li> <li> Block Diagram with Delay 2 1 1 2 t, f, t, f, t, t, t, t, t t f DtDt DfDf </li> <li> Slide 20 </li> <li> Block Diagram with Delay 2 1 1 2 t, f, t, f, t, t, t, t, t, f, t t DtDt DfDf </li> <li> Slide 21 </li> <li> Block Diagram with Delay 2 1 1 2 t, f, t, f, t, t, t, t, t, f f, t f t t DtDt DfDf </li> <li> Slide 22 </li> <li> Block Diagram with Delay 2 1 1 2 t, f, t, f, t, t, t, t, t, f, f, t, f t DtDt DfDf </li> <li> Slide 23 </li> <li> Block Diagram with Delay 2 1 1 2 t, f, t, f, t, t, t, t, t, f, t, f, f, t, f, t, DtDt DfDf </li> <li> Slide 24 </li> <li> Block Diagram with Cycle DfDf Bools </li> <li> Slide 25 </li> <li> Block Diagram with Cycle t, f, t, DfDf </li> <li> Slide 26 </li> <li> Block Diagram with Cycle t, f, t, t fDfDf </li> <li> Slide 27 </li> <li> Block Diagram with Cycle t, f, t, t f,DfDf </li> <li> Slide 28 </li> <li> Block Diagram with Cycle t, f, t, f, t, t, DfDf </li> <li> Slide 29 </li> <li> Legal Transducive Block Diagrams -all components are transducive systems -no cycles e.g., combinational circuits </li> <li> Slide 30 </li> <li> Legal Reactive Block Diagrams -all components are memory-free or delay systems -every cycle contains at least one delay e.g., sequential circuits </li> <li> Slide 31 </li> <li> Discrete-Time Moving-Average DiscMovAvg: [ Nats 0 Reals ] [ Nats 0 Reals ] such that x [ Nats 0 Reals ], y Nats 0, ( DiscMovAvg (x) ) (y) = ? if y &lt; 2 1/3 ( x (y) + x (y-1) + x (y-2) ) if y 2 { </li> <li> Slide 32 </li> <li> Discrete-Time Moving-Average DiscMovAvg c : [ Nats 0 Reals ] [ Nats 0 Reals ] such that x [ Nats 0 Reals ], y Nats 0, ( DiscMovAvg (x) ) (y) = c if y &lt; 2 1/3 ( x (y) + x (y-1) + x (y-2) ) if y 2 { </li> <li> Slide 33 </li> <li> Continuous-Time Moving-Average ContMovAvg c : [ Reals + Reals ] [ Reals + Reals ] such that x [ Reals + Reals ], y Reals +, ( ContMovAvg (x) ) (y) = c if y &lt; 3 1/3 x (t) dt if y 3 { y y-3 </li> <li> Slide 34 </li> <li> Continuous-Time Moving-Average ContMovAvg c : [ Reals + Reals ] [ Reals + Reals ] such that x [ Reals + Reals ], y Reals +, ( ContMovAvg (x) ) (y) = c if y &lt; 3 1/3 x (t) dt if y 3 { y y-3 Integral is a quantifier that binds the variable t. </li> <li> Slide 35 </li> <li> Discrete-Time Moving-Average DiscMovAvg : [ Nats 0 Reals ] [ Nats 0 Reals ] such that x [ Nats 0 Reals ], y Nats 0, ( DiscMovAvg (x) ) (y) = c if y &lt; 2 1/3 x (t) if y 2 { y t = y-2 Sum is a quantifier that binds the variable t. </li> <li> Slide 36 </li> <li> A Noncausal Reactive System Predict: [ Time Bins ] [ Time Bins ] such that x [ Time Bins ], y Time, ( Predict (x) ) (y) = 1 if z Time, x (z) = 1 0 if z Time, x (z) = 0 { </li> <li> Slide 37 </li> <li> A reactive system F : [ Time Values ] [ Time Values ] is causal ( or implementable ) iff x, y [ Time Values ], z Time, if ( t Time, t z x (t) = y (t) ) then ( F (x) ) (z) = ( F (y) ) (z). </li> </ul>