EECS 20 Lecture 12 (February 12, 2001) Tom Henzinger Equivalence

Download EECS 20 Lecture 12 (February 12, 2001) Tom Henzinger Equivalence

Post on 22-Dec-2015

213 views

Category:

Documents

1 download

Embed Size (px)

TRANSCRIPT

<ul><li> Slide 1 </li> <li> EECS 20 Lecture 12 (February 12, 2001) Tom Henzinger Equivalence </li> <li> Slide 2 </li> <li> Quiz 1. Draw the transition diagram of the system Delay 0 : [ Nats 0 Bins ] [ Nats 0 Bins ] x [ Nats 0 Bins ], y Nats 0, ( Delay 0 (x)) (y) = 2. Draw the transition diagram of the system 0 if y = 0 x (y-1) if y &gt; 0 { Delay 0 </li> <li> Slide 3 </li> <li> State before time t : 0 if input at time t-1 was 0, or if t = 0 1 if input at time t-1 was 1 </li> <li> Slide 4 </li> <li> Delay 0 0 1 </li> <li> Slide 5 </li> <li> 0 1 </li> <li> Slide 6 </li> <li> 0 1 1 / 0 0 / 0 </li> <li> Slide 7 </li> <li> Delay 0 0 1 1 / 0 0 / 1 1 / 1 0 / 0 </li> <li> Slide 8 </li> <li> Delay 0 State: ( q1, q2 ) q2q1 </li> <li> Slide 9 </li> <li> Delay 0 q2q1 0,0 1,0 0,1 1,1 </li> <li> Slide 10 </li> <li> Delay 0 q2q1 0,0 1,0 0,1 1,1 </li> <li> Slide 11 </li> <li> Delay 0 q2q1 0,0 1,0 0,1 1,1 1 / 0 0 / 0 </li> <li> Slide 12 </li> <li> Delay 0 q2q1 0,0 1,0 0,1 1,1 1 / 0 0 / 0 0/00/0 1 / 0 </li> <li> Slide 13 </li> <li> Delay 0 q2q1 0,0 1,0 0,1 1,1 1 / 0 0 / 0 0/00/0 1 / 0 1/11/1 0 / 1 1 / 1 </li> <li> Slide 14 </li> <li> Delay 0 </li> <li> Slide 15 </li> <li> Well-formed ! </li> <li> Slide 16 </li> <li> Delay 0 Feedback Feedback : [ Nats 0 Unit ] [ Nats 0 Bins ] where Unit = { }. </li> <li> Slide 17 </li> <li> Delay 0 Feedback Inputs : Unit Outputs: Bins States: { 0, 1 } initialState = 0 q x output (q,x) nextState (q,x) 0 0 0 1 1 1 </li> <li> Slide 18 </li> <li> Delay 0 Feedback 0 1 / 0 / 1 </li> <li> Slide 19 </li> <li> Delay 0 Feedback Only one run ! Time 0 1 2 3 4 5 6 7 Input Output 0 0 0 0 0 0 0 0 State 0 0 0 0 0 0 0 0 0 </li> <li> Slide 20 </li> <li> Delay 0 Feedback 0 1 / 0 / 1 unreachable </li> <li> Slide 21 </li> <li> A state q of a state machine M is unreachable iff q occurs on no run of M ; that is, iff there is no path from the initial state of M to q. Unreachable states can be removed without changing the system (input/output function) implemented by M. </li> <li> Slide 22 </li> <li> Delay 0 Feedback 0 / 0 </li> <li> Slide 23 </li> <li> A more interesting system without inputs Counter Nats 0 Nats 0 0, 1, 2, 3, 4, 5, </li> <li> Slide 24 </li> <li> State-machine implementation of Counter Counter Nats 0 Nats 0 0, 1, 2, 3, 4, 5, Delay 0 Inc where n Nats 0, inc (n) = n + 1. </li> <li> Slide 25 </li> <li> Time 0 1 2 3 4 5 6 7 Input Output 0 1 2 3 4 5 6 7 State 0 1 2 3 4 5 6 7 8 One run Infinitely many states 04321 /0/0 /3/3 /2/2 /1/1 </li> <li> Slide 26 </li> <li> Yet another system without inputs ModCounter Nats 0 Nats 0 0, 1, 2, 3, 0, 1, 2, Delay 0 IncMod4 where n Nats 0, incMod4 (n) = ( n + 1 ) mod 4. </li> <li> Slide 27 </li> <li> Transition diagram of ModCounter 0321 /0/0 /3/3 /2/2 /1/1 </li> <li> Slide 28 </li> <li> A discrete-time reactive system can have many different state-machine implementations. </li> <li> Slide 29 </li> <li> Two state machines M1 and M2 are equivalent iff they implement the same system (input/output function); that is, iff 1. Inputs [M1] = Inputs [M2], 2. Outputs [M1] = Outputs [M2], and 3. x [ Nats 0 Inputs ], M1 (x) = M2 (x). [ Nats 0 Outputs ] </li> <li> Slide 30 </li> <li> Equivalent State Machines 0 1 1/01/0 0/10/1 1/11/10/00/0 M1 a b 1/01/0 0/10/1 1/11/10/00/0 M2 </li> <li> Slide 31 </li> <li> Equivalent State Machines 0 1 / 0 / 1 M1 0 / 0 M2 2 states 1 state </li> <li> Slide 32 </li> <li> Equivalent State Machines 0 1 1/01/0 0/10/1 1/11/10/00/0 M1 0 1 M2 i 1/01/0 0/10/1 1/11/1 0/00/0 0/00/0 1/01/0 3 states 2 states </li> <li> Slide 33 </li> <li> Theorem : Two state machines M1 and M2 are equivalent iff there exists a bisimulation between M1 and M2. A binary relation B between States [M1] and States [M2] ; that is, B States [M1] States [M2]. </li> <li> Slide 34 </li> <li> A binary relation B States [M1] States [M2] is a bisimulation iff 1. ( initialState [M1], initialState [M2] ) B and 2. p States [M1], q States [M2], if ( p, q ) B, then x Inputs [M1], output [M1] ( p, x ) = output [M2] ( q, x ) and ( nextState [M1] ( p, x ), nextState [M2] ( q, x) ) B. </li> <li> Slide 35 </li> <li> 0 1 1/01/0 0/10/1 1/11/10/00/0 M1 a b 1/01/0 0/10/1 1/11/10/00/0 M2 Bisimulation B = { ( 0, a ), ( 1, b) } </li> <li> Slide 36 </li> <li> / 0 / 1 M1 / 0 M2 Bisimulation B = { ( p 0, q 0 ) } p0p0 q0q0 p1p1 </li> <li> Slide 37 </li> <li> Bisimulation B = { ( p 0, q i ), ( p 0, q 0 ), ( p 1, q 1 ) } p0p0 1/01/0 0/10/1 1/11/10/00/0 M1 M2 1/01/0 0/10/1 1/11/1 0/00/0 0/00/0 1/01/0 q0q0 q1q1 qiqi p1p1 </li> <li> Slide 38 </li> <li> Equivalence between state machines: refers only to input and output signals. Bisimulation between state machines: refers to states. </li> <li> Slide 39 </li> <li> Why is bisimulation useful ? Equivalence says something about infinitely many possible input signals. For finite state machines, bisimulation says something about finitely many possible relationships between states. Bisimulation, therefore, is easier to check than equivalence. </li> </ul>