EE466/586EE466/586VLSI DesignVLSI DesignPartha Pande

School of EECSWashington State University

pande@eecs.wsu.edu

Lecture 28ROM

Read-Only Memory CellsRead-Only Memory Cells

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Diode ROM MOS ROM 1 MOS ROM 2

Diode ROMDiode ROM Does not isolate the bit line from the word line. All current required to charge the bit line capacitance

has to be provided by the word line and its drivers Better approach is to use an active device in the cell All output-driving current is provided by the transistor

MOS OR ROMMOS OR ROM

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Vbias

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Pull-down loads

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MOS NOR ROMMOS NOR ROM

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Pull-up devices

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Principle of Operations Bits are stored according to the presence or absence of a

transistor switch at each row-column intersection. A column goes low when any row, joined to the column with a

transistor, is raised to a high level. In normal operation, all but one row line is held low. When a selected wordline is raised to VDD , all transistors

present is that row are turned on. The columns to which they are connected are pulled low. The remaining columns with transistors missing in their

respective rows are held high by the pull-up or the load devices.

MOS NOR ROMMOS NOR ROM Pseudo-NMOS NOR gate with the word lines as

inputs. Under the normal operating conditions, only one of

the word line goes high, and, at most, one of the pull down devices is turned on.

To keep the cell size and bit line capacitance small, the pull-down device should be kept as close as possible to minimum size.

Resistance of the pull-up device must be larger than that of the pull-down to ensure an adequate low level.

Affects low-to-high transition

SizingSizing Difference between memory and logic design In the NOR ROM, we can trade off noise margin for

performance by letting the VOLof the bit line to be at a higher value.

The pull-up device can be widened to improve the low-to-high transition.

MOS NAND ROMMOS NAND ROM

All word lines high by default with exception of selected row

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Pull-up devices

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MOS NAND ROMMOS NAND ROM All transistors of the pull-down chain must be on to

produce a low value. All word lines are high by default with the exception of

the selected row, which is set to 0. Transistors on non selected rows are turned on If no transistor is present on the intersection between

the row and column of interest, then since all other transistors on the series chain are selected, the output is pulled low, and the stored value is 0.

When a transistor present at the intersection is turned off then the associated word line is brought low.

Results in a high output

Precharged MOS NOR ROMPrecharged MOS NOR ROM

PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.

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Precharge devices

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Non-Volatile MemoriesNon-Volatile MemoriesThe Floating-gate transistor (FAMOS)The Floating-gate transistor (FAMOS)

Floating gate

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Device cross-section Schematic symbol

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FAMOSFAMOS Extra polysilicon strip between the gate and the

channel. This strip is not connected to anything Applying a high voltage between the source and gate

terminals creates a high electric field Avalanche injection Electrons acquire sufficient energy and traverse

through the first oxide insulator, so that they get trapped on the floating gate

The trapping of electrons on the floating gate effectively drops voltage on the gate.

FAMOS (Cont’d)FAMOS (Cont’d)

The negative charge accumulated on the floating gate reduces the electric field over the oxide so that ultimately it becomes incapable of accelerating any more electrons.

Removing the voltage leaves the induced negative charge in place, which results in a negative voltage on the intermediate gate.

Effective increase in threshold voltage.

Floating-Gate Transistor ProgrammingFloating-Gate Transistor Programming

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25 V 0 V

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Removing programming voltage leaves charge trapped

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22.5 V 5 V

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Programming results in higher VT.

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10 V 5 V 20 V

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Avalanche injection

A “Programmable-Threshold” Transistor

“0”-state “1”-state

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“ON”

“OFF”

The charge injected onto the floating gate effectively shifts the I-V curves of the transistor.

FLOTOX EEPROMFLOTOX EEPROM

Floating gate

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n1 n1

FLOTOX transistorFowler-Nordheim I-V characteristic

20–30 nm

10 nm

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VGD

FLOTOX EEPROM (Cont’d)FLOTOX EEPROM (Cont’d)

FLOTOX (floating gate tunneling oxide) transistor injects or removes charges from a floating gate through tunneling.

Dielectric separating the floating gate from the channel and drain is reduced in thickness to about 10 nm or less

When a voltage of approx. 10 v is applied over the thin insulator, electrons travel to and from the floating gate through the Fowler-Nordheim tunneling.

Injecting electrons onto the floating gate raises the threshold, while the reverse operation reduces VT

EEPROM CellEEPROM Cell

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Absolute threshold controlis hardUnprogrammed transistor might be depletion 2 transistor cell

Flash Combination of EPROM and EEPROM. Most Flash EEPROM devices use the avalanche hot-

electron injection to program the device and use Fowler-Nordheim tunneling for erase.

Erasure is performed in bulk. Extra access transistor is not needed.

Basic Operations in a NOR Flash Memory―Erase

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12 VG

cell arrayBL0 BL1

open open

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Erase Operation

A 0 v gate voltage is applied, combined with a high voltage at the source

Electrons, if any, at the floating gate are ejected to the source by tunneling

All cells are erased simultaneously. The different initial values of the cell threshold

voltages, as well as variations in the oxide thickness, may cause variations in the threshold voltage at the end of the erase operation

Erase Operation

Before applying the erase pulse, all the cells in the array are programmed so that all the thresholds start approx. at the same value.

After that, an erase pulse of controlled width is applied. Subsequently the whole array is read to check whether or not the cells have been erased.

Basic Operations in a NOR Flash Memory―Write

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Write

A high voltage pulse is applied to the gate of the selected device.

If a “1” is applied to the drain at that time, hot electrons are generated and injected onto the floating gate, raising the threshold

If not, the floating gate remains in the previous state of no electrons, corresponding to a “0” state.

Basic Operations in a NOR Flash Memory―Read

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