ecen 248 lab 6 report

8/10/2019 ECEN 248 Lab 6 Report

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Lab 6: Introduction to Logic

Simulation and VerilogRebecca SontheimerECEN 248-511

TA: Mehanz Rahman

Date: October 22, 2013


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Objectives

The purpose of this lab was to introduce Verilog programming. Verilog programming is

an alternative to breadboarding when dealing with complex circuits. In this lab, I learned theproper syntax of the Verilog language, became familiar with the Verilog software, and learned

the proper way to describe a basic circuit and discover errors in pre-written code.

Design

Attached are the five different source codes that were used during the lab with commentsnotating what is occurring in each part of the code. Each source code is run using a given test

bench code that is used to check that the behavior of the circuit is correct and to create a

diagram that displays the waveforms of the described circuit.

Results

The waveforms that resulted from each source code are shown below. These waveforms

are created by running the given test bench code with the source code in order to generate avisual representation of the timing within a certain circuit.

Experiment 1

two_one_mux

Experiment 2


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add_sub

four_bit_mux


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full_adder

Experiment 3

four_bit_alu


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Conclusion

I successfully got all of my source code to work in a fairly timely manner, however this

lab was challenging. It took quite a bit of debugging to get the code to work properly. Once I hadthe correct code, the modules were able to link together and call previously created modules

much like how block diagrams work in regular circuit design. This allowed for the lab to buildupon itself as it progressed.

Post-lab Deliverables

1. All code is included in the design section of this lab report.

2. All screenshots of the waveform for each circuit and the outputs of each test bench file

are included in the results section of this lab report.

3. The test bench code for the 2:1 MUX puts the code that I have written through a series oftests that ensure the circuit follows the rules that it is supposed to follow. The code takes

in the inputs and outputs then tests them against the predetermined set of inputs and

outputs that have been determined by the truth table for the circuit. If one test fails then

the circuit was unsuccessful in one way or another and is in need of adjusting.4. Not all inputs are tested because that would imply that there would be hundreds of

outputs due to A and B both being 4-bit wires that need each possible set to be tested. It isnot required to test all inputs like that because only 16 sets of inputs are needed todemonstrate that the circuit works properly.

5. There are both disadvantages and advantages to using HDL instead of breadboarding.

Advantages of breadboarding include the fact that it is tangible and one is able to actually

see the connections being made. If this is a problem with a part of the circuit, one is ableto easily troubleshoot and test the circuit to find mistakes. However in HDL, one is able

to easily describe complex circuits that would not be possible with breadboarding

techniques because of size constraints. When trying to describe complex circuits, I preferVerilog because it does not require a mess of wires and can be much easier to understand.

When comparing schematics and HDL design, again I prefer HDL design because it is

concise, cleaner and easy to comprehend. However, schematics are great when you need

to see the physical flow of the circuit and want to see the thought process that went intothe circuit. The downside to HDL design is that it does not have a physical aspect to it.

6. Dataflow is based on function rather than just the structural elements and it uses operands

to describe the functions of the circuit instead of logic gates like the structural approach.The structural approach is shown best in the 2:1 and 4:1 MUX source codes and the

dataflow approach is exhibited in the full adder source code. I personally would prefer

the structural approach because if I was given a schematic and told to describe it using

Verilog, it would be easier to state the gates and their inputs and outputs rather than

trying to figure out the equations.

Feedback

1. I liked this lab because I feel as though I learned a lot about the basics of Verilog. The lab

manual was very helpful because it was like a tutorial with step-by-step instructions. Iliked that the lab also made sure you remembered how to do certain steps. There was

nothing that I disliked.


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2. All parts were very clear and informative.

3. The only suggestion I have would be to include a table of Verilog basics that could be

used for each lab; something that lists out the basic commands and rules.

ecen 248 lab 6 report

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