ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS

DESIGN

Lecture 5

Dr. Shi

Dept. of Electrical and Computer Engineering

How are Gates Implemented? By Metal-Oxide-Semiconductor Field

Effect Transistor (MOSFET) PMOS if source/drain are p-type

semiconductor NMOS if source/drain are n-type

semiconductor CMOS (complementary MOS)

GATE

SOURCE DRAIN

Oxide 5 nm

Gate length 20 nm

Hair=0.1mm1000um=1mm1000nm=1um

NMOS and PMOS

CMOS NOT gate

CMOS NAND Gate

Pull up:

Pull down:

CMOS NOR Gate

Pull up:

Pull down:

Example: Logic Realization

Realize the following logic:

Pull up

Pull down:

Negative Logic

NMOS Gates

NOT Gate

NAND and NOR Gates

Fan-in Fan-out and Buffers

High Fan in

Fan-in: Number of inputs Fan-out = Number of outputs

This gate has large fan in Large delay

High Fan out: Large switching time

Buffer

Each buffer can drive an output.

Just two inverters in series.

Tri-State Buffer

Transmission Gate

Example XOR